JP3130069B2 - Absolute encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder for outputting a detection position as absolute data, and in particular, it is possible to easily change an absolute origin and a counting direction of output data according to a user's request. The present invention relates to a simple absolute encoder.

[0002]

2. Description of the Related Art The absolute origin position of an absolute encoder that outputs a detection position as absolute data, for example, an absolute linear encoder or an absolute rotary encoder is usually built in a scale and a slider or a rotor and a stator. The origin and counting direction cannot be easily changed.

[0003] On the other hand, in a numerical control (NC) device and other equipment using the encoder, the origin position and the counting direction desired by the user usually change depending on the usage.

Therefore, it is conceivable to provide the encoder with a mechanism capable of mechanical adjustment, or to electrically switch the absolute origin position or the like by a jumper switch or the like.

[0005]

However, in any of the methods, after the encoder is assembled in the device, unless the encoder is once removed and disassembled, the absolute origin position is changed unless special measures are taken. Can not.

In addition, the latter method using a jumper switch or the like has a problem that many switches are required to finely adjust the absolute origin position, and the space is limited.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is possible to easily change the absolute origin and the counting direction desired by the user even after the encoder is assembled in the apparatus. It is an object of the present invention to provide a simple absolute encoder.

[0008]

According to the present invention, there is provided an absolute encoder for outputting a detected position as absolute data, wherein an absolute value detector for detecting an absolute position of a slider with a predetermined position determined by a scale pattern as an absolute origin, Input means for inputting the difference between the absolute origin of the scale pattern and the absolute origin desired by the user, and the counting direction desired by the user, the difference between the absolute origin,
A nonvolatile memory for storing the counting direction, a unit for inverting a direction in which the absolute value detector output increases or decreases when the counting direction of the absolute value detector is different from a counting direction desired by a user; Thus, the output of the absolute value detector that is increased or decreased in the counting direction desired by the user and the value stored in the nonvolatile memory are added, and the position desired by the user is defined as the absolute origin. Adder for obtaining absolute data and outputting the absolute data
The above-mentioned object is achieved by providing an output unit that performs the above-mentioned operations. In addition, the absolute encoder
The data output from the output means is serial data
This is done by the following. Absolute
In the remote encoder, data input from the input means is input.
The force is performed by serial data.

[0009]

According to the present invention, the absolute encoder is provided with a memory for storing the difference between the absolute origin of the scale pattern and the absolute origin desired by the user and the counting direction desired by the user. When the counting direction of the absolute value detector is different from the counting direction desired by the user, the increasing / decreasing direction of the output of the absolute value detector is reversed to match, and further, the difference of the absolute origin is added. .

Therefore, even after the encoder is incorporated in the device, the position of the absolute origin of the output data and the counting direction can be changed, and the position desired by the user is set as the absolute origin, and Absolute data that increases or decreases in the desired counting direction can be easily obtained.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[0012] absolute encoder 200 according to this embodiment, as shown in FIG. 1, as the absolute origin position which is determined by the scale pattern to detect the absolute position of the slider, outputs parallel signal D _n-1 ··· D ₀ And an electrically erasable non-volatile programmable lead for storing a difference between the absolute origin of the scale pattern and the absolute origin desired by the user, and a counting direction desired by the user. Only memory (EEPRO)
M) 220 and the absolute value detector 210 for reversing the direction of increase / decrease of the output of the absolute value detector 210 when the original counting direction of the absolute value detector 210 is different from the counting direction desired by the user. An exclusive OR gate 230 provided for each bit of the output, and the output (A _n−1 ·) of the absolute value detector 210 that is increased or decreased in the counting direction desired by the user by the exclusive OR gate 230. .. A ₀ ) and the value (B _n−1 ... B ₀ ) stored in the EEPROM 220 are added, and absolute data (S _n−1. · S ₀₎ and the adder 240 to obtain the parallel signal S _n-1 ··· S ₀ of absolute data of the adder 240 outputs, to the outside of the NC device 300 connected via a connector 310 The serial signal SOU
A parallel-in / serial-out shift register 250 for converting to T, and a shift clock for generating a shift clock SOCK for sequentially reading data from the shift register 250 in accordance with a data request signal REQ from the external NC device 300 A serial write signal SIN input from the generator 260 and an external absolute origin writing device 400 connected via the connector 410
Is converted into a parallel signal (P _n ... P ₀ ) suitable for internal processing in the absolute encoder 200, and the EEPROM 220 and the exclusive OR gate 23
And a serial-in / parallel-out shift register 270 for supplying 0.

As shown in FIGS. 2 and 3, for example, the absolute value detector 210 includes a low-resolution, long-wavelength capacitive absolute code pattern 11 to 13, 15, 16 and a high-resolution, short-wavelength photoelectric type. A scale 10 on which an incremental code pattern 14 is formed in the position detection direction;
A capacitance-type detector 20 for reading the capacitance-type absolute code at a low speed, and the capacitance-type detector 2
A capacitance detection circuit 30 that processes the output of 0 to generate a low-resolution, long-wavelength capacitance absolute signal.
And a register 40 for compiling the capacitance-type absolute data output from the capacitance-type detection circuit 30 in a time-division manner for each track to generate capacitance-type absolute data CAPDATA (parallel signal). A photoelectric detector 50 for reading a photoelectric incremental code at a high speed, and a photoelectric detector 60 for processing the output of the photoelectric detector 50 to generate a high-resolution, short-wavelength photoelectric incremental signal with high resolution; An interpolation circuit 70 for interpolating the photoelectric incremental signal to generate high-resolution, short-wavelength photoelectric absolute signals (parallel signals) b3 to b0, and a highest-order photoelectric absolute signal output from the interpolation circuit 70. A carry generator 80 for generating a carry signal to the least significant digit of the capacitive absolute signal based on the digit; By counting the capacitive absolute signal and the carry signal, an absolute signal (parallel signal) D _n-1 ··· D preset input with the up-down (UP / DN) counter 90 to create a significant digit of _0, the register A comparison circuit 100 for comparing the output of the up / down counter 90 with a capacitance type absolute signal of 40 outputs, generating an NG signal when the difference is large, and correcting the output of the counter 90; An output circuit 110 that outputs the counter 90 as a high-order digit signal and outputs the photoelectric absolute signal as a low-order digit signal; and a photoelectric absolute signal b0, b1 output from the interpolation circuit 70.
And an exclusive OR gate 130 for generating two-phase square wave signals A and B from the outside and outputting the signals to the outside.

As shown in detail in FIG. 4, on the scale 10, a first capacitance measuring coarse accuracy measuring device is arranged in descending order of wavelength.
A track 11, a second track 12 for measuring intermediate accuracy, and a third track 13 for measuring fine precision are formed. The third track 13 is further subdivided in the position detection direction into a fourth track of photoelectric type. (Photoelectric main scale) 14.

As described above, the third track of the capacitance type and the fourth track of the photoelectric type physically share the same track, so that the width of the entire scale 10 can be reduced. . In addition, it is also possible to make the capacitance type third track and the photoelectric type fourth track independent.

In FIG. 4, reference numeral 15 denotes a transmission electrode for the first track, and reference numeral 16 denotes a transmission electrode for the second track.

As shown in FIG. 3, the capacitance type detector 20 is provided with a pickup (slider) 22 which is opposed to the main scale 10 and is relatively moved in a position detecting direction. , A transmission (drive) electrode 24 to which, for example, an eight-phase AC signal is sequentially applied
And a receiving electrode 25 for the first track 11 and a receiving electrode 26 for the second track 12. When receiving a signal from the third track 13, both of the receiving electrodes 25 and 26 are used.

Here, the structure in which the photoelectric detector 50 is sandwiched by the capacitance type detector 20 is that the detection values of the upper three tracks 11 to 13 by the capacitance type are caused by disturbance due to temperature fluctuation or the like. This is to prevent deviation from the detected value of the lowest track 14 by the photoelectric method.

Hereinafter, the detection principle of the capacitance type detector 20 will be briefly described.

FIG. 5 schematically illustrates an electrode pattern of a capacitance type absolute encoder having a length measurement range for one track (third track 13 in the figure) for simplification of description. .

This capacitance type absolute encoder comprises the scale 10 and the pickup 22 which moves along the scale while maintaining a constant interval.

The scale 10 and the pickup 22 are
Each on an insulator such as a glass plate or a glass epoxy plate,
An electrode is formed by forming a conductive pattern by etching.

The voltage applied to the transmission electrode 24 on the pickup 22 is applied to the track electrode 13 on the scale 10.
Through the capacitive coupling. Further, the track electrode 13 on the scale 10 and the transmission electrode (for example, 15) are connected by wiring, and the transmission electrode 17 and the reception electrode (for example, 25) on the pickup 22 are connected by a capacitor. Therefore, a signal corresponding to the capacitance is obtained by the receiving electrode 25.

Since the pitch of each track on the scale 10 and the pitch of the transmission electrode 17 are different from each other, the inclination of the interconnecting wires differs depending on the position on the scale.

The transmitting electrode 24 is composed of, for example, an electrode group connected every eight electrodes, and the electrical connection between each electrode element can be freely selected by a circuit board.

The pitch of the receiving electrodes 25 is set to a length corresponding to one set of the transmitting electrodes 24, and the length of the receiving electrodes 25 in the detection direction is set to a length corresponding to a half wavelength (four) of the transmitting electrodes 24. ing.

Now, suppose that the positional relationship between the pickup 22 and the scale 10 is fixed, and eight kinds of interconnections of the transmission electrode 24 are sequentially provided, ie, first to fourth, second to fifth, third to sixth,. When the capacitance is changed and the capacitance between the transmission electrode 24 and the reception electrode 25 is measured in each case, the capacitance is equivalent to each point shifted in phase by 45 ° on a one-cycle sine wave. Conversely, select a specific connection and
When the relative position of the and the scale 10 is moved, it can be seen that they move on the same sine wave in accordance with the movement of the pickup 22. This is the detection principle of the capacitance type encoder, and the determination of the moving direction is performed by changing the combination of the transmission electrodes 24 and confirming the direction of the phase change.

By changing the connection of the transmitting electrodes in this manner, a sine (SIN) wave and a cosine (C
Since the capacitance waveform of the OS) wave is obtained, the value of the position X can be obtained by calculating tan ^-1 (sin X / cos X) in the capacitance type detection circuit 30.

The detailed structure and operation of the capacitance type detector are described in Japanese Patent Application No. Hei 2-132434 previously proposed by the applicant.
And the detailed description thereof is omitted in Japanese Patent Application No. 2-169654.

The register 40 includes the capacitance type detector 2
It has a function of synthesizing and outputting signals obtained from the three tracks 0.

That is, the data for the upper three tracks obtained by the capacitance type detection circuit 30 has an overlapping portion of, for example, 3 bits each as shown in FIG. this is,
This is an overlap of margin bits for preventing an error in each track and a quantization error from making it impossible to accurately designate a lower track. Therefore, the register 40 receives the data corresponding to each track in a time-division manner, confirms that the overlapping portions are within a predetermined difference from each other, and outputs the combined data.

When the data of the overlapping portion is different,
For example, lower data can be adopted as a correct value. At this time, if the difference between the data of the overlapping portions is larger than a specified value, it can be interpreted as the occurrence of an abnormality and an error signal can be generated.

As shown in detail in FIG. 8, the photoelectric detector 50 comprises a pickup 22 of the capacitance type detector.
A slit plate (slider) 52 that moves integrally with the pickup 22, and an opening 22 A formed in the center of the pickup 22.
A light emitting diode 5 having a characteristic close to a point light source for irradiating the fourth track 14 (common to the third track 13) on the scale 10 with diffused light through the scale 10 (see FIG. 3).
4 and four photos for receiving light modulated by the four index scales 53 on the slit plate 52, which are reflected by the surface of the scale 10 or the fourth track 14 and shifted by 90 ° from each other. And a transistor 56.

In this embodiment, since the sine waves having different phases are obtained by one light source and four light receiving elements, the sine waves having a predetermined pitch which is stable against the gap fluctuation between the slit plate 52 and the scale 10 and the temperature fluctuation. Is obtained.

The detailed structure and operation of the photoelectric detector 50 and the photoelectric detector 60 which processes the output of the photoelectric detector 50 and generates a two-phase sine wave signal having a phase shift of 90 ° are disclosed in Since it is disclosed in -187413 and the like, the description is omitted.

The detailed configuration and operation of the interpolation circuit 70 are described in Japanese Patent Application Laid-Open No. 1-212314, so that detailed description will be omitted.

The interpolation circuit 70 converts a two-phase square wave signal having a 90 ° phase difference obtained by shaping the analog output waveform of the photoelectric detection circuit 60 into a resistor as shown in the upper part of FIG. By the division, signals b0 to b3 of a binary (BIN) code as shown in the lower part of FIG. 9 are finally obtained. The binary code signals b3 to b0 are output from the carry generator 80.
Is input to

The carry generator 80 is constructed, for example, as shown in FIG. 10, and as shown in a time chart of FIG. 11, a rising edge detecting circuit 82 and a falling edge detecting circuit 84 including a common delay element 86. , The edge of the most significant digit signal b3 is observed, and the direction discrimination signal UP and the count pulse signal CP are output via the RS-F / F88 or the like.

The count pulse generated by the carry generator 80 is input to the up / down counter 90, and digit data exceeding the absolute data generated by the photoelectric detection circuit 60 is generated. As shown in FIG. 7, the data of this digit is also created in the register 40 of the capacitance type detection unit, so that it is corrected by comparing it.

That is, the value of the register 40 (input A) and the value of the counter 90 (input B) are compared in the comparison circuit 100 having a configuration as shown in FIG. Specifically, the inputs A and B to be compared are added to an adder (subtractor) 102.
, And the result is determined by the decoder 104.

FIG. 13 shows an example of a truth table of the decoder 104. In this truth table, the rising edge detection circuit 106 generates an NG signal when the difference is ± 2 or more. . The counter 90 is preset by this NG signal, and data is loaded again.

The rising edge detection circuit 106 comprising two D-type (D-) F / Fs and an AND gate after the decoder 104 detects the generation of an NG signal (LD signal) input to the counter 90. , Appropriate width (Clock C
It is used for the purpose of converting the pulse signal into a pulse signal having the same period as that of K2.

FIG. 14 is a time chart of the comparison circuit 100.

The comparison circuit 100 allows the counter 90
Is different from the capacitance type absolute data for detecting the higher absolute value, the absolute value is automatically updated to the correct absolute value.

The function of the comparison circuit 100 can be easily realized by software operation by a microcomputer.

The absolute origin writing device 400, as shown in FIG.
And a serial data / serial clock generator 420 for sending the absolute origin writing information for writing the counting direction to the serial in-parallel out shift register 270 of the absolute encoder 200 in a predetermined order, and to the EEPROM 220. And a write switch SW1 for permitting the writing of data.

The serial data / serial clock generator 420 is provided with a setting switch SW for setting a difference between absolute origins and a counting direction as shown in FIG.
2, a paralein-serial-out shift register 430 in which write information set by the setting switch SW2 is input in parallel by an input switch SW3;
A trigger switch SW4 for supplying a necessary number of the same shift clock SINCK to both the shift register 430 and the serial-in / parallel-out shift register 270 of the absolute encoder 200 via the connector 410. , RS-F / F
442, a frequency divider 444, a decoder 446, and a shift clock generator 440 including an AND gate 448.

In the shift clock generator 440, the counting direction set by the setting switch SW2 and the difference between the absolute origin of the scale pattern and the absolute origin desired by the user are determined by the upper part of FIG. As shown in (1), a parallel input is made to the shift register 430 by the input switch SW3. Next, the reset terminal R of the frequency divider 444 is set to the H level by the trigger switch SW4, and the frequency divider 4
44 is operated. Thus, the shift clock SINCK is output until the value determined by the decoder 446 (corresponding to the number of bits of the write information) is reached.

At this time, the write data S set by the setting switch SW2 is synchronized with the shift clock SINCK.
IN is sent to the serial-in / parallel-out shift register 270 of the absolute encoder 200 via the connector 410. At this time, for example, the leading data of the write data SIN is the count direction inversion control data DIR.

The function of the serial data / serial clock generator 420 can be easily realized by software operation by a microcomputer.

The operation of the embodiment will be described below.

First, the setting switch SW2 of the serial data / serial clock generator 420 sets the difference between the absolute origin of the scale pattern and the absolute origin desired by the user and the counting direction desired by the user. For example, the parallel-in / serial-out shift register 43
The counting direction can be set by the switch at the left end of the drawing so that the leading data of the write data SIN output from 0 becomes the counting direction inversion control data.

After the write information is set by the setting switch SW2, the input switch SW3 is turned on to input the data in parallel to the parallel-in / serial-out shift register 430.

Next, the start switch SW4 of the shift clock generator 440 is turned on to activate the frequency divider 444, and the shift clock generator 440 generates a number of shift clocks SINCK corresponding to the number of bits of the write information. To do.

At this time, the write data S set by the setting switch SW2 is synchronized with the shift clock SINCK.
IN is sent from the parallel-in / serial-out shift register 430 to the serial-in / parallel-out shift register 270 of the absolute encoder 200 via the connector 410.

On the other hand, the serial in-parallel out shift register 270 of the absolute encoder 200
Inputs the write data SIN and temporarily stores it.

Next, when the write switch SW1 of the absolute origin writing device 400 is turned on, the output of the shift register 270 changes from the high impedance state to the output state, and at the same time, the EEPROM 220 writes from the read (output) state to the write (input) state. 16), and the parallel data output from the shift register 270 is written into the EEPROM 220 as shown in the lower part of FIG.

Thus, the write operation is completed.

Since the EEPROM 220 does not lose data even when the power is turned off once, it is much more advantageous than the case where a random access memory (RAM) is combined with a battery or a large capacity capacitor.

Further, in this embodiment, since the pull-up resistor R1 is provided on the input side of the EEPROM 220, erroneous writing does not occur even if the connector 410 is removed.

At the time of measurement, the EEPROM 220
Is input to the exclusive OR gate 230. Since the output of the absolute value detector 210 is input to the other terminal of the exclusive OR gate 230 for each bit, the output of the exclusive OR gate 230 is as shown in FIG. In accordance with the value of the inversion control data DIR, when the value of DIR is 0, the up-count is performed.
Is 1, the count is down, and the counting direction is reversed.

FIG. 17 shows a case where the absolute data is 8 bits, and the binary is represented by two's complement.

The absolute value detector 210 whose counting direction has been inverted as required by the counting direction inversion control data DIR.
Are output from one input A _n-1 ... A ₀ of the adder 140.
, And the other input B _n−1.
The difference from the absolute origin desired by the user, which is input to B ₀ and stored in the EEPROM 220 is added.

The absolute data S _n-1 ... S ₀ having the counting direction desired by the user and having the absolute origin desired by the user, which is output from the adder 140, is output to the NC unit 300.
Is input to the parallel-in / serial-out shift register 250 in order to convert the signal into a serial signal SOUT suitable for output to the serial output SOUT.

The shift register 250 converts the measured data into a serial signal SOUT according to the shift clock SOCK generated by the shift clock generator 260 in response to the data request signal REQ input from the NC device 300 via the connector 310. Are sequentially output to the NC device 300.

In the above embodiment, a combination of a capacitance type detector and a photoelectric type detector is used as the absolute value detector 110 of the absolute encoder 200. Is not limited to this,
For example, one using only a capacitance type detector or one using only a photoelectric type detector may be used. Further, another type of absolute value detector may be used.

In the above embodiment, the absolute origin writing device 400 is separate from the NC device 300.
It is also possible to incorporate the absolute origin writing device 400 in the NC device 300 or in the absolute encoder 200. If built into either one,
The number of connectors can be reduced.

In the above embodiment, the NC device 30
0 and the absolute origin writing device 40
The connector 410 for the NC device 300 is shared by a single connector.
Alternatively, it may be connectable to the absolute origin writing device 400.

In this case, the absolute origin writing device 400 is inserted into the shared connector when writing the absolute origin, and the NC device 300 is inserted into the shared connector when measuring. Also in this case, the number of connectors can be reduced.

Also in this case, since writing can be performed only by changing the cable connected to the NC device 300 to the absolute origin writing device 400, there is no need to remove the encoder from the device to which the absolute encoder 200 is attached.

In the above embodiment, since the EEPROM 220 is used as the nonvolatile memory,
Updating the contents of the non-volatile memory is easy. Note that the type of the nonvolatile memory is not limited to this.

In the above embodiment, the present invention is applied to a linear encoder. However, the scope of the present invention is not limited to this. For example, the present invention can be similarly applied to a rotary encoder.

[0073]

As described above, according to the present invention, the counting direction of the output data and the absolute origin position can be easily changed even after the encoder is incorporated in the device. Therefore, it is possible to flexibly cope with different types of NC devices. In addition, since batteries and capacitors are not used for backup, backup can be performed for almost infinite time, and at the same time, there are excellent effects such as safety in a high-temperature and high-humidity environment.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an absolute value detector used in the embodiment;

FIG. 3 is a perspective view showing a scale of the absolute value detector and a configuration of the detector.

FIG. 4 is a plan view showing a scale pattern of the absolute value detector with a part thereof enlarged.

FIG. 5 is a perspective view for explaining an operation of a capacitance type detector used in the absolute value detector.

FIG. 6 is a diagram showing an example of an output waveform of the capacitance type detector.

FIG. 7 is a diagram showing a data structure for explaining the operation of a register and a comparison circuit used in the absolute value detector.

FIG. 8 is a longitudinal sectional view showing a configuration example of a photoelectric detector used in the absolute value detector.

FIG. 9 is a time chart showing an example of a relation between a binary code signal of an output of an optoelectronic detection circuit and an output of an interpolation circuit used in the absolute value detector.

FIG. 10 is a circuit diagram showing a configuration example of a carry generator used in the absolute value detector.

FIG. 11 is a time chart showing the operation of the carry generator.

FIG. 12 is a circuit diagram showing a configuration example of a comparison circuit used in the absolute value detector.

FIG. 13 is a diagram showing a truth table of a decoder used in the comparison circuit.

FIG. 14 is a time chart showing the operation of the comparison circuit.

FIG. 15 is a block diagram showing a configuration example of a serial data / serial clock generator of the absolute origin writing device used in the embodiment.

FIG. 16 is a time chart illustrating operation waveforms of respective units according to the embodiment.

FIG. 17 is a table illustrating how the counting direction is reversed in the embodiment.

[Explanation of symbols]

10 scale, 22 pickup (slider), 52 slit plate (slider), 200 absolute encoder, 210 absolute value detector, 220 EEPROM, 230 exclusive OR gate, 240 adder, 250, 430 Parallel in-serial out shift register, 260, 440 shift clock generator, 270 serial in-parallel out shift register, 300 NC device, 310, 410 connector, 400 absolute absolute writing device, 420 serial data Serial clock generator.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-71321 (JP, A) JP-A-2-51021 (JP, A) Fully open 1988-167217 (JP, U) Really open 1988 163411 (JP, U)

Claims (3)

(57) [Claims] An absolute encoder for outputting a detected position as absolute data, an absolute value detector for detecting an absolute position of a slider with a predetermined position determined by a scale pattern as an absolute origin, an absolute value detector for detecting the absolute position of the scale pattern and a user. Enter the absolute origin difference desired by the user and the counting direction desired by the user.
An input means, a nonvolatile memory for storing the difference between the absolute origins, and the counting direction; and an increase / decrease in the absolute value detector output when the counting direction of the absolute value detector is different from the counting direction desired by the user. Means for reversing the direction, by the direction reversing means, adding the output of the absolute value detector configured to increase or decrease in the counting direction desired by the user and the value stored in the nonvolatile memory, An absolute encoder comprising: an adder for obtaining absolute data having a position desired by a user as an absolute origin; and output means for outputting the absolute data . 2. The absolute encoder according to claim 1,
In Da, data output from said output means serially
Absolute encoder characterized by data . 3. The absolute absorber according to claim 1 or 2.
In the encoder , data input from the input means is
Absolute encoder characterized by real data .