JP3125560B2 - Halftone display circuit of display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display apparatus of a digital drive system such as a PDP or an LCD, wherein a halftone display for reproducing a smooth image by supplementing a luminance gradation number smaller than an input signal by pseudo halftone display. It relates to a display circuit.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
DP (plasma display panel) has attracted attention. The driving method of this PDP is completely different from the conventional CRT driving method, and is a direct driving method using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are classified into two types: AC type and DC type, which have different basic characteristics. In DC type PDPs, there have been reports on methods for improving brightness and lifetime, which have already been issues, and progress is being made toward practical use. is there.

[0003] On the other hand, in the AC type PDP, sufficient characteristics have been obtained with respect to luminance and life, but there have been only reports on gradation display up to 64 gradation display at the prototype level. Recently, the address / display separated driving method (AD
(S subfield method) has been proposed in the future with 256 gradations. The address / display separation type driving method is a method in which n-bit input data is turned on at a constant luminance for a time period of the weight of each bit in one frame. FIG. 10 shows a panel structure of a PDP (plasma display panel) 10 used in this method, and FIGS. 11A and 11B show a driving sequence and driving waveforms.

In FIG. 10, a pair of an X sustain electrode 12 and a Y sustain electrode 13 are formed of a transparent electrode and an auxiliary electrode on the lower surface of a front surface glass substrate 11 on the display surface side. The auxiliary electrode prevents voltage drop due to the resistance of the transparent electrode,
The bus electrode 23 is formed on a part of the transparent electrode. A dielectric layer 14 is provided on the X-sustain electrode 12 and the Y-sustain electrode 13, and strip-like ribs 18 are formed thereon to separate coupling between cells. Further, a protective layer 15 made of an MgO film is deposited. An address electrode 17 is formed on the opposite back glass substrate 16. A stripe-shaped rib 18 on the stripe is provided between the address electrodes 17, and the address electrodes 17 are further covered.
A (red) phosphor 19, a G (green) phosphor 20, and a B (blue) phosphor 21 are separately formed. In the discharge space 22, Ne +
Xe mixed gas is sealed.

In FIG. 11A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, and 12;
It is composed of eight subfields of eight, and displays 256 gradations by combining the luminance of eight screens. In FIG. 11B, each subfield includes an address period in which data for one refreshed screen is written and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In a display device for reproducing a digital video input signal as described above, the number of luminance gradations smaller than that of the input signal is supplemented by pseudo-halftone display, and a systematic dithering method is used as a halftone display method for reproducing a smooth image. There is a law. In this method, the number of lit dots in a small area block (matrix) of M × N pixels is changed on the display screen, and a pseudo halftone is expressed by the small area block.

This will be described in more detail with reference to FIGS. 7, 8 and 9. In FIG. 8, an n-bit input signal input to a video signal input terminal 30 has a luminance level detected by a level detection circuit 31, and based on the luminance level, 2 n gradations generated from a pattern generation circuit 32. The switching circuit 33 selects a corresponding pattern from the patterns and outputs the selected pattern. FIG. 8 shows a case of displaying a binary image. Since the pattern is composed of 1 bit of 0 or 1, the input n bits are 1 bit (corresponding to 1 luminance gradation) pseudo-halftone output. Is output.

More specifically, in the case of a 4 (M) × 4 (N) matrix, when a signal of 3/16 luminance as shown in FIG. The 3/16 luminance pattern as shown in FIG. 9 is selected from the 2 n gradation patterns generated by the pattern generation circuit 32 and output by the switching circuit 33.

[0009]

In the conventional method described above, when a signal having a luminance of 1 / m is input to the video signal input terminal 30, as shown in FIG. Since the luminance is m, there is a problem that the bright point of the dot is conspicuous at a low luminance level of 1/2 or less, particularly 1/16, 2/16, 3/16,.
Also, if you try to increase the number of dots in the matrix,
The number of brightness gradations had to be reduced.

According to the present invention, when the number of bits of the input signal is less than the number of bits of the display device, the pseudo halftone display is made compatible with a display device having a luminance gradation of 2 bits or more to compensate for the insufficient gradation. It is an object of the present invention to obtain such a circuit. The present invention seeks to achieve this object with a circuit as small as possible.

[0011]

The present invention relates to a display.
N is the number of bits for the halftone display of the device, and
Where x is n <x, and the luminance that is quantized and input from a pattern stored by changing the number of lit dots in a small area block in which the display screen is divided into M × N pixels. By selectively outputting a pattern corresponding to the signal level, in a display device that reproduces a smooth image by supplementing the number of luminance gradations smaller than that of the input signal by pseudo halftone display , the number of bits x of the input signal is expressed as
The number of upper bits n equal to the number of bits of the display device;
Upper / lower bit separation circuit for separating the remaining lower bit number m
50, the pseudo-halftone processing circuit 52 to the output by converting the pseudo-halftone processing per the number of low-order bits m to 1-bit signal, the number of upper bits n, of the pseudo halftone processing circuit 52 A halftone display circuit for a display device, comprising: an adder circuit 51 for sequentially adding 1-bit outputs subjected to pseudo halftone processing.

[0012]

When there is an 8-bit input signal at the input terminal 30,
The upper 4 bits to match the 4 bits of the display device
The bit is sent to the addition circuit 51. The lower 4 bits of the input signal are sent to the pseudo halftone processing circuit 52, the luminance level is detected, a pattern corresponding to the luminance level is selected from the pattern generation circuit 32, and the pattern is output as a 1-bit pseudo halftone. The signal is sent to the addition circuit 51.

In the adder circuit 51, the 1-bit pseudo halftone output is added to the upper 4 bits, and a shortage between a certain grayscale and the next higher grayscale is generated as a pseudo halftone.
In addition to the display device, the pseudo halftone process is compatible with a display device having a gray scale of 2 bits or more. This compensates for the lack of gradation between the gradations of the display device, resulting in a smooth screen. further,
Since only the addition circuit 51 is added, the circuit configuration is simple.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle of the present invention is that when the number n of bits of the display device is smaller than the number x of bits of the input signal (x> n), the gray scale of the insufficient bits is determined by using the pseudo halftone processing circuit of the display device. To a lower bit, for example, a 1-bit signal, and add this to a higher-order bit signal to the display device. It is created as a pseudo halftone.

Further, by applying the pseudo halftone output to the display device, the grayscale of the display device to be subjected to the pseudo halftone process is shifted in accordance with the level of the input signal, and the level of 2 bits or more is shifted. This means that the pseudo halftone process is compatible with a display device having a tone. This makes it possible to compensate for the insufficient gradation between the gradations of the display device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIG. 1 showing the first embodiment, reference numeral 30 denotes a video signal input terminal for an x-bit input signal. The video signal input terminal 30 has a bit number x of the input signal larger than a bit number n of the display device (x > N), it is coupled to an upper / lower bit separation circuit 50 for separating upper n bits and other lower bits m (m ≦ x−n). The upper n bit lines of the upper / lower bit separation circuit 50 are
1 is connected to one input side of
The lower m-bit line of 0 is coupled to the other input side of the adder circuit 51 via the pseudo halftone processing circuit 52, and the adder circuit 51 is coupled to the output terminal.

In the above configuration, if there is an input signal of x bits, for example, 8 bits at the video signal input terminal 30, the upper and lower bit separation circuit 50 matches the number n of bits of the display device, for example, 4 bits. Then, the upper 4 bits are sent to the adding circuit 51. In the upper / lower bit separation circuit 50, the lower m bits of the input signal, for example, x−
n = 4 bits are sent to the pseudo halftone processing circuit 52. The luminance level of the lower 4 bits is detected by the level detection circuit 31, and a luminance pattern corresponding to the detected luminance level is selected by the switching circuit 33 from the pattern of the pattern generation circuit 32, and is set as a low bit, for example, 1 bit pseudo halftone. The output is sent to the addition circuit 51.

The adder circuit 51 adds the 1-bit pseudo halftone output to the upper 4 bits of the input signal, thereby providing an insufficient grayscale between a certain grayscale of the display device and the grayscale immediately above it. Is generated as a pseudo-halftone and the pseudo-halftone output is applied to the display device, so that the grayscale of the display device subjected to the pseudo-halftone process moves in accordance with the level of the input signal. This means that the pseudo halftone processing is compatible with a display device having a gradation of more than one bit. This compensates for the lack of gradation between the gradations of the display device, resulting in a smooth screen.
Further, since only the addition circuit 51 is added, the circuit configuration is simple.

In the first embodiment shown in FIG. 1, the pattern generation circuit 32 of the pseudo halftone processing circuit 52 generates one luminance pattern for each luminance gradation. However, the present invention is not limited to this. Absent. In a small area block (matrix) of M × N pixels arranged at the same position on the screen for each frame, two patterns having substantially the same number of dots and different arrangements (different phases) are prepared. The two patterns may be alternately switched and displayed for each frame.

That is, in FIG. 2, a first frame pattern generation circuit 35 and a second frame pattern generation circuit 36 are provided in parallel instead of the pattern generation circuit 32 in the circuit shown in FIG. It is connected to a switching circuit 33 via a frame switching circuit 37. The frame switching circuit 37 is connected to a vertical synchronization signal input terminal 38 as a switching timing signal.

The first frame pattern 39 of the first frame pattern generation circuit 35 and the second frame pattern 40 of the second frame pattern generation circuit 36 have substantially the same number of dots in the M × N matrix, and Different (different phases) patterns. That is, the number of dots is desirably the same in the first frame pattern 39 and the second frame pattern 40. However, depending on the pattern, the number of dots need not be the same but may be substantially equal. The arrangement of the dots (black points) is such that when the first frame pattern 39 and the second frame pattern 40 are overlapped and the pattern is continuous in the vertical and horizontal directions, a point with dots (black point) and a point without dots (black dot) (White dots) are arranged almost uniformly.

For example, as shown in FIG. 3A, assuming that the pattern of the first frame pattern generation circuit 35 when the lower m bits of the input signal are 1/2 luminance is a checkerboard pattern, The pattern of the generating circuit 36 is
Equal to the number of dots in the first frame pattern 39,
In addition, a checkered pattern like the second frame pattern 40 in FIG. 3A in which the arrangement of white and black is inverted.

The lower m bits of the input signal are 1/8
Assuming that the pattern of the first frame pattern generation circuit 35 at the time of luminance is the first frame pattern 39 of FIG. 3B, the pattern of the second frame pattern generation circuit 36 is the same as the number of dots in the first frame pattern 39. The arrangement of the equal and white and black patterns is such that the first frame pattern 39 and the second frame pattern 40 overlap each other and are substantially uniform when the patterns are continuous in the vertical and horizontal directions.
The frame pattern 40 is used.

In the above configuration, the first frame pattern 39 from the first frame pattern generation circuit 35 is output.
And the second frame pattern 40 from the second frame pattern generating circuit 36 are alternately switched and output for each frame via the frame switching circuit 37 by the vertical synchronization signal from the vertical synchronization signal input terminal 38. Here, when a signal of lower m bits is input from the upper / lower bit separation circuit 50, the level of the luminance is detected by the level detection circuit 31, and the first frame pattern 39 and the second frame pattern corresponding to the luminance level signal are detected. 40 and the switching circuit 33
And alternately outputs the pseudo-halftone output terminal 34 for each frame.

As described above, by alternately outputting the first frame pattern 39 and the second frame pattern 40 for each frame, the first frame pattern 39 and the second frame pattern 40 are displayed in an overlapping manner. The apparent brightness of the dots themselves is halved, and the number of dots is doubled. Therefore, the pseudo halftone display 41 can display a higher definition and improve the resolution.

FIG. 4 shows an embodiment of a color display in the embodiment shown in FIG. In FIG. 4, 50
R, 50G, and 50B are signal input terminals of lower m bits of R, G, and B, respectively, 31R, 31G, and 31B are signal level detection circuits of R, G, and B, respectively, and 33R and 33.
G and 33B are switching circuits for R, G and B, respectively. A first frame pattern generating circuit 35 and a second frame pattern generating circuit 36 are connected to the input side of these circuits via a frame switching circuit 37. In addition, adders 51R, 51G and 51B are coupled to the output side.

Here, the luminance levels of the R, G, and B signals are detected by the R, G, and B signal level detection circuits 31R, 31G, and 31B, respectively.
The frame pattern 39 and the second frame pattern 40 are selected by the R, G, B switching circuits 33R, 33G, 33B, and the R, G, B adding circuits 51R, 51
G and 51B are output alternately for each frame.

As described above, by outputting the first and second frame patterns 39 and 40 alternately for each frame of the R, G and B signals, the first and second frame patterns 39 and 40 are output. The display is superimposed, and the number of dots can be reduced by two without changing the apparent brightness of the dots themselves.
Increase by a factor of two.

Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, in a small area block (matrix) of M × N pixels arranged at the same position on the screen for each frame, three patterns having substantially the same number of dots and different arrangements (different phases) are provided. Are prepared for each predetermined luminance level, and these three patterns are displayed in an overlapping manner. This will be described in more detail with reference to FIG. 5. In each frame, 2 n power gradation patterns are generated.
That is, for each predetermined luminance level, and R,
Pattern forming circuits 40R, 40G, and 40B that form three patterns for each of the G and B signals are provided in parallel, respectively, and these circuits are coupled to a superimposing circuit 44.

The R pattern forming circuit 40 R
Bit R signal input terminal 50R to R level detection circuit 3
It is coupled to the switching circuit 33R via 1R. Also,
First, second, and third frame R pattern generation circuits 41R,
42R and 43R are provided in parallel, and these circuits are coupled to a switching circuit 33R via a frame switching circuit 37R. A vertical synchronization signal input terminal 38 is connected to the frame switching circuit 37R.

Similarly, the same applies to the G pattern forming circuit 40G and the B pattern forming circuit 40B.

The R pattern forming circuits 40R, 40G,
As shown in FIG. 6, each frame pattern of 40B has the same number of dots, and 41r, 42g, 43
b, 41g, 42b, 43r, 41b, 4
The arrangement of 2r and 43g is made equal to each other, and the mutual patterns are distributed as uniformly as possible without overlapping.

In the above configuration, the R, G, B of the lower 4 bits (in the case of a 4 × 4 matrix) of the input signal
When a signal of 3/16 luminance is input to each signal of R, G,
The luminance levels are detected by the B level detection circuits 31R, 31G and 31B, respectively, and the 3/16 luminance pattern as shown in FIG. 6 is selected from the 2 n number of gradation patterns by the switching circuits 33R, 33G and 33B. Select and output.

The vertical synchronizing signal from the input terminal 38
The R, G, and B patterns 41r, 41g, and 41b in the first frame (3n-2) are sent to the overlapping circuit 44 and overlapped, and a first frame pattern 45 is obtained first.

Similarly, a second frame pattern 46 is obtained in the second frame (3n-1), and a third frame pattern 47 is obtained in the third frame (3n).

The first, second and third frame patterns 45, 46 and 47 are further superimposed to obtain a superimposed pattern 48 as a pseudo halftone output. As a result, in the superimposition pattern 48, the apparent luminance of each dot is reduced to 1/3, and the number of dots is reduced by that amount.
It has increased twice. Therefore, in the pseudo halftone display, higher definition display can be performed, and the resolution is improved.

[0037]

【The invention's effect】

(1) When the number n of bits of the display device is less than the number x of bits of the input signal (x> n), the gray level of the missing bit is reduced by using the pseudo halftone processing circuit of the display device to a low bit, for example, 1 bit. By adding this to the upper bit signal to the display device,
Insufficient gradations are created as pseudo halftones between a certain gradation of the display device and one gradation above it, and the lacking gradations between the respective gradations of the display device are supplemented to provide a smooth screen.

(2) By applying the pseudo-halftone output to the display device, the grayscale of the display device to be subjected to the pseudo-halftone process is shifted in accordance with the level of the input signal. This means that the pseudo halftone processing is compatible with a display device having a gradation. This makes it possible to compensate for the insufficient gradation between the gradations of the display device.

(3) Since only the addition circuit 51 is added, the circuit configuration is simple. (4) By displaying the first frame pattern 39 and the second frame pattern 40 in an overlapping manner, the number of dots can be increased without changing the apparent brightness of the dots themselves.
The pseudo-halftone display 41 can perform higher definition display and improve resolution. (5) The bright point of the dot at a low level becomes inconspicuous.

(6) By setting the number of dots of the first frame pattern 39 and the number of dots of the second frame pattern 40 to be substantially the same, flicker which is a visual characteristic in the time axis direction is not perceived. (7) The first, second, and third frames are sequentially superimposed and displayed,
The apparent brightness of the dots themselves is reduced to 1/3, and the number of dots is increased accordingly. Therefore, the pseudo halftone display pattern 48 can display a higher definition and the resolution is improved.

(8) By setting the number of dots to be substantially the same in the first, second and third frames, flicker which is a visual characteristic in the time axis direction is not perceived. (9) By arranging the same number of dots of R, G, and B in a matrix, and arranging the R, G, and B at the same location in the frame direction so as not to overlap, gray representation can be achieved without impairing the color balance. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a halftone display circuit of a display device according to the present invention.

FIG. 2 is a block diagram of another embodiment of the pattern generation circuit 32 in the circuit of FIG.

FIG. 3 is an explanatory diagram of a pseudo halftone pattern superimposing operation by the circuit of FIG. 1;

FIG. 4 is a block diagram of still another embodiment of the pattern generation circuit 32 in the circuit of FIG.

FIG. 5 is a block diagram showing another embodiment of the halftone display circuit of the display device according to the present invention.

6 is an explanatory diagram of a pseudo halftone pattern superimposing operation by the circuit of FIG. 5;

FIG. 7 is an explanatory diagram of a luminance level of pseudo halftone display.

FIG. 8 is a block diagram showing a halftone display circuit of a conventional display device.

FIG. 9 is an explanatory diagram of a pseudo halftone pattern by a conventional circuit.

FIG. 10 is a perspective view of a PDP used for a 256 gradation method.

FIG. 11 is a drive sequence and a drive waveform diagram in a 256 gradation method.

[Explanation of symbols]

10 PDP (plasma display panel), 1
DESCRIPTION OF SYMBOLS 1 ... Surface glass substrate, 12 ... X sustain electrode, 13 ...
Y sustain electrode, 14: dielectric layer, 15: protective layer, 1
6 ... back glass substrate, 17 ... address electrode, 18 ... stripe-shaped rib, 19 ... R (red) phosphor, 20 ... G (green)
Phosphor, 21 ... B (blue) phosphor, 22 ... discharge space, 23
... bus electrodes, 30, 30R, 30G, 30B ... signal input terminals, 31, 31R, 31G, 31B ... level detection circuits, 32 ... pattern generation circuits, 33, 33R, 33G,
33B: switching circuit, 34: pseudo halftone output terminal, 34
R, 34G, 34B ... pattern output terminal, 37R, 37
G, 37B: frame switching circuit, 38: vertical synchronization signal input terminal, 40R, 40G, 40B: pattern forming circuit, 41R, 41G, 41B: first frame pattern generation circuit, 42R, 42G, 42B: second frame pattern generation Circuits, 43R, 43G, 43B ... third frame pattern generation circuit, 44 ... superimposition circuit, 45 ... first frame pattern, 46 ... second frame pattern, 47 ...
3rd frame pattern, 48 ... overlapping pattern, 5
0: Upper / lower bit separation circuit, 51, 51R, 51G, 5
1B ... addition circuit, 52 ... pseudo halftone processing circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Inside of Fujitsu General Limited (72) Inventor Hayato Denda 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Fujitsu General Limited (56) References JP-A-2-85974 (JP, A) JP-A-6-161400 (JP, A) JP-A-7-121149 (JP, A) (58) Fields investigated (Int. ^7, DB name) G06T 5/00 G09G 3/20 G09G 3/28 G09G 3/288

Claims (5)

(57) [Claims] 1. A bit for a halftone display of a display device.
When the number is n and the number of bits of the input signal is x, n <x
Then, a pattern corresponding to the input luminance signal level which has been quantized is selectively output from patterns stored by changing the number of lit dots in a small area block in which the display screen is divided in units of M × N pixels. Thus, in a display device which reproduces a smooth image by supplementing the number of luminance gradations smaller than that of the input signal by pseudo halftone display, the number of bits x of the input signal is reduced by the bit number of the display device.
Number of upper bits n and m of remaining lower bits
An upper / lower bit separation circuit 50 for separation,
Pseudo halftone processing for several meters and conversion to 1-bit signal
And halftoning circuit 52 to the output by the upper-bi
A halftone display circuit for a display device, comprising: an adder circuit 51 for sequentially adding a 1-bit output obtained by performing the pseudo halftone processing of the pseudo halftone processing circuit 52 to the number n of bits . 2. A pattern corresponding to an input luminance signal level that has been quantized and selected from patterns stored by changing the number of lit dots in a small area block in which a display screen is divided in units of M × N pixels. By outputting, by a pseudo halftone display, the number of luminance gradations smaller than that of the original signal is complemented by a pseudo halftone display to reproduce a smooth image. A pseudo-halftone processing circuit 52 for outputting, an adding circuit for adding the same number of higher-order bits of the input signal as the number of bits of the display device and the pseudo-halftone-processed low bit output of the pseudo-halftone processing circuit 52 51, the pseudo halftone processing circuit 52 includes a first frame pattern generation circuit 35, and a pattern of the first frame pattern generation circuit 35. A second frame pattern generation circuit 36 for generating patterns having substantially the same number of dots and different arrangements, and alternately switching the patterns of the first frame pattern generation circuit 35 and the second frame pattern generation circuit 36 for every frame Frame switching circuit 37
And a halftone display circuit for a display device. 3. A pattern corresponding to an input luminance signal level which has been quantized and selected from patterns stored by changing the number of lit dots in a small area block in which a display screen is divided in units of M × N pixels. By outputting, by a pseudo halftone display, the number of luminance gradations smaller than that of the original signal is complemented by a pseudo halftone display to reproduce a smooth image. A pseudo-halftone processing circuit 52 for outputting, an adding circuit for adding the same number of higher-order bits of the input signal as the number of bits of the display device and the pseudo-halftone-processed low bit output of the pseudo-halftone processing circuit 52 51, the pseudo halftone processing circuit 52 includes a first frame pattern generation circuit 35, and a pattern of the first frame pattern generation circuit 35. A second frame pattern generation circuit 36 for generating patterns having substantially the same number of dots and different arrangements, and alternately switching the patterns of the first frame pattern generation circuit 35 and the second frame pattern generation circuit 36 for every frame Frame switching circuit 37
The second frame pattern 40 of the second frame pattern generation circuit 36 overlaps the first frame pattern 39 of the first frame pattern generation circuit 35 with the second frame pattern 40 of the second frame pattern generation circuit 36, A halftone display circuit for a display device, wherein when a pattern is continuous in a vertical direction and a horizontal direction, an arrangement is such that dots with dots and dots without dots are substantially uniform. 4. A pattern corresponding to a quantized and input luminance signal level is selected from patterns stored by changing the number of lit dots in a small area block in which a display screen is divided in units of M × N pixels. By outputting, by a pseudo halftone display, the number of luminance gradations smaller than that of the original signal is complemented by a pseudo halftone display to reproduce a smooth image. A pseudo-halftone processing circuit 52 for outputting, an adding circuit for adding the same number of higher-order bits of the input signal as the number of bits of the display device and the pseudo-halftone-processed low bit output of the pseudo-halftone processing circuit 52 51, and the pseudo halftone processing circuit 52 performs the first, second, and third R, G, and B for each predetermined input luminance signal level.
R, G, and B pattern generation circuits that generate three types of patterns in which the number of dots in each frame is substantially equal and the arrangement of dots is at least different for each frame, and each of these R, G, and B A switching circuit for selecting a pattern corresponding to an input luminance signal level from a pattern generating circuit, and a superimposing circuit for superimposing patterns of first, second, and third frames in R, G, and B. Halftone display circuit of a display device. 5. A pattern corresponding to a quantized and input luminance signal level is selected from patterns stored by changing the number of lit dots in a small area block in which a display screen is divided in units of M × N pixels. By outputting, by a pseudo halftone display, the number of luminance gradations smaller than that of the original signal is complemented by a pseudo halftone display to reproduce a smooth image. A pseudo-halftone processing circuit 52 for outputting, an adding circuit for adding the same number of higher-order bits of the input signal as the number of bits of the display device and the pseudo-halftone-processed low bit output of the pseudo-halftone processing circuit 52 51, and the pseudo halftone processing circuit 52 performs the first, second, and third R, G, and B for each predetermined input luminance signal level.
R, G, and B pattern generation circuits for generating a pattern in which the number of dots in each frame is substantially equal, and the three types of arrangement of dots for each luminance level generate different patterns for each frame and for each of R, G, and B sequentially And a switching circuit for selecting a pattern corresponding to the input luminance signal level from each of the R, G, and B pattern generation circuits, and the first, second, and third frame patterns in R, G, and B. And a superimposing circuit for combining, wherein the R pattern generating circuit comprises first, second, and third frame R pattern generating circuits for generating 2 n gradation patterns for each frame, respectively. G
The pattern generation circuit includes first, second, and third frame G pattern generation circuits that generate 2 n gradation patterns for each frame, and the B pattern generation circuit includes, for each frame, A first, a second and a third frame B pattern generating circuit for generating 2 n gradation patterns, wherein the first frame R, the second frame G and the third frame B have the same arrangement, The second frame R, the third frame G, and the first frame B have the same arrangement, respectively, and the third frame R, the first frame G, the second frame
A halftone display circuit for a display device, wherein each of the frames B generates a pattern having the same arrangement.