JP3125325B2 - Transmission control method in storage-type star communication network - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of terminal devices and a central station for transmitting and receiving communication data between these terminal devices, and a storage type star for performing communication between the terminal devices through the central station. The present invention relates to a transmission control method in a communication network.

[0002]

2. Description of the Related Art First, a general star communication network will be described with reference to FIG. The star communication network includes a plurality of terminal devices 81-1 to 81-n and a central station 82, and each of the terminal devices 81-1 to 81-n has a transmission line 83-1.
To 83-n and the receiving lines 84-1 to 84-n, respectively.

Here, for example, when a packet indicating data is transmitted from the terminal device 81-1, the packet is transmitted to the central station 82 via the transmission line 83-1. Central Bureau 8
2 receives the packet and sends the packet to each receiving line 8
All terminal devices 81-1 through 4-1 through 84-n
81-n. Upon receiving the packet, each of the terminal devices 81-1 to 81-n determines whether or not the packet is addressed to its own terminal device, and if the packet is addressed to itself, removes the packet. Put in.

On the other hand, each of the terminal devices 81-1 to 81-n constantly monitors signals from each of the receiving lines 84-1 to 84-n, and any signal is transmitted to its own receiving line. When transmitting, the packet is not transmitted to the central station. For this reason, if a packet has been transmitted through its own receiving line, the terminal device waits until the transmission is completed, and transmits a packet addressed to another terminal device to the centralized station after the transmission is completed.

In some cases, two or more terminal devices simultaneously transmit respective packets to a centralized station. In this case, packet collision occurs. In such a case, the centralized station detects a packet collision and notifies this collision to all terminal devices. Two or more terminal devices transmitting packets among all the terminal devices respond to the notification from the central station and immediately stop transmitting the packets. This avoids packet collisions,
Subsequently, a process for retransmitting the packet is performed according to a predetermined back-off algorithm.

However, in such a star-type communication network, it is impossible to simultaneously transmit each packet from two or more terminal devices to a centralized station, so that good communication efficiency cannot be obtained. In view of this, the applicant of the present application has previously proposed a "storage type star communication network (Japanese Patent Application Laid-Open No. 62-194760)" to improve communication efficiency. In this storage type star communication network, each storage device corresponding to each terminal device is provided on the central station, and each packet transmitted from each terminal device is temporarily stored in each storage device. Are sequentially transmitted from the central station to all the terminal devices.

In such a storage type star communication network, 2
Although it is possible to simultaneously transmit each packet from one or more terminal devices to the centralized station, the packet is stored in the storage device until the storage device corresponding to the terminal device is full. Nevertheless, when a new packet is further transmitted from the terminal device to the central station, the new packet is discarded or stored in the storage unit because the capacity of the storage unit is full. The stored packet is discarded, and a new packet is stored. In either case, there is a disadvantage that the packet is discarded.

[0008]

As described above, in the conventional star communication network, it is not possible to simultaneously transmit each packet from two or more terminal devices to the centralized station, and thus the communication efficiency is poor. There was a point. In order to solve this problem, in the storage-type star communication network proposed by the applicant of the present invention, although the communication efficiency has been improved, the capacity of the storage means provided on the central station is reduced. Even if packets are stored in the storage unit until the storage unit is full, if a new packet is transmitted from the terminal device corresponding to the storage unit to the centralized station, the packet is discarded. Was occurring.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a transmission control method in a storage type star communication network capable of preventing a packet from being discarded at a central station.

[0010]

According to the present invention, storage means, dummy data generation means, and transmission means corresponding to a plurality of terminal devices are provided on the central station, and each of the storage means is provided from each of the terminal devices. Each of the communication data transmitted to and received from the central station is stored, and a storage state signal indicating that the communication data has been stored to a predetermined amount is output, and the dummy data generating means outputs the dummy data. The transmitting means transmits the communication data in the storing means from the centralized station to all the terminal devices, and when the storage state signal is output from any of the storing means, For the terminal device corresponding to the storage unit that has output the storage state signal, communication data and dummy data from the dummy data generation unit are included. It is to be transmitted either at all times.

[0011]

According to the present invention, when a storage state signal indicating that communication data has been stored up to a predetermined amount is output from the storage means, communication with the terminal device corresponding to the storage means is performed. One of the data and the dummy data is always transmitted. Therefore, this terminal device always receives the communication data or the dummy data from the centralized station because the communication data is stored up to the predetermined amount in the storage means corresponding to the terminal device. here,
Since the terminal device cannot perform transmission to the central station during a period of receiving data from the central station, it transmits new communication data to the central station when receiving communication data or dummy data. Never do. For this reason,
In spite of the fact that communication data is stored in the storage means, it does not occur that new communication data must be stored.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a storage type star communication network to which an embodiment of a transmission control system according to the present invention is applied. In FIG. 1, a plurality of terminal devices 1-1 to 1-n are respectively composed of transmission lines 2-1 to 2-n and reception lines 3-1 to 3-n.
Are connected to the centralized station 4 through the transmission lines 2-1 to 2-n, respectively.
And receives packets from the centralized station 4 through the receiving lines 3-1 to 3-n.

The central station 4 includes reception memories 41-1 to 41-n corresponding to the terminal devices 1-1 to 1-n, a control circuit 42, a dummy generation unit 43, and a transmission unit 44. It is configured.

Each of the receiving memories 41-1 to 41-n receives each packet transmitted from each of the terminal devices 1-1 to 1-n through each of the receiving lines 3-1 to 3-n. Packets are stored for each of the terminal devices 1-1 to 1-n, and each has a storage capacity enough to store one packet. These receiving memories 41-1 to 41-
n is configured using a FIFO type semiconductor memory, for example, and outputs each of the empty signals L1 to Ln.
This empty signal indicates the value “0” when one packet is stored or is being stored in the receiving memory that is outputting the empty signal. Also,
This empty signal indicates the value "1" if the receiving memory outputting the empty signal is empty.

Further, each of the receiving memories 41-1 to 41-n
Are respectively supplied with read signals R1 to Rn from the control circuit 42, and these read signals R1 to Rn have the value "1".
Alternatively, it indicates the value “0”.

The control circuit 42 includes the receiving memories 41-1 to 4-4.
1-n, and if there is an empty signal indicating the value "0", the read signal applied to the receiving memory is changed from the value "0" to the value "1". Switch to Therefore, each reception memory 41-
Numerals 1 to 41-n respectively store packets from the terminal devices 1-1 to 1-n, and each empty signal L1 having a value "0".
To Ln, the control circuit 4 responds accordingly.
2, the respective read signals R1 to Rn having the value "1" are input. Then, each of the receiving memories 41-1 to 41-
When n receives each of the read signals R1 to Rn having a value of “1”, it outputs each stored packet to the transmission unit 44. Such a processing procedure will be described with reference to the flowchart of FIG.

First, the control circuit 42 samples the first empty signal L1 (step 101) and determines whether or not the value "1" is indicated by the empty signal L1 (step 102). Here, the empty signal L1
Indicates a value "0" (step 102,
NO), the control circuit 42 switches the read signal R1 from the value "0" to the value "1", thereby causing the transmission unit 44 to output the packet in the reception memory 41-1 (step 103).
This packet is read from the reception memory 41-1 at the same speed as the data transmission speed on each of the transmission lines 2-1 to 2-n,
The data is transmitted to all the terminal devices 1-1 to 1-n through the transmission unit 44.

Subsequently, the control circuit 42 samples the second empty signal L2 (step 101), and determines whether or not the value "1" is indicated by the empty signal L2 (step 102). Here, if the value "1" is indicated by the empty signal L2 (step 10).
2, YES), since the receiving memory 41-2 outputting the empty signal L2 is empty, the process returns to the step 101 without performing the process of the step 103. Thereafter, in the same manner, step 1 is performed for each empty signal from the third.
The process from 01 is repeated, and when the value "0" is indicated by the empty signal, the read signal to the receiving memory outputting the empty signal is switched from the value "0" to the value "1", As a result, the packets in the reception memory are transmitted to all the terminal devices 1-1 to 1-1 through the transmission unit 44.
-N.

In FIG. 1, a dummy generating section 43 is for generating dummy data D in place of a packet, and constantly outputs this dummy data D to a transmitting section 44. This dummy data D is formed by repeating a predetermined code pattern, and is transmitted from the transmission unit 44 to the terminal device through a reception line as described later.

The transmitting unit 44 receives the packet from the receiving memory and sends the packet to all the terminal devices 1-1 to 1-n as described above, or sends the packet to the dummy generating unit 43. This is for transmitting the dummy data D in place of the packet, and the configuration is shown in FIG.

In FIG. 3, the OR circuit 31 receives the read signals R1 to Rn from the control circuit 42 and outputs a signal R indicating the logical product of the values of the read signals R1 to Rn.

A plurality of AND circuits 32-1 to 32-n are provided corresponding to the respective reception memories 41-1 to 41-n, and thus also correspond to the respective terminal devices 1-1 to 1-n. Will be. These AND circuits 32-1 to 32-n use the signal R from the OR circuit 31 as an inverting input, and the empty signals L1 to Ln from the receiving memories 41-1 to 41-n as their inverting inputs. Further, a dummy packet D 1 from the dummy generation unit 43 is input, and signals D1 to Dn indicating the logical sum of three inputs are output to each AND circuit.

The plurality of OR circuits 33-1 to 33-n are provided corresponding to the respective AND circuits 32-1 to 32-n, so that each of the receiving memories 41-1 to 41-n and each of the terminal devices 1 are provided. It also corresponds to -1 to 1-n. These OR circuits 33-1 to 33-n are connected to the respective reception memories 41.
-1 to 41-n, and the signals D1 to Dn from the AND circuits 32-1 to 32-n, respectively.
Each signal B1 to Bn indicating the logical product of two inputs is output. These signals B1 to Bn are respectively sent to the receiving lines 3-1 to 3-n connected to the terminal devices 1-1 to 1-n.

In such a configuration, for example, when respective packets are simultaneously transmitted from the two terminal devices 1-1 and 1-2 to the centralized station 4, the centralized station 4 uses the timing chart shown in FIG. The following operation is performed.

First, when the first packet a and the second packet b are transmitted from the terminal devices 1-1 and 1-2 to the transmission lines 2-1 and 2-2, respectively, The reception memories 41-1 and 41-2 start storing the first packet a and the second packet b, and switch the empty signals L1 and L2 from the value "1" to the value "0" from the start point. . Therefore, each signal indicating the value "1" obtained by inverting each of the empty signals L1 and L2 having the value "0" is added to each of the AND circuits 32-1 and 32-2 in the transmission unit 44. Further, since no packet is stored in the reception memory 41-n, the empty signal Ln indicates the value "1", and therefore the AND circuit 32-n outputs the value "0" obtained by inverting the empty signal Ln of the value "1". Is added.

On the other hand, when the first packet a and the second packet b are stored in each of the receiving memories 41-1 and 41-2, each read signal added to each of the receiving memories 41-1 to 41-n is read. Assuming that R1 to Rn all indicate the value "0", the OR circuit 31 outputs the signal R having the value "0". Therefore, the value "0" is supplied to each of the AND circuits 32-1 to 32-n. Each signal indicating the value "1" obtained by inverting the signal R of "" is added.

That is, each of the AND circuits 32-1 and 32-
2 is added with each signal indicating the value “1” obtained by inverting each of the empty signals L1 and L2 having the value “0”, and each signal indicating the value “1” obtained by inverting the signal R having the value “0” is added. Each is added. Therefore, each of the AND circuits 32-1,
32-2 outputs the dummy data D from the dummy generation unit 43 to the respective OR circuits 33-1 and 33-2, and outputs the respective receiving lines 3-1 and 3-2 from the respective OR circuits 33-1 and 33-2. , And the dummy data D is sent out to each other. Since the packet B has not been transmitted from any of the receiving memories 41-1 to 41-n, each OR circuit 33-1
No packet B is input to .about.33-n.

Further, a signal indicating a value “0” obtained by inverting the empty signal Ln having the value “1” is added to the AND circuit 32-n. Is not output to the OR circuit 33-n. Therefore, the packet B or the dummy data D is not transmitted to the reception line 3-n.

Since the value "0" is indicated by each of the empty signals L1 and L2, the control circuit 42 determines that each packet is stored in each of the reception memories 41-1 and 41-2. When this determination is made, first, the control circuit 42 switches the read signal R1 from the value “0” to the value “1”. In response, the receiving memory 41-1 outputs the first packet a as the packet B. This packet B is applied to each of the OR circuits 33-1 to 33-n.
On the other hand, since the read signal R1 of the value “1” is applied to the OR circuit 31, the signal R output from the OR circuit 31 indicates the value “1”. Therefore, each of the AND circuits 32-1 to 32-32
Each signal indicating a value “0” obtained by inverting the signal R having the value “1” is added to n.
-1 to 32-n transfer the dummy data D to each of the OR circuits 33-1.
~ 33-n.

That is, each of the OR circuits 33-1 to 33-n
The packet B, which is the first packet a, is added to each of the OR circuits 33-1 to 33-n.
n, the first packets a are respectively transmitted.

When the transmission of the first packet "a" is completed, the control circuit 42 switches the read signal R1 from the value "1" to the value "0" and returns the read signal R1 to the value "0" for a fixed period. 0 ”. During this period, the OR circuit 31 outputs the signal R having the value "0". Therefore, each of the AND circuits 32-1 to 32-n indicates the value "1" obtained by inverting the signal R having the value "0". Each signal is applied separately. Further, since the second packet b is still stored in the reception memory 41-2, the empty signal L2 having the value “0” is output from the reception memory 41-2, and the value “2” is output to the AND circuit 32-2. A signal indicating a value “1” obtained by inverting the empty signal L2 of “0” is added. Further, since no packet is stored in the reception memory 41-1 and the reception memory 41-n, the empty signal L1 and the empty signal Ln of the value "1" are output from the reception memory 41-1 and the reception memory 41-n.
Are respectively output to the AND circuit 32-1 and the AND circuit 32-n, each signal indicating the value "0" obtained by inverting the empty signal L1 and the empty signal Ln having the value "1".

That is, to the AND circuit 32-2, a signal indicating the value "1" obtained by inverting the signal R having the value "0" and a signal indicating the value "1" obtained by inverting the empty signal L2 having the value "0" are added. Therefore, the dummy data D is output from the AND circuit 32-2 to the OR circuit 33-2, and the dummy data D is transmitted from the OR circuit 33-2 to the reception line 3-2. The AND circuit 32-1 and the AND circuit 32-
Since the n and the respective signals indicating the value “0” obtained by inverting the empty signal L1 of the value “1” and the empty signal Ln are added to the n, the AND circuit 32-1 and the AND circuit 32-
n does not output the dummy data D. Therefore, the dummy data D is not output to the reception lines 3-1 and 3-n.
Is not sent. Since each of the read signals R1 to Rn is set to the value "0" for a certain period, the packet B is not input to each of the OR circuits 33-1 to 33-n. No packet B is sent to 3-n.

Next, the control circuit 42 switches the read signal R2 from the value “0” to the value “1”, and in response, the receiving memory 41-2 outputs the second packet “b” as the packet B. This packet B is transmitted to each of the OR circuits 33-1 to 33-n.
Respectively. On the other hand, the read signal R2 of the value “1”
Is added to the OR circuit 31, so that the signal R output from the OR circuit 31 indicates the value "1". Therefore, each signal indicating the value "0" obtained by inverting the signal R having the value "1" is added to each of the AND circuits 32-1 to 32-n. Dummy data D
To each of the OR circuits 33-1 to 33-n.

That is, each of the OR circuits 33-1 to 33-n
, A packet B, which is a second packet b, is added, and each of the receiving circuits 3-1 to 3-
n, and the second packet b is sent to each of them.

In this way, the first packet a and the second packet b are transmitted from the two terminal devices 1-1 and 1-2 to the central station 4, and from the central station 4 all the terminal devices 1 -1 to 1-n. Here, during a period in which at least a part of the first packet a is stored in the reception memory 41-1, the dummy data D or the first data is transmitted to the reception line 3-1 between the terminal device 1-1 and the centralized station 4. Is transmitted. In addition, during a period in which at least a part of the second packet b is stored in the reception memory 41-2, the dummy data D and the first data are provided on the reception line 3-2 between the terminal device 1-2 and the centralized station 4. Packet a or second packet b has been transmitted. Of course, all the receiving lines 3-1 to 3-
In n, the first packet a is transmitted at the same timing, and the second packet b is transmitted at the same timing.

When any signal is transmitted to each of the receiving lines 3-1 to 3-n, each of the terminal devices 1-1 to 1-n transmits through each of the transmitting lines 2-1 to 2-n. No packet is transmitted to the central station 4. Such a function is well known and is used in a conventional star communication network.

Therefore, for example, the terminal device 1-1 receives the dummy data D or the first packet a during a period in which at least a part of the first packet a described above is stored in the reception memory 41-1. Since the packet is received through the line 3-1, a new packet following the first packet a is not transmitted to the central station 4 through the transmission line 2-1. For this reason, a situation in which a new packet must be stored in the reception memory 41-1 while at least a part of the first packet a is stored in the reception memory 41-1 occurs. Therefore, the packet already stored in the reception memory 41-1 or a new packet is not discarded at all. Similarly, during a period in which at least a part of the second packet b described above is stored in the reception memory 41-2, the terminal device 2-2 performs:
Since the dummy data D and the first packet a or the second packet b have been received through the reception line 3-2, a new packet following the second packet b is transmitted to the transmission line 2-2.
, And no packet or new packet already stored in the reception memory 41-2 is discarded at all. of course,
All the terminal devices 1-1 to 1-n have respective reception lines 3
If no packet or dummy data has been transmitted to -1 to 3-n, the packet is transmitted to each transmission line 2 at that time.
It can be transmitted to the central station 4 through -1 to 2-n.

FIG. 5 is a block diagram showing a storage type star communication network to which another embodiment of the transmission control system according to the present invention is applied. In this embodiment, instead of the reception memories 41-1 to 41-n and the transmission unit 44 in the storage type star communication network shown in FIG. It is configured using. In FIG. 5, parts that perform the same operations as those of the storage type star communication network shown in FIG. 1 are denoted by the same reference numerals for convenience of explanation.

Each of the receiving memories 51-1 to 51-n stores each packet transmitted from each of the terminal devices 1-1 to 1-n through each of the receiving lines 3-1 to 3-n. And each has a storage capacity enough to store two packets. These receiving memories 41-1 to 41-1
-N is configured using, for example, a FIFO type semiconductor memory, and outputs not only the empty signals L1 to Ln but also the full signals F1 to Fn.
The empty signal indicates a value “0” when at least one packet is stored or is being stored in the reception memory that outputs the empty signal, and indicates the reception signal that outputs the empty signal. If the memory is empty, it indicates the value "1". On the other hand, this full signal indicates the value "1" when two packets are stored in the receiving memory outputting the full signal, that is, when the storage is performed until the storage capacity of the receiving memory becomes full. When the storage capacity of the receiving memory becomes empty, the value is switched to "0".

The transmitting section 52 is constructed as shown in FIG. 6. Instead of the AND circuits 32-1 to 32-n in the transmitting section 44 shown in FIG.
53-n, and each of the receiving memories 51-1 to 5-5
1-n from the respective AND circuits 53-1
To 53-n.

In such a configuration, for example, the first packet a is transmitted from the terminal device 1-1 to the centralized station 4, and two second packets a are transmitted from the terminal device 1-2 to the centralized station 4.
When the packet b and the third packet c are continuously transmitted, the central station 4 performs an operation according to the timing chart shown in FIG.

First, when the first packet a and the second packet b are transmitted from the terminal devices 1-1 and 1-2 to the transmission lines 2-1 and 2-2, respectively, Each of the reception memories 51-1 and 51-2 starts storing the first packet a and the second packet b. From this start point, the empty signals L1 and L2 are changed from the value "1" to the value "0", respectively. Switch.

Since the value "0" is indicated by each of the empty signals L1 and L2, the control circuit 42 determines that each packet is stored in each of the reception memories 51-1 and 51-2, and first reads the data. The signal R1 is switched from the value “0” to the value “1”. In response, the receiving memory 51
-1 outputs the first packet a as packet B.
This packet B is applied to each of the OR circuits 33-1 to 33-n. On the other hand, since the read signal R1 of the value “1” is applied to the OR circuit 31, the signal R output from the OR circuit 31 indicates the value “1”. Therefore, each AND circuit 53
−1 to 53-n are added with respective signals indicating a value “0” obtained by inverting the signal R having the value “1”.
Each of the AND circuits 53-1 to 53-n does not send the dummy data D to each of the OR circuits 33-1 to 33-n.

That is, each of the OR circuits 33-1 to 33-n
The packet B, which is the first packet a, is added to each of the OR circuits 33-1 to 33-n.
n, the first packets a are respectively transmitted.

When the first packet a is transmitted in this manner, when the third packet c is transmitted from the terminal device 1-2 to the transmission line 2-2 following the second packet b,
The reception memory 51-2 in the central station 4 starts storing the second packet, and switches the full signal F2 from the value "0" to the value "1" from this start point. Therefore, the full signal F2 of the value "1" is applied to the AND circuit 53-2. Since the second packet is not stored in the reception memory 51-1 and the packet is not stored in the reception memory 51-n, the AND circuit 53-1 and the AND circuit 53 are not stored.
The full signal F1 and the full signal Fn having the value “0” are added to −n.

Next, when the transmission of the first packet a is completed, the control circuit 42 switches the read signal R1 from the value "1" to the value "0" and returns the read signal R1 to the read signal R1 for a predetermined period. Set the value to “0”. During this period, the OR circuit 31 outputs the signal R having the value "0". Therefore, each of the AND circuits 32-1 to 32-n indicates the value "1" obtained by inverting the signal R having the value "0". Each signal is applied separately. Accordingly, the full signal F2 of the value "1" is added to the AND circuit 53-2, and a signal indicating the value "1" obtained by inverting the signal R of the value "0" is added to the AND circuit 53-2. Outputs dummy data D, and the dummy data D is sent to the reception line 3-2 via the OR circuit 33-2. Further, the AND circuit 53-1 and the AND circuit 53-n provide the full signal F1 and the full signal Fn of the value “0”.
Are not added, the dummy data D is not output from the AND circuit 53-1 and the AND circuit 53-n. Therefore, the reception line 3-1 and the reception line 3-
No dummy data D is sent to n. Since each of the read signals R1 to Rn is set to the value "0" for a certain period, the packet B is not input to each of the OR circuits 33-1 to 33-n. No packet B is sent to 3-n.

Next, the control circuit 42 switches the read signal R2 from the value "0" to the value "1", and in response to this, the receiving memory 51-2 stores the second packet b and the third packet c.
Is output as each packet B. These packets B are applied to the respective OR circuits 33-1 to 33-n. On the other hand, the read signal R2 having the value “1” is supplied to the OR circuit 31.
, The signal R output from the OR circuit 31
Indicates the value “1”. Therefore, each of the AND circuits 53-1 to 5-5
Each signal indicating the value "0" obtained by inverting the signal R having the value "1" is added to 3-n, and each of the AND circuits 53-1 to 53-n outputs the dummy data D to each of the OR circuits 33.
-1 to 33-n.

That is, each of the OR circuits 33-1 to 33-n
Is added to each packet B, which is the second packet b and the third packet c, and each of the OR circuits 33-1 to 33-1
The second packet b and the third packet c are continuously transmitted from 33-n to the receiving lines 3-1 to 3-n, respectively.

Here, during the period when both the second packet b and the third packet c are stored in the reception memory 51-2, the reception line 3-2 between the terminal device 1-2 and the centralized station 4 is connected. Obviously, the dummy data D or the packet has been transmitted. For this reason, the terminal device 1-2 receives some signal through the reception line 3-2 during that period, and sends a new packet following the third packet c through the transmission line 2-2 to the central station 4. Never sent to. Therefore, when two packets are stored in the reception memory 51-2, a new packet is transmitted to the reception memory 51-2.
In this case, there is no possibility that the packet has to be stored in the receiving memory 51-2, so that the packet already stored in the receiving memory 51-2 or a new packet is not discarded at all.

[0051]

As described above, according to the present invention, when communication data is stored up to a predetermined amount in the storage means corresponding to the terminal device, the communication data or dummy data is transferred from the central station to the terminal device. Since the data is always transmitted, the terminal device does not transmit new communication data to be stored in the storage means to the central station. Therefore, even when the communication data is stored in the storage means, a situation in which new communication data has to be stored does not occur, and therefore, the communication data is not discarded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a storage-type star communication network to which an embodiment of a transmission control method according to the present invention is applied.

FIG. 2 is a flowchart showing a processing procedure by a control unit of a central station in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a configuration of a transmitting unit of a centralized station in the embodiment shown in FIG.

FIG. 4 is a timing chart used for explaining data communication between the terminal device and the central station in the embodiment shown in FIG. 1;

FIG. 5 is a block diagram showing a storage-type star communication network to which another embodiment of the transmission control method according to the present invention is applied.

FIG. 6 is a block diagram showing a configuration of a transmitting unit of the central station in the embodiment shown in FIG.

FIG. 7 is a timing chart used to explain data communication between the terminal device and the central station in the embodiment shown in FIG. 5;

FIG. 8 is a block diagram showing a schematic configuration of a general star communication network.

[Explanation of symbols]

1-1 to 1-n: terminal device, 2-1 to 2-n: transmission line,
3-1 to 3-n reception line, 4 centralized station, 41-1 to 41
-N, 51-1 to 51-n reception memory, 42 control circuit, 43 dummy generation section, 44, 52 transmission section, 31,
33-1 to 33-n... OR circuits, 32-1 to 32-n,
53-1 to 53-n ... AND circuits.

Claims (1)

(57) [Claims] An information processing apparatus comprising: a plurality of terminal devices; and a central station for transmitting and receiving communication data between the terminal devices, wherein the central station receives communication data from any of the terminal devices, This communication data is transmitted to each of the terminal devices, and each of the terminal devices is provided corresponding to each of the terminal devices in a storage-type star communication network that performs transmission to a central station while avoiding a data reception period. A plurality of storage units each storing communication data transmitted and received from the terminal device to the centralized station, and respectively outputting a storage state signal indicating that the communication data has been stored to a predetermined amount. And dummy data generating means for generating dummy data, and transmitting communication data in the storage means from the centralized station to each of the terminal devices, and transmitting the communication data from one of the storage means to the terminal device. When the storage state signal is output, one of the communication data and the dummy data from the dummy data generation unit is constantly transmitted to the terminal device corresponding to the storage unit that has output the storage state signal. A transmission control method in a storage-type star communication network, comprising: