JP3124730B2 - Chopper comparator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitably used for an analog / digital converter or the like, and applies a reference voltage after applying an input voltage to a capacitor, and determines whether the capacitor is in a charged state or a discharged state. And a chopper comparator circuit for comparing the input voltage with the reference voltage.

[0002]

2. Description of the Related Art Conventionally, an analog / digital converter compares an input voltage of an analog signal within a sampling period with a reference voltage by a comparison circuit, and converts the input analog signal into a digital signal using the comparison result. Converting.

As a comparison circuit of the analog / digital converter, for example, a chopper comparator circuit is used. This chopper comparator circuit includes a capacitor,
A first MOS transistor which is connected to one end of the capacitor and is an analog switch for selectively applying an input voltage; a second MOS transistor which is connected to one end of the capacitor and which is an analog switch for selectively applying a reference voltage; A third MOS transistor that is connected to the other end of the capacitor and that is an analog switch that selectively applies a predetermined voltage. Then, after the first MOS transistor and the third MOS transistor are turned on and the input voltage is applied to the capacitor, the second MOS transistor is turned on and a reference voltage is applied to the capacitor. The reference voltage and the input voltage are compared depending on which of the discharging states.

In recent years, even when the input voltage and the reference voltage have a small potential difference due to the low power and high precision of the electronic equipment including the analog / digital converter, the chopper comparator circuit can control the input voltage and the reference voltage. It is necessary to compare the voltage with the voltage with high accuracy. However, due to the phenomenon of clock feedthrough, it is difficult to accurately compare the input voltage, which is a small potential difference, with the reference voltage. The clock feedthrough is a phenomenon that occurs when a MOS transistor, which is an analog switch, is turned from an off state to an on state or from an on state to an off state. For example, when the MOS transistor is turned off, This means that the parasitic capacitance generated between the source electrode and the drain electrode flows into the capacitor.

[0005]

As a technique for eliminating the influence of the clock feedthrough described above, a clock signal applied to the gate electrode of the first MOS transistor and a third
Japanese Patent Publication No. Hei 6-91419 discloses a technique in which the third MOS transistor is turned off before the first MOS transistor by giving a minute phase difference to a clock signal applied to the gate electrode of the MOS transistor. It is proposed in the gazette.

However, in order to provide clock signals having different phases to the gate electrodes of the first MOS transistor and the third MOS transistor, it is necessary to further provide a new signal line, and additionally control the clock signal. Since a control circuit is also required, there is a problem that a circuit configuration becomes complicated and a chip area increases.

Further, as a technique for eliminating the influence of clock feedthrough, the threshold voltage of the third MOS transistor is set higher than the threshold voltage of the first MOS transistor, so that the third MOS transistor is connected to the first MOS transistor.
A technique for turning off the transistor prior to the transistor is proposed in Japanese Patent Publication No. 8-34410.

According to this technique, it is not necessary to newly provide a signal line or the like, so that it is possible to prevent a complicated circuit configuration and an increase in chip area. However, since it is necessary to set two types of threshold voltages, there is a problem that the process of manufacturing the chopper comparator circuit becomes complicated.

An object of the present invention is to provide a high-precision chopper comparator circuit while preventing an increase in circuit scale and complication of a circuit manufacturing process. As an issue.

[0010]

According to the present invention, there is provided a chopper comparator circuit comprising: a capacitor; a first field-effect transistor for selectively applying an input voltage to one end of the capacitor; A second field effect transistor for selectively applying a reference voltage to one end of the capacitor; and a third field effect transistor for selectively applying a predetermined voltage to the other end of the capacitor; When the effect transistor and the third field-effect transistor are on, the second field-effect transistor is turned off to charge the capacitor with a charge corresponding to the input voltage; And when the third field-effect transistor is off, the second field-effect transistor is turned on and the reference The capacitor is configured to allow charging or discharging the electric charge in response to pressure, a first field effect DOO
The value of (parasitic resistance × parasitic capacitance) of the transistor is the third
From (parasitic resistance x parasitic capacitance) of a field effect transistor
So that the first field-effect transistor and
Layout of gate electrode portion of third field effect transistor
The shape of the third field-effect transistor
Turns off faster than the first field-effect transistor.
It is characterized by setting so that.

According to the above configuration, the first field-effect transistor and the third field-effect transistor do not change the threshold voltage, but the first field-effect transistor and the first field-effect transistor use the first capacitance and the first resistance by the parasitic capacitance and the parasitic resistance set based on the layout shape of the gate electrode portion. The time required for the voltage level of the field effect transistor to reach the low level from the high level can be made longer than that of the third field effect transistor. Thus, the capacitor is not affected by the fluctuation of the charge due to the clock feedthrough of the first field-effect transistor, so that the input voltage and the reference voltage can be compared with high accuracy.

The layout may be such that the gate width of the gate electrode of the first field effect transistor is longer than the gate width of the gate electrode of the third field effect transistor.

Accordingly, the area of the gate electrode portion facing the channel of the first field effect transistor is:
It is larger than the area of the gate electrode portion facing the channel of the third field effect transistor. Therefore, the parasitic capacitance at the gate electrode of the first field-effect transistor is
It becomes larger than the parasitic capacitance at the gate electrode of the third field-effect transistor. Since the value of (parasitic capacitance × parasitic resistance) of the first field-effect transistor can be made larger than that of the third field-effect transistor, the time required for the first field-effect transistor to be completely turned off is reduced. It can be longer than the third field effect transistor. For this reason, the third field-effect transistor is turned off earlier than the first field-effect transistor, and clock feedthrough in the first field-effect transistor is not performed. Voltage and can be compared. Note that the gate length of the gate electrode of the first field-effect transistor may be longer than the gate length of the gate electrode of the third field-effect transistor.

The length of the wiring to the gate electrode of the first field-effect transistor may be longer than the length of the wiring to the gate electrode of the third field-effect transistor.

Accordingly, the resistance value (that is, the value of the parasitic resistance) of the wiring to the gate electrode of the first field-effect transistor becomes larger than the resistance value of the wiring to the gate electrode of the third field-effect transistor. . The value of (parasitic capacitance × parasitic resistance) of the first field-effect transistor is
Therefore, the time required for the first field-effect transistor to be completely turned off can be made longer than that of the third field-effect transistor. For this reason, the third field-effect transistor is better than the first field-effect transistor.
Since the transistor is turned off quickly and clock feedthrough is not performed in the first field-effect transistor, the input voltage and the reference voltage can be compared with high accuracy.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a chopper comparator circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an internal configuration of a chopper comparator circuit to which the present invention is applied. The chopper comparator circuit includes an n-type MOS transistor 1 as a first field-effect transistor, an n-type MOS transistor 2 as a second field-effect transistor, an n-type MOS transistor 3 as a third field-effect transistor, It comprises a capacitor 4 and an inverter 5 composed of CMOS. This MOS transistor 1,
The MOS transistor 2 and the MOS transistor 3 are used as analog switches. When a voltage Vdd is applied to the gate electrode as a gate voltage, the MOS transistor 2 and the MOS transistor 3 are turned on, that is, the source-drain is turned on. When turned on,
The MOS transistor 1 applies an input voltage Va to one end of the capacitor 4, the MOS transistor 2 applies a reference voltage Vr to one end of the capacitor 4, and the MOS transistor 3 applies a constant voltage applied to the output terminal OUT. A predetermined voltage indicating a value is applied to the other end of the capacitor 4. The inverter 5 includes an n-type MOS transistor and a p-type MOS transistor connected in series, and has an input side connected to the other end of the capacitor 4.

A first clock signal (φ) is applied to the gate electrodes of the MOS transistors 1 and 3, and the first clock signal (φ) is applied to the gate electrodes of the MOS transistor 2.
A second clock signal (φB) having a phase 180 ° different from that of the clock signal (φ) is applied. First clock signal (φ)
And the second clock signal (φB) indicates the power supply voltage Vdd when it is at the high level, and indicates the power supply voltage Vdd when it is at the low level.
Indicates ss. Therefore, the MOS transistor 1 and the MOS transistor
A high-level first clock signal (φ) is applied to the gate electrode of the transistor 3 so that the MOS transistor 1 and the MOS transistor
When the S-transistor 3 is on, that is, the source-drain is conducting, a low-level second clock signal (φB) is applied to the gate electrode of the MOS transistor 2, so that the MOS transistor 2 is off, ie, The source and drain are cut off. Conversely, when the low-level first clock signal (φ) is supplied and the MOS transistors 1 and 3 are off, the high-level second clock signal (φB) is supplied, and the MOS transistor 2 is turned on. State.

FIG. 2A shows the MO on the gate electrode side.
FIG. 2 is a schematic diagram showing the structure of the S transistor 1 and FIG.
(B) is a schematic diagram showing the structure of the MOS transistor 3 on the gate electrode side. The gate length L1 of the gate electrode 11 of the MOS transistor 1 is set longer than the gate length L3 of the gate electrode 13 of the MOS transistor 3, and the gate width W1 of the gate electrode 11 is set to the gate width W of the gate electrode 13.
Set longer than 3. For example, the gate length L1 is three times the gate length L3, and the gate width W1 is three times the gate width W3. Further, the length Y1 of the wiring of the gate electrode 11 is formed to be longer than the length Y3 of the wiring of the gate electrode 13. In particular, the length X1 of the wiring up to the gate electrode 11 portion (the hatched portion in FIG.
The wiring is formed so as to be longer than the length X3 of the wiring up to the hatched portion (b).

By setting the gate length and the gate width as described above, the area where the gate electrode 11 and the channel below the gate electrode 11 face each other (the shaded portion in FIG. 2) is reduced. Is larger than the area facing the channel. The length X1 of the wiring to the gate electrode 11 is longer than the length X3 of the wiring to the gate electrode 13. As a result, the value of (parasitic capacitance × parasitic resistance) of the MOS transistor 1 becomes 9 times or more the value of the MOS transistor 3. Therefore, the MOS transistor 1 and the MOS transistor
Even if the threshold voltage of the transistor 3 is the same, the time required for the MOS transistor 1 and the MOS transistor 3 to be completely turned off is M
It is longer than the OS transistor 3.

Next, the operation of the chopper comparator circuit having the above configuration will be described. When a high-level first clock signal (φ) is applied to the gate electrodes of the MOS transistors 1 and 3, the MOS transistors 1 and 3 are turned on, and the charge corresponding to the input voltage Va is stored in the capacitor 4. Charged. At this time, the low-level second clock signal (φB) is applied to the gate electrode of the MOS transistor 2, and the MOS transistor 2 is turned off.

Then, when the first clock signal (φ) falls to a low level, the MOS transistor 3 has a higher MO
The transistor is completely turned off before the S transistor 1, and the MOS transistor 1 is completely turned off with a sufficient delay. This is because, as described above, the value of (parasitic capacitance × parasitic resistance) of the MOS transistor 1
This is because it is 9 times or more larger than the above.

When the MOS transistor 1 and the MOS transistor 3 are completely turned off, the second clock signal (φB) rises to a high level.
The OS transistor 2 is turned on, and the reference voltage Vr is applied to the capacitor 4.

In this case, the input voltage Va is changed to the reference voltage Vr
If it is larger than the above, the charge charged on one end of the capacitor 4 is discharged through the source-drain of the MOS transistor 2, so that the charge (e.g., electrons) charged on the other end is also discharged. The charge (electrons) at the input portion of the inverter 5 becomes excessive, and the inverter 5 outputs a high-level signal to the output terminal OUT. On the other hand, when the input voltage Va is smaller than the reference voltage Vr, one end of the capacitor 4 is further charged by the reference voltage Vr, and the other end of the capacitor 4 is further charged (electrons). Therefore, the charge (electrons) at the input portion of the inverter 5 is depleted, and a low-level signal is output from the inverter 5 to the output terminal OUT.

As described above, the MOS transistor 3 is turned off prior to the MOS transistor 1 so that the clock feedthrough charge including the variable potential component based on the input voltage Va is not charged in the capacitor 4. be able to. That is, the MOS transistor 3
Is turned off first, and one end of the capacitor 4 is connected to the output terminal O
When separated from the UT, the charges charged to both electrodes of the capacitor 104 are kept constant at that time. Therefore, this charge includes clock feed-through charges generated when the MOS transistor 3 is turned off. There is no influence of clock feedthrough due to the subsequent OFF operation of the MOS transistor 1. Therefore, the electric charge charged in the capacitor 4 does not include the fluctuation potential component of the clock feedthrough based on the input voltage Va. Therefore, as described above, the reference voltage Vr and the input voltage Va depend on the signal level output from the output terminal OUT. Can be compared with high accuracy.

The input voltage Va that changes within a certain range
Is the lowest voltage value, the MOS transistor 1 is turned off sufficiently later than the MOS transistor 3 so that the gate lengths, gate widths, and gate electrode portions of the gate electrodes of the MOS transistors 1 and 3 May be set.

Further, in the above-described embodiment, the gate length, the gate width, and the length of the wiring to the gate electrode portion of the MOS transistors 1 and 3 are adjusted. However, if (parasitic resistance × parasitic capacitance) of the MOS transistor 1 can be made larger than (parasitic resistance × parasitic capacitance) of the MOS transistor 3, either one or two may be adjusted. Good.

In the above-described embodiment, an n-type MOS transistor is used for each of the MOS transistors 1 to 3 as an analog switch.
Type MOS transistor may be used, or an analog switch composed of CMOS may be used. Further, at least a field effect transistor having a MIS structure may be used as an analog switch.

[0029]

According to the invention described above, the circuit configuration and the chip area are prevented from increasing as in the prior art, and the layout of the gate electrode of the transistor can be changed without increasing the manufacturing process. Only by setting, it is possible to easily prevent an error from occurring due to clock feedthrough, and to output a highly accurate comparison result.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an internal configuration of a chopper comparator circuit applied to the present invention.

FIG. 2A is a schematic diagram illustrating a shape of a gate electrode of a transistor to which an input voltage is selectively applied, and FIG. 2B is a diagram of a transistor to which a predetermined voltage is selectively applied; FIG. 3 is a schematic diagram illustrating a shape of a gate electrode.

[Explanation of symbols]

 1 to 3 MOS transistor 4 Capacitor 5 Inverter 11, 13 Gate electrode L1, L3 Channel length Va Input voltage Vr Reference voltage W1, W3 Channel width X1, X3 Length of wiring to gate electrode

Claims (4)

(57) [Claims] A first field-effect transistor for selectively applying an input voltage to one end of the capacitor; a second field-effect transistor for selectively applying a reference voltage to one end of the capacitor; A third field-effect transistor for selectively applying a predetermined voltage to the other end of the capacitor, wherein the first and third field-effect transistors are on when the second and third field-effect transistors are on. A field-effect transistor is turned off to charge the capacitor with a charge corresponding to the input voltage, and the second field-effect transistor is turned off when the first field-effect transistor and the third field-effect transistor are off. and the transistor in the on state in response to the reference voltage and configured such that the capacitor can be charged or discharged electric charge, first field Of fruit transistor (parasitic resistance × parasitic capacitance)
Of the third field-effect transistor (parasitic resistance
× parasitic capacitance) so as to be larger than the value of the first electric field.
Of the third effect transistor and the third field effect transistor.
3rd field effect by setting the layout shape of the gate electrode
Transistors are better than first field-effect transistors
The switch is set to turn off quickly.
Chopper comparator circuit. 2. The layout according to claim 1, wherein the gate width of the gate electrode of the first field-effect transistor is longer than the gate width of the gate electrode of the third field-effect transistor. A chopper comparator circuit as described. 3. The layout according to claim 1, wherein the gate length of the gate electrode of the first field effect transistor is longer than the gate length of the gate electrode of the third field effect transistor. 3. The chopper comparator circuit according to 2. 4. The layout of the first field-effect transistor, wherein the length of the wiring to the gate electrode is longer than the length of the wiring to the gate electrode of the third field-effect transistor. Claims 1 to 3
The chopper comparator circuit according to any one of the above.