JP3119996B2 - Multi-scan display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image signal, and more particularly to a multi-scan display device suitable for displaying an image signal of a personal computer, a workstation, a multimedia device or the like.

[0002]

2. Description of the Related Art A display device used for a personal computer, a workstation or the like includes a special display device designed and manufactured for a specific model and an image signal having a certain range of horizontal and vertical frequencies. There is a multi-scan display device that can display the data.

There are many types of personal computers currently on the market having different architectures, and even in the same architecture, there are a plurality of image signal modes, each having a resolution (number of pixels in the vertical and horizontal directions), a horizontal frequency, and a vertical frequency. Are different. The multi-scan display device is designed and manufactured so that one display device can cope with a plurality of image signal systems. Normally, parameters (for displaying image signals of a plurality of systems on a screen at the time of factory shipment) are set in advance. The number of horizontal dots, the number of vertical lines, the dot clock, the clock phase for A / D conversion, the horizontal position, and the vertical position) are preset.

FIG. 5 shows a configuration of a conventional example of such a multi-scan display device. In FIG. 5, a conventional multi-scan display device has an image signal input terminal 1.
4 and an analog / digital switch (hereinafter, A /
A D changeover switch 15, an amplifier 16, an analog / digital converter (hereinafter abbreviated as ADC) 17,
Memory control circuit 4 and field memory 11
And a liquid crystal interface (hereinafter abbreviated as liquid crystal I / F) 1
2, a liquid crystal panel 13, a phase comparator 1, a low-pass filter (hereinafter abbreviated as LPF) 2, a voltage controlled oscillator (hereinafter abbreviated as VCO) 3, a CPU 5, a control panel 7, and an EE-PROM. And a reference clock generator 10.

[0005] The memory control circuit 4 in the range surrounded by the dashed line includes a selector 41 and a synchronizing signal control circuit 4.
2, a clock control circuit 43, and a 1 / N frequency dividing circuit 44
, A field memory write control circuit 45, a field memory read control circuit 46, and a liquid crystal display timing generation circuit 47.

[0006] The conventional multi-scan display device having the above configuration operates as follows. First, an image signal is input to the image signal input terminal 14. The A / D switch 15 set by the user generates a selector 41 switching signal. If the input image signal is a digital signal, the A / D switch 15 directly switches the selector 41.
And to an amplifier 16 if the signal is an analog signal. The amplifier 16 amplifies the analog image signal to a level at which AD conversion can be performed, and outputs the signal to the ADC 17. ADC17
Converts the input signal into 8-bit digital data for each color at the timing adjusted by the clock control circuit 43 and outputs the data to the selector 41 as 24-bit data for a three-color meter.

The selector 41 of the memory control circuit 4
Switches between the digital image signal from the A / D switch 15 and the digital image signal from the ADC 17 according to the instruction of the A / D switch 15 and outputs it to the field memory 11.

The digital signal sent from the selector 41 is applied to the field memory 1 in accordance with the write address and write instruction sent from the field memory write control circuit 45.
Written to 1. Further, the field memory read control circuit 46 instructs a read address of the field memory 11 and a read timing suitable for the liquid crystal panel 13, and the content read according to the read address is a liquid crystal I / F.
It is sent to 12. The liquid crystal I / F 12 receives a display timing signal from the liquid crystal display timing generation circuit 47 based on a display timing signal.
By performing signal conversion according to the driving mode of the liquid crystal panel 13,
A drive signal for the liquid crystal panel 13 is generated.

The synchronization signal control circuit 42 receives a horizontal synchronization signal (HSYNC) and a vertical synchronization signal (VSYNC) from the image signal input terminal 14. Further, the synchronization signal control circuit 42 has a built-in horizontal cycle counter, and outputs a horizontal cycle count value by the horizontal cycle counter in response to the status read of the input image signal from the CPU 5.

The dot clock generation circuit includes a phase comparator 1
, LPF2, VCO3, and 1 / N frequency dividing circuit 44. Further, the frequency dividing ratio N of the 1 / N frequency dividing circuit 44 can be set from the CPU 5, and is a so-called programmable frequency divider. The dot clock is a timing signal corresponding to each dot of pixel data, and is usually not directly output from a personal computer. Therefore, it is necessary to generate an image signal by sampling an input image signal.

In the above dot clock generation, the VCO
3 is divided by a 1 / N frequency dividing circuit 44 to become a feedback signal (HSYNCF).
Given to. Also, the input horizontal synchronization signal (HSYNC)
Is also supplied to the phase comparator 1. The phase comparator 1 is HSY
The NC and the HSYNCCF are compared, and if there is a phase difference between the two inputs, an output voltage corresponding to the phase difference is output.

The output of the phase comparator 1 passes through only the low-frequency component by the LPF 2 and is returned to the VCO 3 again. Thus, a signal synchronized with the horizontal synchronizing signal and having a frequency N times the horizontal synchronizing signal is obtained at the output of the VCO 3. by the way,
Since the CPU 5 is informed of the cycles of the horizontal synchronization signal and the vertical synchronization signal of the input image signal, the CPU 5 calculates one cycle from these cycles.
The number of dots N per line is determined, and the 1 / N frequency dividing circuit 4
The division ratio N is set to 4. Therefore, a signal having a frequency that is N times the frequency of the horizontal synchronizing signal obtained at the output of the VCO 3 becomes a signal indicating the timing of each pixel of the input image signal, and the sampling clock of the ADC 17 that performs A / D conversion of the input image signal and It is used as a write clock for the field memory 11.

Next, a description will be given of a method of determining an input image signal in the conventional multi-scan display device having the above configuration. FIGS. 6 and 7 are flowcharts showing the determination of the input image signal and the switching portion of the scan parameter based on the determination from the program incorporated in the CPU 5.

First, the status of the input image signal is read (step S100). This status includes the presence or absence of an input image signal, the state of the analog / digital changeover switch 15, an interlace flag indicating whether the input image signal is an interlace signal or a non-interlace signal, and the value of a horizontal synchronization counter incorporated in the synchronization signal control circuit 42. .

Next, the presence or absence of an input image signal is checked (step S101). If there is no input image signal, it is assumed that the image signal is from a model that does not support mode discrimination or is not compatible,
The display on the LCD is stopped (S107). If there is an input image signal, then the analog / digital switch 1
The state of No. 5 is determined (step S102).

If it is a digital input, the interlace flag is checked (step S103). If the interlace flag is set, it is determined that the image signal is an image signal from a non-mode-determined or non-compatible model, and the display on the LCD is stopped (S107). If the interlace flag has not been set, then the value of the horizontal cycle counter is checked (step S104).

In step S104, the values of the horizontal cycle counter are respectively displayed in hexadecimal, and "0C" and "0
9 "," 08 ", and" 06 ", the modes of the input image signals are CGA (640 × 200 dots) and EG, respectively.
A (640 × 350 dots), EGA (640 × 350 dots)
Dot) and JEGA (640 × 480 dots), and the routine goes to Step S108. If the value of the horizontal cycle counter is any other value, the process proceeds to step S107 as a model that is not a mode discriminator or a non-compliant model.

In step S102, if the input is an analog input, the interlace flag is checked (step S105). If the interlace flag is set, it is determined that the input image signal is a PC. If the interlace flag is not set,
The value of the horizontal cycle counter is checked (step S106).

In step S106, the values of the horizontal cycle counter are respectively displayed in hexadecimal notation, "05" and "0".
If it is "6", "07", or "08", the mode of the input image signal is determined to be VGA, VGA, PC98, or PC98, and the process proceeds to step S108. The process proceeds to step S107 as a model that is not the mode discriminator or a non-compliant model.

In step S108, it is determined whether the mode of the input image signal determined this time is the same as or different from the mode of the input image signal determined last time. If the mode is the same as the previous mode, the mode set last time is continued, so the current process is not necessary, and the process proceeds to other processes. If the mode is different from the previous mode, the display on the LCD is stopped (step S109), the number of the input image signal is set (step S110), and the mode LED blinks, turns on or off according to the determined image signal number. The light is turned off (step S111).

Next, a parameter address corresponding to the set image signal number is read (step S11).
2) Using this address, the standard parameter memory 8
(Configured with EE-PROM)
It is stored in the internal RAM of the CPU 5 (step S11)
3). Next, parameters are set from the internal RAM of the CPU 5 to each part of the memory control circuit 4 (Step S).
114), according to the set parameters.
3 is started (step S115).

[0022]

However, in the above-described conventional multi-scan display device, only the image signals stored in advance in the standard parameter memory can be displayed, and the image signals not set in the standard parameter memory are input. In this case, there is a problem that the input image signal cannot be displayed on the display screen.

In view of the above problems, an object of the present invention is to allow a user to input an image signal in a mode in which parameters are not previously set in a standard parameter memory in accordance with the input image signal. To provide a multi-scan display device capable of setting a parameter in a non-volatile memory and thereafter displaying an image signal using the parameter set by the user when the same image signal is input in the mode set by the user. It is.

[0024]

In order to solve the above problems, the present invention has the following arrangement. That is, the present invention
In a multi-scan display device capable of displaying on a screen any of a plurality of image signals in which one or both of a scanning method and a signal transmission method are different from each other, image signals set in a manufacturing process and of different types are displayed on a screen. Parameter storage means for storing a plurality of sets of standard parameters, a parameter input means for a user to input user setting parameters, and a non-volatile user having at least one storage location for storing the user setting parameters. Setting parameter storage means, search means for searching for parameters compatible with the input image signal from the standard parameter storage means and the user setting parameter storage means, and controlling display of the image signal based on the searched parameters. Control means. It is a multi-scan display device according to claim.

In the present invention, the user setting parameters may include a horizontal pixel number, a vertical pixel number, a dot clock frequency, a phase, a horizontal position, and a vertical position. Further, in the present invention, a voltage controlled oscillator having a plurality of bands and generating a dot clock,
A dot clock divider that divides the dot clock; a phase comparator that compares the phase of the divided dot clock with a horizontal synchronization signal; and a voltage controller that passes a low-frequency signal output from the phase comparator. A low-pass filter for controlling the oscillator, an analog-to-digital converter for converting the control voltage from analog to digital, and a dot clock frequency controlled by the parameter input means at an end of the band. Band switching means for switching the band to an adjacent band based on the digital conversion value of the control voltage. Further, in the present invention, the screen can be a liquid crystal panel.

[0026]

According to the present invention, when an image signal which is not set as a standard parameter is input, the user can store a parameter corresponding to the input image signal in the user setting parameter storage means. By searching the setting parameter storage means and the conventional standard parameter storage means, a display control parameter suitable for the input image signal can be read.

[0027]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a multi-scan display device according to the present invention. In addition,
The same components as those of the related art shown in FIG. 5 are denoted by the same reference numerals. In FIG. 1, the multi-scan display device of the present embodiment includes an image signal input terminal 14, an A / D switch 15, an amplifier 16,
ADC 17, memory control circuit 4, field memory 11, liquid crystal I / F 12, liquid crystal panel 13
, Phase comparator 1, LPF2, VCO3, CPU
5, ADC 6, control panel 7, EE-P
It comprises a standard parameter memory 8 composed of a ROM, a user setting parameter memory 9 also composed of an EE-PROM, and a reference clock generator 10.

The memory control circuit 4 includes a selector 41, a synchronization signal control circuit 42, a clock control circuit 43, a 1 / N frequency dividing circuit 44, a field memory write control circuit 45, and a field memory read control. Circuit 46
And a liquid crystal display timing generation circuit 47.

In this embodiment having the above configuration, the components added in the present invention include an ADC 6, a user setting parameter memory 9, and two sub-programs built in the CPU 5, that is, a user setting parameter input means and This is a means for searching for a parameter corresponding to the input image signal from both the standard parameter and the user setting parameter. The other components use the same components as in the related art, and thus the same description will be omitted.

The dot clock generation circuit of this embodiment is a PLL comprising a phase comparator 1, an LPF 2, a VCO 3, and a programmable 1 / N frequency dividing circuit 44.
It has become. VOC3 is controlled by PLL voltages 1 to 4 V, respectively, as shown in FIG.
~ 35MHz, 14.5 ~ 25.5MHz, 7.5 ~ 1
It has a three-band configuration of 7.5 MHz. The PLL voltage is converted from analog to digital by the ADC 6 and read by the CPU 5.

The band selection of the VCO 3 is performed by selecting a dot clock adjustment button (for increasing the dot clock and a dot clock) included in the key switch of the control panel 7 when an image signal for which no parameter is set is input in a flowchart described later. It is used when adjusting the dot clock by using (for lowering). That is, every time the dot clock button is pressed, the PLL voltage goes up and down,
The CPU 5 checks the PLL voltage after each change,
When the PLL voltage is at an end in a range of 1 to 4 V (for example, 1.2 V).
V or less and 3.5 V or more), the band is switched to the adjacent band. If there are no adjacent bands, no switching occurs.

When the dot clock adjustment is completed,
Next, the parameters of the number of horizontal dots, the number of vertical lines, the clock, the phase, the horizontal position, and the vertical position are also set from key switches provided on the control panel 7, and the parameters read by the CPU 5 from the control panel 7 are set by the user. Setting parameter memory (EE
-PROM) 9 is written.

Next, a method of determining an input image signal in the multi-scan display device of this embodiment will be described. FIGS. 3 and 4 are flowcharts showing the determination of the input image signal and the switching portion of the scan parameter based on the determination from the program incorporated in the CPU 5.

First, the status of the input image signal is read (step S10). This status is
It includes the presence / absence of an input image signal, the state of the analog / digital changeover switch 15, an interlace flag indicating whether the input image signal is an interlace signal or a non-interlace signal, and the value of a horizontal synchronization counter incorporated in the synchronization signal control circuit.

Next, the presence or absence of an input image signal is checked (step S11). If there is no input image signal, it is determined that the image signal is out of the mode determination, and the process proceeds to the dot clock adjustment mode (step S17). If there is an input image signal, then the state of the analog / digital switch 15 is determined (step S12).

If it is a digital input, the interlace flag is checked (step S13). If the interlace flag is set, it is determined that the signal is a non-standard image signal, and the process proceeds to the dot clock adjustment mode (step S).
17). If the interlace flag has not been set, then the value of the horizontal cycle counter is checked (step S14).

In step S14, the values of the horizontal cycle counter are each displayed in hexadecimal notation, "0C", "09",
When “08” and “06”, the mode of the input image signal is
CGA (640 x 200 dots) and EGA (6
It is determined that they are 40 × 350 dots), EGA (640 × 350 dots), and JEGA (640 × 480 dots), and the process proceeds to step S25. If the value of the horizontal cycle counter is other than that, the process proceeds to step S17 to enable the user to set parameters.

If it is determined in step S12 that the input is an analog input, then the interlace flag is checked (step S15). If the interlace flag is set, it is determined that the input image signal is a PC.
If the interlace flag is not set, the value of the horizontal cycle counter is checked (step S16).

In step S16, the values of the horizontal cycle counter are each displayed in hexadecimal, and are "05", "06",
When “07” and “08”, the mode of the input image signal is
It is determined that they are VGA, VGA, PC98, and PC98, respectively, and the process proceeds to step S25. If the value of the horizontal cycle counter is other than that, the process proceeds to step S17 to enable the user to set parameters.

In step S17, the dot clock adjustment mode is set, and then the PLL voltage of the VCO 3 is checked (step S18). In checking the PLL voltage, first, it is checked whether it is 3.5 V or more (step S19). If it is more than 3.5V, switch the oscillation frequency range of VCO3 to the higher adjacent band,
If the band is the highest band, no switching is performed (step S2).
0). If it is less than 3.5 V, it is subsequently checked whether it is less than 1.2 V (step S21). If the voltage is equal to or lower than 1.2 V, the oscillation frequency range of the VCO 3 is switched to a lower adjacent band, and if the lowest band, the switching is not performed (step S22). If it is within the range of 1.2 to 3.5 V, the process proceeds to step S23 without performing band switching.

After the band switching, in step S23, the parameters of the number of horizontal dots, the number of vertical lines, clock, A / D conversion clock phase, horizontal position, and vertical position are set from the control panel, and the CPU 5 reads them inside. . Next, these parameters are written in the user setting parameter memory 9, and an input image signal number corresponding to the write address is set (step S2).
4) Then, the process proceeds to step S25.

In step S25, it is determined whether the mode of the input image signal determined this time is the same as or different from the mode of the input image signal determined last time. If the mode is the same as the previous mode, the mode set last time is continued, so the current process is not necessary, and the process proceeds to other processes. If the mode is different from the previous mode, the display on the LCD is stopped (step S26), the number of the input image signal including the user-set image signal number is set (step S27), and according to the determined image signal number, The mode LED blinks, turns on or off (step S28).

Next, a parameter address corresponding to the set image signal number is read (step S2).
9), using this address, the standard parameter memory 8
Then, the parameters are read from the user setting parameter memory 9 and stored in the internal RAM of the CPU 5 (step S30). Next, parameters are set from the internal RAM of the CPU 5 to each part of the memory control circuit 4 (step S31), and the LCD is set according to the set parameters.
13 is started (step S32).

[0044]

As described above, according to the present invention, the user-set parameter input means and the user-set parameter storage means temporarily set the user-set parameter storage means even when an image signal not set in the standard parameter storage means is input. The next time, a multi-scan display device that can automatically search for parameters, use parameters that match the input video signal, and display non-standard image signals in an appropriate display mode There is an effect that it can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a multi-scan display device according to the present invention.

FIG. 2 shows a voltage controlled oscillator (VCO) used in the embodiment.
Dot clock-PLL for explaining band switching of
It is a graph which shows voltage correspondence.

FIG. 3 is a first half of a flowchart for explaining the operation of the embodiment.

FIG. 4 is a second half of a flowchart for explaining the operation of the embodiment.

FIG. 5 is a block diagram illustrating a configuration example of a conventional multi-scan display device.

FIG. 6 is a first half of a flowchart for explaining the operation of the conventional example.

FIG. 7 is a latter half of a flowchart for explaining the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Low pass filter (LPF) 3 Voltage controlled oscillator (VCO) 4 Memory control circuit 41 Selector 42 Synchronous signal control circuit 43 Clock control circuit 44 Programmable 1 / N frequency dividing circuit 45 Field memory write control circuit 46 Field memory read Control circuit 47 Liquid crystal display timing generation circuit 5 CPU 6 Analog / digital converter (ADC) 7 Control panel 8 Standard parameter memory 9 User setting parameter memory 10 Reference clock generator 11 Field memory 12 Liquid crystal interface 13 Liquid crystal panel 14 Image signal input terminal 15 analog / digital changeover switch 16 amplifier 17 analog / digital converter (ADC)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G09G 5/12 H04N 3/14 H04N 3/14 5/05 5/05 5/46 5/46 G09G 5/00 520T (56) References JP-A-5-35240 (JP, A) JP-A-4-349491 (JP, A) JP-A-2-181784 (JP, A) JP-A-6-161369 (JP, A) Jpn. Microfilm (JP, U) photographing the contents of the specification and drawings attached to the application form No. 66251 (Japanese Utility Model Application No. Hei 4-24793) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/18 G09G 1/16 G09G 3/20 G09G 3/36 G09G 5/00 G09G 5/12 H04N 3/14 H04N 5/05 H04N 5/46

Claims (3)

(57) [Claims] 1. A multi-scan display device capable of displaying on a screen any one of a plurality of image signals in which one or both of a scanning method and a signal transmission method are different from each other. Parameter storage means for storing a plurality of sets of standard parameters for displaying on a screen, parameter input means for a user to input user setting parameters, and at least one storage location for storing the user setting parameters. A non-volatile user setting parameter storage unit, a search unit for searching for a parameter matching the input image signal from the standard parameter storage unit and the user setting parameter storage unit, and an image signal based on the searched parameter. Control hand to control the display of When, wherein the user configuration parameters, the number of horizontal pixels, the vertical pixels
Number, dot clock frequency, analog / digital conversion
The sampling clock phase, horizontal position and vertical position
Multiscan display device which comprises respectively. 2. The voltage control according to claim 1, wherein the voltage control has a plurality of bands and generates a dot clock.
Oscillator and dot clock divider for dividing the dot clock
And the phase of the divided dot clock and the horizontal synchronization signal.
A phase comparator to be compared, and the voltage control by passing a low-frequency signal output from the phase comparator.
A low-pass filter for controlling the oscillator, and an analog for converting the control voltage from analog to digital
/ Digital converter and dot clock controlled by the parameter input means
When the frequency is at the end of the band, the control voltage
Based on the digital conversion value of
A multi-scan display device , further comprising: band switching means for switching to a band . 3. The method according to claim 1, wherein
A multi-scan display device characterized in that the screen is a liquid crystal panel .