JP3117676B2 - Inspection design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (LS)
The present invention relates to a design for facilitating the inspection of I), and particularly relates to a register transfer level (RTL).
vel) for the RTL circuit, which is an integrated circuit
It belongs to the technology of designing for easy inspection .

[0002]

2. Description of the Related Art A scan design method is a typical example of a conventional design method for testability. The scan design method is to replace a flip-flop (FF) in a logic-designed integrated circuit with a scan FF that can be directly controlled (scan-in) and observed (scan-out) from the outside, thereby generating a test input generation problem for a sequential circuit. Is simplified to a combinational circuit problem, thereby facilitating generation of a test sequence (1990, published by Computer Science Press, "Digita
l Systems Tesing and Testable DESIGN, ”Chapter 9, Design For Testability).

Conventional scan design methods include a full scan design method in which all FFs are replaced by scan FFs, and a method in which observation and control are difficult to solve problems such as large area overhead in the full scan design method. There is a partial scan design method that replaces only a scan FF, and is mainly performed at the gate level.

[0004]

However, according to the conventional gate-level partial scan design method, the operation timing of the gate-level circuit generated by logic synthesis is affected by the scan design, and normal operation is guaranteed. There was a case that was not. For this reason, there is a problem in that rework of the design occurs and the design period is lengthened.

Therefore, recently, there has been proposed a method of performing a partial scan design at a register transfer level (RTL) having a higher degree of abstraction than a gate level.

For example, an integrated circuit (R) designed by RTL
For the TL circuit, a method has been proposed in which a register to be scanned is determined using a testability scale or the like within a specified range of the scan ratio (1995).
Year, ASPDAC (Asia and South Pasific Design Au
tomation Conference), pp209-216, "Design For T
estability Using register Transfer Level Partial S
can Selection ").

However, according to the partial scan design method in the RTL, it is difficult to guarantee a high failure detection rate in the RTL. That is, in the partial scan design method in the RTL, a stance of increasing a failure detection rate as much as possible within a range of a specified scan ratio is taken. Therefore, determination of a register to be scanned, logic synthesis, scan path insertion, and inspection are performed. A series of steps of sequence generation must be repeatedly performed until a high fault coverage is obtained. For this reason, there is a problem that it takes a long time for the scan design as a whole, and as a result, the test design cost increases.

[0008] In view of the above problems, the present invention provides a design change in an RTL so that an integrated circuit can be easily inspected, and
An object of the present invention is to provide a testability design method that can guarantee a high failure detection rate in RTL.

[0009]

[0010]

[0011]

Means for Solving the Problems To solve the above problems, a solution taken by the invention of claim 1 is a register transfer level (RTL, Register Transfer Level).
) For the RTL circuit, which is an integrated circuit designed in
As an inspection facilitating design method for making a design change so that inspection after manufacturing is facilitated, a first step of designating a circuit structure which is easy to inspect and a structure of the RTL circuit at the time of inspection are performed by using a register for scanning. When the normal data input is regarded as a pseudo external output and the data output is regarded as a pseudo external input, scanning is performed from among the registers in the RTL circuit so that the circuit structure specified in the first step is easy to inspect. A second step of deciding a register to be inspected, and the circuit structure specified in the first step, which is easy to inspect, comprises an external input or a pseudo external input and an external input.
For any pair with the output or pseudo external output, this pair
External input or pseudo external input and external output or pseudo
The number of registers in each path to the similar external output is n
As shown below, n is a natural number , and has an n-fold acyclic structure.

According to the first aspect of the present invention, the register to be scanned is determined so that the structure of the RTL circuit at the time of inspection is an n-fold acyclic structure designated as a circuit structure which is easy to inspect in the first step. Therefore, a high failure detection rate can be guaranteed in the upstream design stage.
Further, since the design for testability is performed in the RTL, the rework of the design is greatly reduced, and the design period of the LSI can be shortened as compared with the related art.

Further, a solution taken by the invention of claim 2 is a register transfer level (RTL, Register T
A first step of designating a circuit structure that is easy to inspect as an inspection-easy design method for making a design change so that an inspection after manufacturing is easy for an RTL circuit that is an integrated circuit designed at ransfer level). And the RTL at the time of inspection
When the circuit structure is such that the normal data input of the register to be scanned is regarded as a pseudo external output and the data output is regarded as a pseudo external input, the circuit structure specified in the first step is easily inspectable, A second step of determining a register to be scanned from among the registers in the RTL circuit, wherein the easy-to-test circuit structure designated in the first step comprises an external input or a pseudo external input to an external output or a pseudo external input. In each path to the external output, the number of stages of the gates constituting the combination functional component is n or less (n is 0 or a natural number).

According to the second aspect of the present invention, the structure of the RTL circuit at the time of inspection is from an external input or a pseudo external input to an external output or a pseudo external output designated as a circuit structure which is easy to inspect in the first step. In each path, the number of stages of gates constituting the combinational functional component is n or less (n
(0 or a natural number), the register to be scanned is determined so that a high failure detection rate can be guaranteed in the upstream design stage. Also, RTL
In this case, the design for easy inspection is performed, so that the rework of the design is greatly reduced, and the design period of the LSI can be shortened as compared with the related art.

[0015]

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a flowchart showing a flow of processing in a testability design method according to a first embodiment of the present invention. In FIG. 1, S11 is a step as a first step of designating a circuit structure which is easy to inspect, and S12 is a register transfer level (RTL, Register Transfer Level).
RTL circuit as an integrated circuit designed by RTL
Generating a directed graph from the design data, S13
Is such that the circuit structure of the RTL circuit at the time of inspection is such that the normal data input of the register to be scanned is regarded as a pseudo external output and when the data output is regarded as a pseudo external input, the circuit structure specified in step S11 is used. This is a step as a second step of determining a register to be replaced with a scan register (register to be scanned) on the directed graph generated in step S12.

In step S11, a circuit structure that can be easily inspected includes an acyclic structure and an n-fold alignment structure (n is a natural number)
Alternatively, a structure having a combined inspection input generation complexity is specified.

The acyclic structure means a structure in which a circuit does not include a feedback loop. The n-fold alignment structure means that, for an arbitrary pair of a register and an external output or a pseudo external output in a circuit, the order depth of each path between the paired register and the external output or the pseudo external output is n ways. Refers to the following structure. A circuit having an n-fold alignment structure has such a property that when the time axis is expanded for an arbitrary external output or pseudo external output, the number of time frames in which each register exists is limited to n or less.
Further, the structure having the combinational test input generation complexity means a structure having such a complexity that the test sequence generation algorithm for the combinational circuit can be applied.

FIG. 2 is a diagram showing the classification of synchronous sequential circuits according to structure. As shown in FIG. 2, the acyclic structure includes an n-fold alignment structure, and the n-fold alignment structure includes a structure having a combinational test input generation complexity.

In the directed graph generated in step S12, functional components such as combination functional components and registers are represented by nodes, and data transfer between the nodes is represented by edges. For an RTL circuit including a finite state machine, a directed graph is generated after only the finite state machine is logically synthesized and the entire RTL circuit is expressed by connecting registers and combinational functional components. Or
The registers included in the finite state machine are assumed to be scanned, and a directed graph is generated by the registers and the combination functional components.

The design method for testability according to the present embodiment will be described with reference to FIGS.

FIG. 3 is a directed graph showing an example of the RTL circuit which is generated from the RTL design data in step S12 and which is targeted by the testability designing method according to the present embodiment. In FIG. 3, A to K are combination functional parts, reg.
1 to reg9 are registers, PI1 and PI2 are external inputs,
PO1 and PO2 indicate external outputs, respectively. FIG.
The directed graph as shown in (1) may be described as a diagram in an actual testability design, or may be described in a functional description language such as Verilog-HDL.

FIG. 4 is a diagram showing the result of determining the register to be scanned for the RTL circuit shown in FIG. 3 in step S13 when the acyclic structure is designated as the circuit structure which can be easily inspected in step S11. . As shown in FIG. 4, the original directed graph has a register reg.
1, reg2, reg6 and combination functional parts A, B,
F, a loop 1 and registers reg1, reg2,
There are three feedback loops: a loop 2 composed of reg8 and the combined functional components A, B, and H, and a loop 3 composed of the register reg4 and the combined functional component D. Loop 1 and Loop 2 are both registers reg1 and r
Since both of the registers reg2 and reg2 are replaced with scan registers, both loops 1 and 2 can be broken. Loop 3 is a register r
A break can be achieved by replacing eg4 with a scan register. For this reason, as shown in FIG. 4, the hatched registers reg2 and reg4 are determined as registers to be scanned.

FIG. 5 is a diagram showing a result of determining a register to be scanned for the RTL circuit shown in FIG. 3 in step S13 when a single alignment structure is designated as a circuit structure which can be easily inspected in step S11. It is.
The single alignment structure refers to a structure in which n = 1 in an n-fold alignment structure, that is, a structure in which the order depth of each path from a certain register to a certain external output or pseudo external output is one. In other words, in the single alignment structure, each register has a path to a certain external output or a pseudo external output that does not pass through itself, and the number of registers in each path is one.

As shown in FIG. 5, in the original directed graph, registers reg1, reg2, reg4, reg
6, reg8 has a path through itself to the external outputs PO1 and PO2 due to the presence of the feedback loop, and the register reg3 has two registers (two and one) in the path to the external output PO1. It is. Therefore, the original RTL circuit does not have a single alignment structure. Therefore, if the registers reg2 and reg4 are replaced with scan registers, there is no register having a path that passes through the registers. If the register reg3 is replaced with a scan register, each register has one register in the path to the external output or the pseudo external output. Becomes RTL
The circuit has a single alignment structure. Therefore, as shown in FIG. 5, hatched registers reg2, reg3,
reg4 is determined as a register to be scanned.

FIG. 6 shows a case where a structure (balanced structure) having a combined test input generation complexity is designated as a circuit structure which is easy to test in step S11, and the RTL circuit shown in FIG. 3 is scanned in step S13. FIG. 14 is a diagram illustrating a result of determining a register. In FIG. 6, the number of registers from the external input PI1 to the external output PO1 is not one, and the number of registers from the external input PI2 to the external output PO2 is not one. External input PI
The number of registers from 2 to the external output PO1 is not one. When the registers reg2, reg4, reg7 are replaced with scan registers, the circuit has a balanced structure. For this reason, as shown in FIG. 6, the hatched registers reg2, reg4, and reg7 are determined as registers to be scanned.

As described above, when the structure of the RTL circuit is such that the normal data input of the register to be scanned is regarded as a pseudo external output and the data output is regarded as a pseudo external input, the acyclic structure, the n-fold alignment structure, the combination Since the registers to be scanned are determined so as to have a circuit structure that can be easily inspected, such as a structure having inspection input generation complexity, a high fault detection rate can be guaranteed in the upstream design stage. In addition, at the time of logic synthesis, since the register to be scanned is already determined, the operation timing of the gate-level circuit generated by the logic synthesis is not affected by the subsequent scan design, so that the design rework is performed. Is greatly reduced.

(Second Embodiment) FIG. 7 is a flowchart showing a flow of processing in a testability design method according to a second embodiment of the present invention. The design method for testability according to the present embodiment shown in FIG.
In the method for designing for testability according to the first embodiment shown in FIG. 1, a step S14 as a third step of additionally determining a register to be scanned is added.

In step S14, when the normal data input of the register to be scanned is regarded as a pseudo external output and the data output is regarded as a pseudo external input to the RTL circuit having determined the register to be scanned in step S13,
This is processing for additionally determining registers to be scanned so that the number of registers is the same for each path from one pseudo external input to an external output or pseudo external output.

FIG. 8 is a directed graph generated from the RTL design data in step S12 and representing an example of the RTL circuit targeted by the testability design method according to the present embodiment. In FIG. 8, A to D are combination functional parts, reg.
1 to reg4 are registers, PI1 and PI2 are external inputs,
PO1 indicates an external output. In FIG. 8, it is assumed that the acyclic structure is designated as the structure that can be easily inspected in step S11, and the register r is used in the original directed graph.
Since there is a loop composed of eg1, reg3 and the combination functional components B and C, to break this loop,
The hatched register reg1 is determined as a register to be scanned.

FIG. 9 is a diagram showing a result of converting the RTL circuit shown in FIG. 8 into a pseudo external output PPO1 and a normal data input of a register reg1 determined as a register to be scanned into a pseudo external output PPO1. . In FIG. 9, since the number of registers in each path from the pseudo external input PPI1 to the external input PO1 is two (one and two), in order to make this one, hatching is added in step S14. Register reg
4 is additionally determined as a register to be scanned.

As described above, when the normal data input of the register to be scanned is regarded as a pseudo external output, and the data output is regarded as a pseudo external input, each path from one pseudo external input to an external output or a pseudo external output is considered. By additionally determining the registers to be scanned so that the number of registers is the same, the shift operation can be limited in the scan test sequence for a certain failure, so that the test sequence can be shortened.

The first reference example of [0034] (First reference example) The present invention relates to test sequence generation method for generating a test sequence against RTL circuit. Ginseng
The test sequence generation method according to the example is directed to an RTL circuit in which a register to be scanned is determined by the testability design method according to the first or second embodiment. However, at the time of inspection, the RTL circuit which originally has an acyclic structure and the register to be scanned are determined. At the time of inspection, the normal data input of the register to be scanned is regarded as a pseudo external output, and the data output is regarded as pseudo external output. RT with a closed-circuit structure when regarded as pseudo external input
The L circuit can also be a target of the test sequence generation method according to the present reference example .

FIG. 10 is a flowchart showing the flow of processing in the test sequence generation method according to the first embodiment of the present invention. In FIG. 10, S20 performs time-base expansion on the target RTL circuit, generates a time-base expanded RTL circuit, and stores a time frame in which each external output and pseudo external output exist. In the step of logically synthesizing the RTL circuit to generate a gate-level circuit, in step S32, the time-base expansion of the gate-level circuit is performed from the time frame of each external output and the pseudo external output stored in step S20, and the time-axis expansion A step of generating a time axis expansion combination circuit as a gate level circuit as a test sequence generation circuit and storing a time frame in which each external input and a pseudo external input exist; and step S33 is a time axis expansion combination circuit generated in step S32. , Generate test input for combinational circuits targeting multiple stuck-at faults Step S34 is a step of converting the test input generated in Step S33 into a test sequence for a sequential circuit based on the information on the time frame in which the external input and the pseudo external input stored in Step S32 exist, and Step S35 This is a step of converting the test sequence converted in S34 into a scan test sequence in consideration of a scan shift operation. Steps S20, S31, S3
2 constitute a first step, and step S3
3 constitute a second step, and step S3
4, S35 constitutes a third step.

First, step S20 will be described with reference to FIGS.

[0037] FIG. 11 is a flowchart showing a detailed process flow of step S20 in test sequence generation method according to the present embodiment shown in FIG. 10. In FIG. 11, S2
1 is a step of obtaining the maximum value of the order depth up to the external input or the pseudo external input, that is, the maximum order depth, for each of the external output and the pseudo external output. S22 sorts the external output and the pseudo external output in descending order of the maximum order depth. Step S23 is a step of setting the number of time frames for time axis expansion. Steps S24 to S26 are for each external output and pseudo external output, in the order of the sorting results in step S22, based on a predetermined evaluation index, based on a predetermined evaluation index. This is the step to be performed.

FIG. 12 is a directed graph showing an example of an RTL circuit targeted by the test sequence generation method according to this embodiment . In FIG. 12, A to I are combination functional parts, reg.
1 to reg7 are registers, PI1 to PI3 are external inputs,
PPI1 is a pseudo external input, PO1 is an external output, PPO1
Indicates pseudo external outputs.

First, in step S21, the external output P
The maximum order depth is obtained for each of O1 and the pseudo external output PPO1. For the external output PO1, the order depth up to the external input PI1 is 2, the order depth up to the external input PI2 is 2, and the order depth up to the pseudo external input PPI1 is 3, so the maximum order depth is 3. Also, for the pseudo external output PPO1, the order depth to the external input PI1 is 3, the order depth to the external input PI2 is 3, and the order depth to the pseudo external input PPI1 is 4, so the maximum order depth is 4.

Next, at step S22, the external output P
O1 and the pseudo external output PPO1 are sorted in descending order of the maximum order depth. As a result of sorting, pseudo external output PPO
1, the external output PO1.

Next, in step S23, the number of time frames for time axis expansion is set. Since the number of time frames required for time axis expansion is given by adding 1 to the maximum value of the maximum order depth of each external output and pseudo external output, the maximum order of the pseudo external output PPO1 at the head of the sorted result A value obtained by adding 1 to the depth, that is, 5 is set as the number of time frames.

Hereinafter, in steps S24 to S26, R
The time axis expansion of the TL circuit is performed. The time axis expansion here is
This is performed for each external output or pseudo external output in the order sorted in step S22. That is, first, the pseudo external output PPO
1 is expanded on a time axis, and then the external output PO1 is expanded on a time axis. Further, in the time axis expansion, which time frame the external output or the pseudo external output is to be arranged is determined based on a predetermined evaluation index.

Here, it is assumed that the total sum of the number of combined functional components existing in each time frame is used as a predetermined evaluation index. Then, time axis expansion is performed so that this evaluation index becomes smaller. The scale of the test sequence generation circuit is almost proportional to the total number of combinational functional components present in each time frame, and the smaller the circuit size, the easier the test sequence generation is. By performing time-axis expansion using the sum of the numbers as the evaluation index, it is possible to more easily generate the test sequence.

FIG. 13 is a diagram showing the result of time base expansion of the pseudo external output PPO1. Pseudo external output P
Since the maximum order depth of PO1 is 4, the number of time frames required for this time axis expansion is 5, which is equal to the number of time frames set in step S23. For this reason, the position of the pseudo external output PPO1 is necessarily determined in the time frame 5.

Next, time axis expansion is performed on the external output PO1, and the maximum order depth of the external output PO1 is 3, so the number of time frames required for this time axis expansion is 4.
For this reason, the position of the external output PO1 is the time frame 4 or the time frame 5, and it is determined which of the time frame 4 and the time frame 5 the external output PO1 is to be arranged based on the evaluation index.

FIG. 14 is a diagram when the external output PO1 is arranged in the time frame 5. The number of combined functional components related to the time axis expansion for the pseudo external output PPO1 is 10
Since the number of combined functional components related to the time axis expansion for the external output PO1 is 7, if there is no overlap of the combined functional components in each time frame, it exists in each time frame as the predetermined evaluation index. The total number of combined functional components is 17. In FIG. 14,
Since the combined functional components F overlap in the time frame 2 and the combined functional components A overlap in the time frame 3, the number of overlapping combined functional components is two. Therefore,
The value of the predetermined evaluation index when the external output PO1 is arranged in the time frame 5 is the sum of the number of combined functional components existing in each time frame when there is no overlap.
7 is obtained by subtracting 2 which is the number of combined functional components from 15, and becomes 15.

FIG. 15 is a diagram when the external output PO1 is arranged in the time frame 4. In FIG. 15, the combined functional components F overlap in the time frame 1, the combined functional components A, F, and G overlap in the time frame 2, and the combined functional components B and H overlap in the time frame 3, so they overlap. The number of combination functional components is six. Therefore, the value of the predetermined evaluation index when the external output PO1 is arranged in the time frame 4 is calculated from 17 which is the sum of the number of the combined functional components existing in each time frame when there is no overlap, and 6 which is the number of parts
Is reduced to 11.

Therefore, the position of the external output PO1 is determined in the time frame 4. As a result, the result of the time base expansion of the RTL circuit shown in FIG.
It looks like 6. In step S20, the position of the pseudo external output PPO1 is the time frame 5, the external output PO1.
Is stored as time frame 4.

Next, in step S31, logic synthesis of the RTL circuit is performed to generate a gate-level circuit. FIG. 17 is a diagram showing a gate-level circuit generated by performing logic synthesis on the RTL circuit shown in FIG.

Next, in step S32, step S
20. The time base expanded RTL circuit obtained in step 20 and step S31
A gate-level circuit (time-axis expanded combination circuit) expanded on a time axis for generating a test sequence is generated from the gate-level circuit generated in step (1). Specifically, the target RTL
Each external output and the pseudo external output of the circuit are
Are arranged in the time frames stored in step S31, and based on the gate-level circuit information generated in step S31,
A time axis expansion combination circuit is generated by time axis expansion at the gate level from the arranged external outputs and pseudo external outputs. FIG. 18 is a time axis expansion RTL shown in FIG.
Based on the circuit and the gate level circuit shown in FIG.
It is a figure showing the time axis expansion combination circuit generated in step S32.

Next, in step S33, step S
A test input for multiple combinational circuits is generated with respect to the time-axis expanded combinational circuit generated in step S32. For example, the following test input for fault detection is generated for the time base expansion combination circuit of FIG. PI1 (2) = 0, PI1
(3) = 1, PI2 (2) = 0, PI3 (4) = 1 PPI1 (1) = 0, PPI1 (2) = 1 Here, the numbers in parentheses are time frame numbers.
For example, “PPI1 (1) = 0” indicates that the test input for the pseudo external input PPI1 in the time frame 1 is “0”.

Next, in step S34, step S
The test input generated in step 33 is converted into a test sequence for a sequential circuit in accordance with the time frame position of each external input and pseudo external input. The test input for the time base expansion combination circuit of FIG. 18 is converted into the following test sequence. Here, X represents don't care. PI1 = X01XX, PI2 = X0XXX, PI3 = XXX1X PPI1 = 01XXX

Further, in step S35, the test sequence for the pseudo external input is converted into a scan test sequence in consideration of the scan path shift operation. The time axis expansion combination circuit shown in FIG.
The test sequence for 1 is converted into a scan test sequence.

As described above, using the sum of the number of combined functional components present in each time frame as an evaluation index, the time axis is expanded in the RTL so that the evaluation index becomes smaller. Is generated, the size of the combinational circuit for generating the test input becomes smaller, so that the test sequence generation becomes easier.

Although the sum of the number of combined functional components present in each time frame is used as an evaluation index here, a value obtained by weighting each combined functional component according to its type and adding them together is used as an evaluation index. May be used. Alternatively, the number of gates may be estimated for each combinational functional component in advance, and the total number of estimated gates of the combinational functional components existing in each time frame may be used as an evaluation index.

Also, in the RTL time axis expansion of step S20, when determining the time frame position of one external output or pseudo external output, the determined time frame position of the external output or pseudo external output is not changed and the evaluation index is determined. The time frame position may be determined so as to be optimal, or the time frame position may be determined so that the evaluation index is optimal, including the change of the time frame position of the already determined external output or pseudo external output. It doesn't matter.

The evaluation index used for the time axis expansion in the RTL is not limited to the total sum of the numbers of the combined functional components existing in each time frame described above.

Here, as an example of another evaluation index, the number of time frames in which a pseudo external input or a pseudo external output exists is used. Since the number of time frames in which the pseudo external input or the pseudo external output exists is equivalent to the number of shift operations required for a test sequence for detecting a certain failure, the smaller the value of this evaluation index, the less the number of shift operations As a result, the length of the test sequence is shortened. Therefore, the test sequence can be shortened by expanding the time axis so that the value of the evaluation index becomes smaller.

FIGS. 19 and 20 are diagrams showing the result of time-base expansion of the RTL circuit of FIG.
9 is a diagram when the external output PO1 is arranged in the time frame 5, and FIG. 20 is a diagram when the external output PO1 is arranged in the time frame 4. As shown in FIG. 19, when the external output PO1 is arranged in the time frame 5, there are four time frames in which the pseudo external input PPI1 or the pseudo external output PPO1 exists (time frames 1, 2, 3, 5).
Therefore, the value of the evaluation index is 4. On the other hand, as shown in FIG. 20, when the external output PO1 is arranged in the time frame 4, the pseudo external input PPI1 or the pseudo external output PP
Since there are three time frames in which O1 exists (time frames 1, 2, 5), the value of the evaluation index is 3.

Therefore, the position of the external output PO1 is determined in the time frame 4 in which the value of the evaluation index becomes smaller. Also in this case, the result of the time base expansion of the RTL circuit shown in FIG. 12 is as shown in FIG.

As described above, RT based on a predetermined evaluation index
By generating the time series expansion combination circuit for generating the test sequence by expanding the L circuit on the time axis, the generation of the test sequence can be facilitated or the test sequence can be shortened.

[0062] The second reference example (second reference example) The present invention, like the first reference example, at the time of inspection and RTL circuit is acyclic structure, a register for scan design has been determined And a test sequence for generating a test sequence for an RTL circuit having a non-closed structure when a normal data input of a register to be scanned is regarded as a pseudo external output and a data output is regarded as a pseudo external input at the time of inspection. It relates to a generation method.

FIG. 21 is a flowchart showing the flow of processing in the test sequence generation method according to the second embodiment of the present invention. As shown in FIG. 21, the test sequence generation method according to the present reference example has the same steps S33 to S35 as the test sequence generation method according to the first reference example shown in FIG.

S40 is for the target RTL circuit.
Step S41 is a pre-processing step of grouping combination functional components to which no register, external input and external output belong in a path connecting each other, and S41 is to combine the combination functional components grouped in step S40 as one combination functional component. Performing a time-base expansion on the RTL circuit to generate a time-base expanded RTL circuit; and S42, performing logic synthesis in units of the combinational functional components grouped in step S40 to generate a gate-level circuit. S43 is the time base expansion RT generated in step S41.
In this step, a time axis expansion combination circuit for generating a test sequence is generated from the L circuit and the gate-level circuit for each group generated in step S42, and a time frame in which each external input and a pseudo external input exist is stored. . The first step is constituted by steps S40, S41, S42 and S43.

FIG. 22 is a directed graph showing an example of an RTL circuit targeted by the test sequence generation method according to this embodiment . In FIG. 22, AI is a combination functional component, reg
1 to reg6 are registers, PI1 is an external input, PPI1
Indicates a pseudo external input, PO1 indicates an external output, and PPO1 indicates a pseudo external output.

First, in step S40, the combination functional components A to I are grouped. In FIG. 22, the group P1 is formed by the combination functional components A and B, the group P2 is formed by the combination functional components C, D, E, and F, and the groups P3, P4, and P are formed by the combination functional components H, G, and I, respectively.
5 has been generated. FIG. 23 is a diagram showing a result of grouping the combination functional components in step S40.

Next, in step S41, time base expansion is performed on the RTL circuit shown in FIG. 23 in the same manner as in step S20 in the third embodiment. FIG. 24 is a diagram showing a time-base expanded RTL circuit obtained as a result of the time-base expansion in step S41.

Next, in step S42, step S
Each group P1 to P as a result of grouping in 40
5 and the groups P1 to P
5 is generated. Then, in step S43, step S shown in FIG.
Each group P1 of the time base expanded RTL circuit generated in 41
By assigning the gate-level combination circuit generated in step S42 to P5, a time-axis expansion combination circuit as shown in FIG. 25 is generated as a test sequence generation circuit. Subsequent processing is the same as in the first reference example .

A third reference example of [0069] (Third Example) The present invention, like the first and second reference example, and RTL circuit is acyclic structure at the time of inspection,
A register to be scanned is determined, and at the time of inspection, a normal data input of the register to be scanned is regarded as a pseudo external output, and an RTL circuit having a non-closed structure when the data output is regarded as a pseudo external input. And a test sequence generation method for generating a test sequence.

FIG. 26 is a flowchart showing the flow of processing in the test sequence generation method according to the third embodiment of the present invention. As shown in FIG. 26, the test sequence generation method according to this reference example has the same steps S33 to S35 as the test sequence generation methods according to the first and second reference examples .

S51 is a step of logically synthesizing the target RTL circuit to generate a gate-level circuit. S52 is a time-base expansion for the gate-level circuit generated in step S51, and a time axis for test sequence generation. Generating an expansion combinational circuit and storing a time frame in which each external input and the pseudo external input exist; Step S
The first step is constituted by 51 and S52.

The time axis expansion of the gate level in step S52 is the same as that of R in step S20 of the first reference example.
As in the case of the TL time axis expansion, it is performed based on a predetermined evaluation index.

For example, using the sum of the number of gates present in each time frame as an evaluation index, performing time axis expansion at the gate level so that the evaluation index becomes smaller, and generating a time axis expansion combination circuit. As a result, the combinational circuit for generating the test input becomes smaller, thereby facilitating the generation of the test sequence. In addition, by using the number of time frames in which a pseudo external input or a pseudo external output exists as an evaluation index, it is possible to shorten a test sequence.

[0074] A fourth reference example (fourth reference example) The present invention, like the first and second reference example, and RTL circuit is acyclic structure at the time of inspection,
A register to be scanned is determined, and at the time of inspection, a normal data input of the register to be scanned is regarded as a pseudo external output, and an RTL circuit having a non-closed structure when the data output is regarded as a pseudo external input. The present invention relates to a test sequence generation method for generating a test sequence, and performs time axis expansion based on an evaluation index different from that shown in the first reference example .

In this embodiment , for each pseudo external output,
An evaluation index that minimizes the number of existing time frames is used. Specifically, the sum of the sum of the number of time frames in which each pseudo external input exists and the sum of the number of time frames in which each pseudo external output exists is used as an evaluation index. However, when there is a register to which the corresponding pseudo external input belongs in the time frame following the time frame to which the corresponding pseudo external output belongs, the number of the registers is subtracted from the evaluation index. At this time, regarding the last time frame, the next time frame means the first time frame.

Further, a scan FF constituting a register corresponding to a pseudo external output existing in one time frame,
And one scan path is configured by a scan FF configuring a register corresponding to a pseudo external input existing in a time frame next to the one time frame,
By converting the test input into a test sequence, the length of the test sequence can be reduced.

FIG. 27 is a directed graph showing an example of the RTL circuit targeted by the test sequence generation method according to the present embodiment . In FIG. 27, A to G are combination functional components, reg.
1 to reg5 are registers, PI1 and PI2 are external inputs,
PO1 and PO2 indicate external outputs, respectively. FIG.
Since the RTL circuit shown in FIG. 7 has two feedback loops, the registers reg4 and r4 are used to break the two feedback loops so as to form an acyclic structure.
eg5 is determined as a register to be scanned.

FIG. 28 is a diagram showing a result of replacing the register to be scanned with a pseudo external input and a pseudo external output in the RTL circuit shown in FIG. In FIG. 28,
The register reg4 is replaced with a pseudo external input PPIr4 and a pseudo external output PPOr4.
5 is a pseudo external input PPIr5 and a pseudo external output PPO
has been replaced by r5.

FIG. 29 is a diagram showing the time axis expansion according to the present embodiment for the RTL circuit shown in FIG. Since the order depth of the RTL circuit shown in FIG. 28 (that is, the maximum value of the maximum order depth of each external output and pseudo external output) is 3,
As shown in FIG. 29, the number of time frames at the time of expanding the time axis is set to four. Then, first, the pseudo external output PPOr4 having the maximum maximum order depth is expanded on the time axis.

Next, time axis expansion is performed for the pseudo external output PPOr5 having the maximum order depth of 1.

When the pseudo external output PPOr5 is arranged in the time frame 4 ((i) in FIG. 29), for the pseudo external input, PPIr4 exists in the time frames 1 and 3, and PPIr5 exists in the time frame 4. For the pseudo external output, both PPOr4 and PPOr5 exist in the time frame 4, and for the register reg4, the pseudo external output PPOr4 exists in the time frame 4, and the pseudo external input PPIr4 exists in the time frame 1. Therefore, the value of the evaluation index is 4 (= 3 + 2-1).

When the pseudo external output PPOr5 is arranged in the time frame 3 ((ii) in FIG. 29), for the pseudo external input, PPIr4 exists in the time frames 1 and 2, and PPIr5 exists in the time frame 3.
For pseudo external output, PPOr4 is time frame 4
And PPOr5 is present in time frame 3, and for register reg4, a pseudo external output PP
Or4 is a pseudo external input PPIr4 in time frame 4.
Is present in time frame 1, the value of the evaluation index is 4
(= 3 + 2-1).

When the pseudo external output PPOr5 is arranged in the time frame 2 ((iii) in FIG. 29), for the pseudo external input, PPIr4 exists in the time frame 1 and PPIr5 exists in the time frame 2, and the pseudo external output As for the output, PPOr4 is present in time frame 4 and PPOr5 is present in time frame 2, and the pseudo external output PPO
Since r4 is in time frame 4 and pseudo external input PPI r4 is in time frame 1, the value of the evaluation index is 3
(= 2 + 2-1).

Therefore, the arrangement position of the pseudo external output PPOr5 is determined in the time frame 2 in which the value of the evaluation index becomes minimum. Similarly, the arrangement position of the external output PO1 is determined on the time frame 1, and the arrangement position of the external output PO2 is determined on the time frame 3.

As a result, a time base expanded RTL circuit as shown in FIG. 30 is generated. In FIG. 30, each pseudo external input and pseudo external output are PP
Only Ir4 has PPIr5 and PP in time frame 2.
Only Or5, only PPIr5 exists in time frame 3, and only PPOr4 exists in time frame 4.

In the time series expansion combination circuit for generating a test sequence generated based on the time axis expansion RTL circuit shown in FIG. 30, one scan path is formed by the register reg4, and another scan path is formed by the register reg5. Shall be.

For example, assume that register reg4 has a data width of 8 bits and register reg5 has a data width of 4 bits.
In this case, the FFs forming the registers reg4 and reg5
Is 12.

Here, assuming that two scan paths consisting of six scan FFs are simply configured, and that each scan path includes the scan FFs of the registers reg4 and reg5, the time frames 1, 2 , 3 require a shift operation, the length of the test sequence for shift required for one test input is 18 (=
6.3).

On the other hand, one scan path is formed by the eight scan FFs constituting the register reg4,
When another scan path is configured by the four scan FFs forming the eg5, the length of the test sequence for the shift required for one test input is 16 (= 8 + 4 ·
2).

As described above, for each pseudo external output, the test sequence can be shortened by performing the time axis expansion using the evaluation index that minimizes the number of existing time frames.

[0091] The fifth reference example (fifth reference example) The present invention, like the first and second reference example, and RTL circuit is acyclic structure at the time of inspection,
A register to be scanned is determined, and at the time of inspection, a normal data input of the register to be scanned is regarded as a pseudo external output, and an RTL circuit having a non-closed structure when the data output is regarded as a pseudo external input. The present invention relates to a test sequence generation method for generating a test sequence, and performs time axis expansion based on an evaluation index different from that shown in the first reference example.

In this embodiment , the total number of external inputs existing in each time frame is used as an evaluation index. Then, the time axis is expanded so that the value of the evaluation index becomes maximum.

FIG. 31 is a directed graph showing an example of an RTL circuit having an acyclic structure, which is a target of the test sequence generation method according to the present embodiment . In FIG. 31, AF is a combination functional component, reg1 to reg4 are registers, PI1, P
I2 indicates an external input, and PO1 and PO2 indicate external outputs.

FIG. 32 is a diagram showing the time axis expansion according to the present embodiment for the RTL circuit shown in FIG. Since the order depth of the RTL circuit shown in FIG. 31 (that is, the maximum value of the maximum order depth of each external output and pseudo external output) is 3,
As shown in FIG. 32, the number of time frames at the time of expanding the time axis is set to four. Then, first, the time axis is developed for the external output PO1 having the maximum maximum order depth.

Next, time axis expansion is performed on the external output PO2. When the external output PO2 is arranged in the time frame 4 ((i) in FIG. 32), the external input PI1 exists in the time frame 1, the external input PI1 exists in the time frame 2, and the external inputs PI1 and PI2 exist in the time frame 3. Therefore, the value of the evaluation index is 4 (= 1 + 1 + 2). on the other hand,
When the external output PO2 is arranged in the time frame 3 ((ii) in FIG. 32), the external input PI
1 indicates that the external inputs PI1 and PI2 exist in the time frame 2, so that the value of the evaluation index is 3 (= 1 + 2). Therefore, the arrangement position of the external output PO2 is determined in the time frame 4 in which the value of the evaluation index becomes maximum.

[0096] Figure 33 is a diagram showing a time axis expansion RTL circuit generated by the time base expansion of the present embodiment for RTL circuit shown in FIG. 31. In the figure, (a) is a diagram when the external output PO2 is arranged in the time frame 4,
(B) is a diagram when the external output PO2 is arranged in the time frame 3.

FIG. 34 shows the result of converting the time base expanded RTL circuit shown in FIG. 33 to a gate level. 33A shows the conversion result of FIG. 33A in which the external output PO2 is arranged in the time frame 4, and FIG. 33B shows the conversion result of FIG. 33B in which the external output PO2 is arranged in the time frame 3. It is a figure showing a conversion result. In FIG. 34, the combination functional component A is connected to one NOT gate ga and the combination functional component B
Is a single NOT gate gb, a combined functional component C is a single NAND gate gc, and a combined functional component D is a single N
The OT gate gd, the combined functional component E is one NOR gate ge, and the combined functional component F is one AND gate g
f.

In the circuit of FIG. 34A, the test inputs for detecting the stuck-at-0 fault (s · a-0) in the output of the NAND gate gc are: PI1 (0) = 0, PI1 (1) = 1 , PI1 (2) =
0, PI2 (2) = 1, and the stuck-at fault in the output of the NOR gate ge can be detected together with this test input. on the other hand,
In the circuit of FIG. 34B, the test inputs for detecting the stuck-at-0 fault at the output of the NAND gate gc are: PI1 (0) = 0, PI1 (1) = 1, PI2 (1) =
It becomes 1. According to this test input, one input of the AND gate gf is always "0" because PI1 (1) = 1, and the output of the AND gate gf is always "0". A stuck-at-1 fault in the output cannot be detected.

As described above, when the number of external inputs present in each time frame is large, the number of faults that can be detected by one test input increases, and the required test sequence length is shortened. Therefore, by performing the time axis expansion based on the evaluation index as shown in the present reference example , the length of the test sequence can be shortened.

The evaluation indices shown in the fourth and fifth reference examples can be used even when the time axis is developed at the gate level as in the third reference example .

( Third Embodiment ) The third embodiment of the present invention relates to a design method for testability similar to the first embodiment. The RTL circuit is divided into a plurality of blocks, The register to be scanned is determined for each block so as to have a circuit structure that can be easily inspected.

FIG. 35 shows an RT divided into a plurality of blocks.
It is a figure which shows an L circuit typically. The RTL circuit shown in FIG. 35 is divided into three blocks A, B, and C. However, since the blocks A, B, and C form a feedback loop, the inspection of the RTL circuit as a whole does not become easy if the blocks A, B, and C have a circuit structure that is easy to inspect. Test sequence generation is LSI
Since the inspection is performed for the entire LSI, a high failure detection rate cannot be obtained unless the entire LSI is easily inspected.

Therefore, in each block, the register that reaches the input side from the output of the block and reaches through only the combination functional component is determined as the register to be scanned. Then, a register to be scanned is determined so that each block has a circuit structure that can be easily inspected.

FIG. 36 is a directed graph showing the configuration of each block of the RTL circuit shown in FIG. In the figure, (a) shows block A, (b) shows block B, and (c) shows block C, respectively. 36, a to n are combinational functional components, reg0 to reg11 are registers, and I
1 to I7 are block inputs, and O1 to O7 are block outputs.

First, in each of the blocks A, B, and C, a register that reaches from the output of the block to the input side and reaches through only the combination functional component is determined as a register to be scanned. For block A, FIG.
As shown in the figure, the register re arrives directly from the output O1.
The register reg2 arriving from the g3 and the output O2 through the combination functional component c is shown in FIG.
6 (b), the register reg6 directly reaching from the output O3, the register re reaching directly from the output O4
g7 and register reg8, which arrives directly from output O5
For the block C, as shown in FIG. 36 (c), the register reg1 that directly arrives from the outputs O6 and O7.
1 is first determined as a register to be scanned.

Thereafter, registers to be scanned are determined so that each of the blocks A, B, and C has a circuit structure that can be easily inspected. Here, as a circuit structure that is easy to inspect,
An acyclic structure shall be specified. In this case, the registers reg0, r that have not yet been broken in block A
Since there is a loop including eg1 and the combined functional components a, b, and d, the register reg0 is determined as a register to be scanned in order to break this loop.

As a result, hatched registers reg0, reg2, reg3, reg6, r6 in FIG.
eg7, reg8, reg11 are determined as registers to be scanned. As a result, the entire RTL circuit is easily inspected, and a high failure detection rate can be guaranteed.

( Fourth Embodiment ) The fourth embodiment of the present invention relates to a design method for facilitating inspection similar to that of the first embodiment. This specifies a circuit structure different from that of the embodiment.

In the present embodiment, a circuit structure whose multiplicity becomes n (n is a natural number) when the time axis is expanded is designated as a circuit structure that is easy to inspect. Specifically, when the normal data input of the register to be scanned is regarded as a pseudo external output and the data output is regarded as a pseudo external input,
External input or pseudo external input and external output or pseudo external
For any pair with the output, this pair of external input or
Designates a structure in which the number of registers not to be scanned in each path between a pseudo external input and an external output or a pseudo external output is n or less as a circuit structure that can be easily inspected. The above-mentioned circuit structure is referred to as “n-fold acyclic circuit structure” in this specification. When n is 1, the n-fold acyclic structure has the same meaning as the equilibrium structure.

FIG. 37 is a directed graph showing an example of an RTL circuit targeted by the testability designing method according to the present embodiment. In FIG. 37, A to K are combination functional parts, re
g1 to reg8 indicate registers, PI1 and PI2 indicate external inputs, and PO1 and PO2 indicate external outputs.

For the RTL circuit shown in FIG. 37, it is assumed that the double acyclic structure is designated as a circuit structure which can be easily inspected to facilitate the inspection. As shown in FIG. 37, the original directed graph includes a loop composed of registers reg1, reg5 and combination functional components A, B, F, and a register reg.
1, reg7 and a loop composed of the combined functional components A, B, and H, and a loop composed of the register reg3 and the combined functional component D, there are three feedback loops.
eg1 and reg3 are determined as registers to be scanned.

At this time, from the external input PI1 to the external output P
Up to O1, one non-scanned register r
Path where eg5 exists, 2 non-scanning resists
This RTL circuit has a triple acyclic structure because there are a path in which the registers reg2 and reg4 exist and a path in which three registers reg2, reg6 and reg8 not to be scanned exist. In order to make the RTL circuit have a double acyclic structure, the register reg6 is determined as a register to be scanned.

As a result of the above processing, the RTL shown in FIG.
The circuit is easily inspected as shown in FIG. RT in FIG. 38
The L circuit includes hatched registers reg1, reg.
3 and reg6 are determined as registers to be scanned, thereby forming a double acyclic structure. When the RTL circuit in FIG. 38 is expanded on the time axis, the multiplicity becomes two. Therefore, it is sufficient to consider a double fault when generating a multiple fault test input. In this way, by specifying the n-fold acyclic structure as a circuit structure that is easy to test, the multiplicity to be taken into account when generating multiple failure test inputs is limited to n, so that the generation of a test sequence can be easily performed. Become.

( Fifth Embodiment ) The fifth embodiment of the present invention relates to a design method for facilitating inspection similar to that of the first embodiment. This specifies a circuit structure different from that of the embodiment.

In the present embodiment, when the normal data input of the register to be scanned is regarded as a pseudo external output, and the data output is regarded as a pseudo external input, when the data from the external input or the pseudo external input to the external output or the pseudo external output is considered. In each path, a structure in which the number of gate stages is n or less (n is 0 or a natural number) is designated as a circuit structure that is easy to inspect. As a premise, the number of gate stages needs to be estimated for each combinational functional component of the RTL circuit.

FIG. 39 is a directed graph showing an example of the RTL circuit targeted by the testability designing method according to the present embodiment. In FIG. 39, A to K are combination functional parts, re
g1 to reg9 indicate registers, PI1 and PI2 indicate external inputs, and PO1 and PO2 indicate external outputs.
As shown in FIG. 39, the number of gate stages is estimated for each of the combination functional components A to K. For example, for the combination functional component A, the number of gate stages is estimated to be 2 or 1 for each of the two paths.

In the RTL circuit shown in FIG. 39, a structure in which the number of gate stages is 5 or less in each path from an external input or pseudo external input to an external output or pseudo external output is designated as a circuit structure that is easy to inspect. To facilitate inspection.

First, in order to break the loop consisting of the register reg4 and the combination functional component D, the register r
eg4 is determined as a register to be scanned.

Next, the registers reg1, reg2, re
In order to break the loop consisting of g6 and the combined functional parts A, B, F, registers reg1, reg2, r
One of eg6 is determined as a register to be scanned.

Assuming that the register reg1 is determined to be a register to be scanned, the path in which the maximum number of gate stages exceeds 5 is from the register reg1 to the external output PO1 (the number of gate stages 7), from the register reg1 to the register reg1.
g1 (7 gate stages), register reg1 to external output PO2 (8 gate stages), external input PI1 to external output PO1 (6 gate stages), external input PI1
To the external output PO2 (the number of gate stages is 7).

Assuming that the register reg2 is determined to be a register to be scanned, a path in which the maximum number of gate stages exceeds 5 is from the register reg2 to the register reg2 (the number of gate stages is 7), the external input PI1 to the external output PO1.
Up to (the number of gate stages) and from the register reg4 to the register reg2 (the number of gate stages).

Assuming that the register reg6 is determined to be a register to be scanned, the path where the maximum number of gate stages exceeds 5 is from the register reg6 to the register reg6 (the number of gate stages 7), from the external input PI1 to the external output PO1.
(The number of gate stages is 6), from the external input PI1 to the external output P
O2 (7 gate stages), from register reg4 to external output PO1 (10 gate stages), register reg4
To the external output PO2 (the number of gate stages is infinite).

Therefore, the register reg2 in which the number of paths in which the maximum number of gate stages exceeds 5 is the smallest is determined as a register to be scanned. By deciding the register reg2 as the register to be scanned, the loop composed of the registers reg1, reg2, reg8 and the combination functional components A, B, H is also broken.

Next, one of the registers belonging to the remaining paths having more than five gate stages is determined as a register to be scanned so that there is no path having more than five gate stages. Registers reg2 to reg6, r
a path from the external input PI1 to the registers reg3 and reg, from the external input PI1 to the registers reg3 and reg
5, the path from the register reg4 to the register reg8,
Since a path (the number of gate stages: 6) through reg1 to the register reg2 remains as a path where the number of gate stages exceeds 5, the registers reg1, reg3, reg5, re
One of g6 and reg8 is determined as a register to be scanned.

If the register reg1 is determined as a register to be scanned, the number of the paths where the number of gate stages exceeds 5 becomes one, and the other registers reg3, reg
If any one of 5, 5, reg6, and reg8 is determined as a register to be scanned, the remaining two will be determined. Here, register reg1 is determined as a register to be scanned.

The remaining paths having more than 5 gate stages are the registers reg3 and reg5 from the external input PI1.
Since only the path to the external output PO1 (the number of gate stages is 6) is passed through, if any of the registers reg3 and reg5 is determined as a register to be scanned, there will be no path in the RTL circuit with more than 5 gate stages. Become. Here, register reg5 is determined as a register to be scanned.

As a result of the above processing, the RTL shown in FIG.
The circuit is easily inspected as shown in FIG. R in FIG.
The TL circuit includes hatched registers reg1 and reg.
By determining 2, reg4 and reg5 as registers to be scanned, the number of gate stages is 5 or less in each path from an external input or pseudo external input to an external output or pseudo external output. When the RTL circuit of FIG. 40 is expanded on the time axis, the number of gate stages in each time frame is likely to be 5 or less. In general, generation of a test input for a combinational circuit becomes more difficult as the number of gate stages increases. Therefore, as in the present embodiment, by specifying a structure in which the number of gate stages is n or less in each path from an external input or pseudo external input to an external output or pseudo external output as a circuit structure that is easy to inspect, Generation of inspection input is facilitated.

[0128]

As described above, according to the present invention, a register to be scanned is determined for an RTL circuit so as to have a circuit structure specified in advance and which can be easily inspected, so that a high fault detection rate is guaranteed in RTL. can do. In addition, since there is no need for design rework, the LSI design period can be shortened as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a process flow in a testability design method according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a classification of a synchronous sequential circuit according to a structure.

FIG. 3 is a directed graph illustrating an example of an RTL circuit targeted by the testability designing method according to the first embodiment of the present invention;

4 is a diagram illustrating a result of determining a register to be scanned for the RTL circuit illustrated in FIG. 3 when an acyclic structure is designated as a circuit structure that is easy to inspect;

5 is a diagram illustrating a result of determining a register to be scanned for the RTL circuit illustrated in FIG. 3 when a single alignment structure is designated as a circuit structure that is easy to inspect;

6 is a diagram showing a result of determining a register to be scanned for the RTL circuit shown in FIG. 3 in a case where a structure (balanced structure) having a combinational test input generation complexity is designated as a circuit structure that is easy to inspect. .

FIG. 7 is a flowchart illustrating a flow of processing in a testability design method according to a second embodiment of the present invention.

FIG. 8 is a directed graph showing an example of an RTL circuit targeted by the testability designing method according to the second embodiment of the present invention.

9 is a diagram illustrating a result of converting the RTL circuit illustrated in FIG. 8 by regarding a normal data input of a register to be scanned as a pseudo external output and using the data output as a pseudo external input.

FIG. 10 is a flowchart showing a processing flow in a test sequence generation method according to the first reference example of the present invention.

FIG. 11 is a flowchart showing a detailed processing flow of RTL time base expansion S20 in the test sequence generation method according to the first reference example of the present invention shown in FIG. 10;

FIG. 12 is a directed graph showing an example of an RTL circuit targeted by the test sequence generation method according to the first reference example of the present invention.

FIG. 13 is a diagram illustrating a time axis expansion of a pseudo external output PPO1 with respect to the RTL circuit illustrated in FIG. 12;

FIG. 14 is a diagram in which an external output PO1 is arranged in a time frame 5 and time axis expansion is performed with respect to FIG.

FIG. 15 is a diagram obtained by arranging an external output PO1 in a time frame 4 and expanding the time axis in FIG.

FIG. 16 is a diagram illustrating a result obtained by performing time axis expansion on the RTL circuit illustrated in FIG. 12;

17 is a diagram illustrating a gate-level circuit generated by performing logic synthesis on the RTL circuit illustrated in FIG. 12;

FIG. 18 is a time axis expansion combination circuit generated based on the time axis expansion RTL circuit shown in FIG. 16 and the gate level circuit shown in FIG. 17 with respect to the RTL circuit shown in FIG.

19 is a diagram showing a time axis expansion for the RTL circuit shown in FIG. 12, when an external output PO1 is arranged in a time frame 5. FIG.

20 is a diagram showing a time axis expansion for the RTL circuit shown in FIG. 12, when the external output PO1 is arranged in the time frame 4. FIG.

FIG. 21 is a flowchart showing a flow of processing in a test sequence generation method according to a second reference example of the present invention.

FIG. 22 is a directed graph showing an example of an RTL circuit targeted by a test sequence generation method according to a second reference example of the present invention.

FIG. 23 is a diagram illustrating a result of grouping of combination functional components with respect to the RTL circuit illustrated in FIG. 22;

24 is a diagram illustrating a result obtained by performing time axis expansion on the RTL circuit illustrated in FIG. 23;

FIG. 25 is a diagram showing a time axis expansion combination circuit generated based on the time axis expansion RTL circuit shown in FIG. 24 with respect to the RTL circuit shown in FIG. 22;

FIG. 26 is a flowchart showing a flow of processing in a test sequence generation method according to a third reference example of the present invention.

FIG. 27 is a directed graph illustrating an example of an RTL circuit targeted by a test sequence generation method according to a fourth reference example of the present invention.

28 is a diagram showing a result of replacing a register to be scanned with a pseudo external input and a pseudo external output in the RTL circuit shown in FIG. 27;

FIG. 29 is a circuit diagram of the RTL circuit shown in FIG. 28 according to the present invention;
It is a figure showing time axis development concerning a 4th example .

FIG. 30 is a circuit diagram of the present invention for the RTL circuit shown in FIG. 28;
It is a figure showing the result of having performed time axis expansion concerning a 4th example .

FIG. 31 is a directed graph illustrating an example of an RTL circuit targeted by a test sequence generation method according to a fifth reference example of the present invention.

FIG. 32 is a circuit diagram of the RTL circuit shown in FIG. 31 according to the present invention;
It is a figure showing time axis development concerning a 5th example .

FIG. 33 is a circuit diagram of the present invention for the RTL circuit shown in FIG. 31;
It is a figure which shows the result of having performed the time axis expansion | deployment which concerns on a 5th reference example , (a) is a figure when the external output PO2 is arrange | positioned at the time frame 4, (b) is the external output PO2 at the time frame 3. FIG.

FIG. 34 is a diagram showing a result of converting the time-axis-expanded RTL circuit shown in FIG. 33 to a gate level, and (a) of FIG.
33A is a diagram illustrating a conversion result, and FIG. 33B is a diagram illustrating a conversion result of FIG.

FIG. 35 is a diagram schematically illustrating an example of an RTL circuit targeted by the testability designing method according to the third embodiment of the present invention;

36 is a directed graph showing a configuration of each block of the RTL circuit shown in FIG. 35. FIG.
(B) is a figure which shows the block B, (c) is a figure which shows the block C, respectively.

FIG. 37 is a directed graph showing an example of an RTL circuit targeted by the testability designing method according to the fourth embodiment of the present invention.

FIG. 38 is a circuit diagram showing the RTL circuit shown in FIG. 37 according to the present invention;
It is a figure showing the result of having performed inspection facilitation concerning a 4th embodiment .

FIG. 39 is a directed graph showing an example of an RTL circuit targeted by the testability designing method according to the fifth embodiment of the present invention;

40 is a diagram illustrating the RTL circuit shown in FIG. 39 according to the present invention;
It is a figure showing the result of having performed inspection facilitation concerning a 5th embodiment .

[Explanation of symbols]

 reg1 to reg11 Registers A to K, a to n Combined functional components PI1, PI2, PI3 External inputs PO1, PO2 External outputs PPI1, PPIr4, PPIr5 Pseudo external inputs PPO1, PPOr4, PPOr5 Pseudo external outputs O1 to O7 Block outputs

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hideo Fujiwara 7-22-1-4 Kodai, Seika-cho, Soraku-gun, Kyoto (56) References JP-A-7-65064 (JP, A) Tomoya Takasaki et al., "Extended Partial Scan Design that Can Generate Combinatorial Tests," IEICE Technical Report FTS 96-41-47, IEICE, October 1996, Vol. 96, No. 291; 1-8 2. Hideo Fujiwara, "Sequential circuit structure capable of test generation with combinational test generation complexity and its application", IEICE Technical Report FTS95-63-74, IEICE Technical Report, December 1995, Vol95, No411 , P. 17-24 3. Akira Motohara, 4 others, "Design method for testability at the register transfer level," Symposium on Information Processing Society of Japan DA Symposium '94, Information Processing Society of Japan, August 1994, Vol. 94, no. 5, p. 89-94 4. Toshinori Hosokawa et al., "Design for testability using RTL circuit partitioning", Symposium on Information Processing Society, DA Symposium '96, Information Processing Society of Japan, August 1996, Vol. 96, No. 4, p. 225-230 5. Toshinori Hosokawa, 3 others, "Partial scan design method based on n-fold alignment structure", Symposium on Information Processing Society of Japan DA Symposium '97, Information Processing Society of Japan, July 1997, Vol. 97, No4, pp. 51-56

Claims (2)

(57) [Claims] 1. A register transfer level (RTL,
Register transfer level) An RTL circuit, which is an integrated circuit designed by Register Transfer Level, is a testability design method for making a design change so that the post-manufacture test becomes easy. Step 1, the structure of the RTL circuit at the time of inspection regards the normal data input of the register to be scanned as a pseudo external output,
When the data output is regarded as a pseudo external input, the first
A second step of determining a register to be scanned from the registers in the RTL circuit so as to have a circuit structure that is easy to inspect specified in the first step. The circuit structure is that the external input or pseudo external input and the external output or pseudo
For any pair with a similar external output, the external input
Power or pseudo external input and external output or pseudo external output
, The number of registers in each path is n or less (n
Is a natural number), which is an n-fold acyclic structure. 2. A register transfer level (RTL,
Register transfer level) This is an easy-to-test design method for making design changes to an RTL circuit, which is an integrated circuit designed by register transfer, so as to facilitate the post-manufacturing test. Step 1, the structure of the RTL circuit at the time of inspection regards the normal data input of the register to be scanned as a pseudo external output,
When the data output is regarded as a pseudo external input, the first
A second step of determining a register to be scanned from the registers in the RTL circuit so as to have a circuit structure that is easy to inspect specified in the first step. In the circuit structure of, the number of gates constituting the combinational functional component is n or less (n is 0 or a natural number) in each path from the external input or pseudo external input to the external output or pseudo external output.
A design method for facilitating inspection, wherein