JP3117269B2 - Method for manufacturing active matrix liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing an active matrix liquid crystal display device, comprising a sample-and-hold means for sampling and holding synchronously particular three primary color signals were cyclically recombination horizontal scanning period in the horizontal shift register , The sample-and-hold means comprises a horizontal shift register.
The switch means and the buffer capacity which use the signal as the control signal
A, a manufacturing method of an active matrix liquid crystal display device for transferring a hold signal to each pixel of the selected line in the vertical shift register.

[0002]

2. Description of the Related Art Recent advances in semiconductor integration technology have
Circuit components used for word processors, personal computers, and the like have been reduced in size and weight, and accordingly, various matrix-type flat panel display devices have been developed. Among them, the liquid crystal display device has advantages such as low voltage and low power consumption, and has been attracting attention because it is suitable for IC. T
As a system of a matrix type liquid crystal display device used for V and the like, there are a simple matrix system and an active matrix system. In the active matrix system, a pixel switch is provided for each pixel to cut off an unrelated signal at the time of non-selection in order to prevent cross-talk between scanning lines generated in the simple matrix system.

FIG. 12 is a diagram showing a conventional basic drive circuit of the active matrix liquid crystal display device.

In FIG. 1, reference numeral 901 denotes a horizontal shift register, 902 denotes a vertical shift register, 903 denotes a sampling MOS transistor, 904 denotes a TFT (thin film transistor), 905 denotes a liquid crystal cell, and 906 to 908 denote 3-line video inputs.

[0005] Three line video inputs 906-908 include:
A signal (which becomes an image signal) in which the connection order of the R, G, and B primary color signals is cyclically changed for each horizontal cycle in accordance with the arrangement of the color filters in the horizontal direction of the liquid crystal color matrix panel is input.

The horizontal lines are sequentially selected by the vertical shift register 902, and the video signals input to the three-line video inputs 906 to 908 are sampled by the horizontal shift register 901 and the sampling MOS transistor 903, and the liquid crystal cell of the selected line is sampled. Are written sequentially.

[0007]

However, such a conventional configuration has the following problems.

That is, one horizontal scanning period of 63.5 NTSC.
The effective scanning period other than the horizontal blanking period in μsec is about 50 μsec. However, as the definition of the liquid crystal panel increases and the number of pixels increases, the writing time per pixel becomes extremely short. For example, if the horizontal line is 50
Assuming 0 pixels, the writing time per pixel is 100
Only nsec.

When the number of pixels is increased and the aperture ratio is increased, the size of the TFT 904 is limited, so that the ON-state resistance cannot be reduced.

In the active matrix system, T
Since the writing is performed via the FT, the speed is determined by a time constant determined by the resistance of the TFT when the TFT is ON and the capacitance of the liquid crystal cell, and it is difficult to satisfy the writing time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an active matrix type liquid crystal device using a liquid crystal element as a display element so as to be able to drive at a higher speed and to achieve a high pixel and high definition high speed drive in view of the above-mentioned problems of the prior art. It is to be able to correspond to what needs.

[0012]

A method of manufacturing an active matrix liquid crystal display device according to the present invention includes sample and hold means for sampling and holding three primary color signals cyclically rearranged in a horizontal scanning cycle in synchronization with a horizontal shift register. , The sample-and-hold means comprises a horizontal shift register.
The switch means and the buffer capacity which use the signal as the control signal
It has a manufacturing method of the active matrix liquid crystal display device for transferring a hold signal to each pixel of the selected line in the vertical shift registers, at least, and said buffer capacitor and said Sui <br/> pitch means , it is provided the single crystal semiconductor layer formed on the light transmissive substrate surface, the single crystal semi
The conductor layer is made of a non-porous single bond on a porous Si substrate.
Insulation formed on the surface of the crystal layer or on the non-porous single crystal layer
The surface of the layer is bonded to a light-transmitting substrate,
Treating the etched Si substrate at least including wet chemical etching.
The light-transmissive substrate or the insulating
Active, a non-porous single-crystal layer formed on the edge layer
This is a method for manufacturing a matrix liquid crystal display device.

In the method of manufacturing an active matrix liquid crystal display device according to the present invention, the three primary color signals cyclically recombined in the horizontal scanning cycle and the polarity inversion signal thereof are synchronized with the horizontal shift register and the horizontal scanning cycle or each pixel cycle is performed. in, they comprise a sample-and-hold means for sampling and holding alternately pixel signal and its polarity inversion signal, the sample-hold hand
The stage is a switch that uses the signal of the horizontal shift register as a control signal.
A method of manufacturing an active matrix liquid crystal display device having a switching means and a buffer capacity and transferring a held signal to each pixel of a line selected by a vertical shift register.
I, at least, and said buffer capacitor and said switching means, becomes disposed on the light transmissive substrate single crystal semiconductor layer formed on the surface <br/>, the single crystal semiconductor layer was made porous
The surface of the non-porous single crystal layer on the Si substrate or the non-porous single crystal layer
The surface of the insulating layer formed on the porous single crystal layer
At least, the porous Si substrate is bonded at least
By removing by processing including wet chemical etching,
Non-porous formed on the light transmitting substrate or the insulating layer
Of active matrix liquid crystal display device
It is a manufacturing method.

[0014]

[0015]

In an active matrix liquid crystal display device,
In order to be able to drive at higher speeds and to be able to respond to those requiring high pixel and high definition high speed driving,
What is necessary is just to provide a sample hold means. That is, the three-line video input signal may be temporarily held in the sample-and-hold means, and the held three-line video input signal may be written to the selected pixel at once.

However, for example, 230,000 pixel NTSC
Non-interlaced drive, 1 pixel size 20 × 30 μm
In consideration of the panel No. 1 and higher image quality and realization of the display performance of 64 gradation levels, the sample and hold capacity constituting the sample and hold means is about 1
About 0 pF is required.

The sample-and-hold capacity is expressed as polyS
If an insulating layer is formed on i and then polySi is provided, the capacitance width is about 0.2 mm, which results in an increase in size. To reduce this size,
When the thickness of the insulating layer between polySis is reduced, problems such as a decrease in breakdown voltage and an increase in leak current occur.

Next, the sample hold capacity is 10
It is required to write a video signal at a high speed of MHz, but to write at this frequency, it is necessary to reduce the ON resistance of the switching transistor.
In the case of lySiTFT, W / L = 4500 μm / 2 μm
It is necessary to increase the size until. This is because a pattern has a very long W and is practically difficult to lay out.

According to the present invention, there is provided an SOI device capable of forming a single-crystal Si layer having excellent crystallinity on an insulating surface of a light-transmitting substrate such as glass.
Using the technique, the sample-and-hold capacitor and the switching transistor that constitute the sample-and-hold means are formed in such a single-crystal Si layer. When a sample-hold capacitor is formed from a single-crystal Si material as in the present invention, a high-quality oxide film can be formed, and the capacitance width is about 0.04.
~ 0.06mm, chip size 0.1
It is possible to reduce the size by 4 to 0.16 mm. Further, by using the single crystal Si-TFT technology, the TFT size can be about W / L = 70/2 to 90/2 (μm / μm). Therefore, even if it is laid out, the chip size is reduced by about 0.36 to 0.38 mm,
Both the capacitance and the TFT can reduce the chip size by about 0.5 mm and reduce the cost. The present invention is particularly important for a high-quality, high-performance liquid crystal display device.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram of a drive circuit of an active matrix liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a view of a portion surrounded by a chain line 110 in FIG. FIG. 3 is a circuit diagram, and FIG. 3 is a timing chart.

1 and 2, reference numeral 101 denotes a horizontal shift register; 102, a sample-and-hold (S / H) circuit;
3 is a vertical shift register, 104 is an active matrix liquid crystal panel, 105 is a transfer MOS transistor, 10
6 to 108 are 3-line video inputs, 109 is a transfer pulse, 201 is a sampling MOS transistor, 202
Is the buffer capacity.

The three-line video inputs 106-108 include:
A signal (image signal) in which the connection order of the R, G, and B primary color signals is cyclically changed for each horizontal cycle according to the arrangement of the color filters in the horizontal direction of the liquid crystal color matrix panel 104 is input.

The video signal is supplied to the horizontal shift register 101
The sampling is sequentially performed by the sampling MOS transistor 201 during one horizontal scanning period (1H period), and is held in the buffer capacitance 202. The held charge is transferred via the transfer MOS transistor 105 during the horizontal blanking period and written to the pixel selected by the vertical shift register 103, as shown in the timing chart of FIG.

According to such a driving method, the sampling MOS transistor 201 can be made larger than the TFT of each pixel, so that the resistance value at ON can be made smaller. Therefore, the time constant determined by the capacity of the buffer capacity 202 also becomes small, and the sampling time can be satisfied even when the number of pixels increases.

Also, the time required for the transfer to each pixel may be within one horizontal blanking period, and the speed of the drive circuit can be more than 100 times faster than the conventional method.

The circuit component shown in FIG. 2 is formed on a single crystal layer formed on a glass substrate. FIG. 4 is a cross-sectional view showing the structure of the circuit component of FIG. 2, and FIG. 5 is a cross-sectional view for explaining the manufacturing process.

As shown in FIG. 4, S
A sampling MOS transistor 201, a buffer capacitor 202, and a transfer MOS transistor 105 are formed via an iO ₂ oxide layer 6, and each semiconductor element region is insulated and separated by a selective insulating region 4.

Hereinafter, a method of manufacturing the above-described circuit component will be described.

As shown in FIG. 5A, first, a Si single crystal substrate is prepared and made porous. The porous substrate may be formed on the entire substrate or a part of the substrate. Next, the thin film single crystal layer 2 is formed on the surface of the substrate 1 which has been epitaxially grown and made porous by a CVD method such as a thermal CVD method, a plasma CVD method, or an optical CVD method, a bias sputtering method, or a growth method such as a liquid phase growth method. Form.

Here, the porous Si used in the present invention will be described.

The Si single crystal substrate is made porous by an anodizing method using an HF solution. The porous Si layer, the monocrystalline Si as compared with the density of 2.33 g / cm ^3, the density of 1.1~0.6g / cm ³ by changing the density of HF solution concentration to 50 to 20% Range. This porous layer is easily formed on a P-type Si substrate for the following reasons. According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer.

The porous Si was prepared by Uhril et al.
It was discovered during the research process of electropolishing of semiconductors in 56 (A. Uhril, Bell Syst. Tech.
J. , Vol 35, p. 333 (1956)). In addition, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in an HF solution requires holes, and the reaction is as follows (T Unagi: J. Electrochem.So
c. , Vol. 127, p. 476 (1980)).

[0033] Si + 2HF + (2-n ) e + → SiF 2 + 2H + + ne - SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or, Si + 4HF + (4- λ) e + → SiF 4 + 4H + + λe ^{_{- SiF 4 + 2HF → H 2}} SiF 6 where e ⁺ and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the number of holes required for dissolving one atom of silicon, respectively, and it is assumed that porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon having holes is easily made porous. In making this porous,
Selectivity has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Onaka, Kajiwara; IEICE Technical Report, vol 79, SSD79-9549 (197)
9), K. Imai; Solid-State Elec
tronics vol 24, 159 (198
1)). P-type silicon having holes as described above is easily made porous, and P-type silicon can be selectively made porous.

On the other hand, it has been reported that high-concentration N-type silicon also becomes porous (RP Holmstorm, IJ.
Y. Chi Appl. Phys. Lett. vol.
42, 386 (1983)), and it is important to select a substrate that can realize porosity regardless of P and N.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Regardless, single crystallinity is maintained.

Further, since the porous layer has a large amount of voids formed therein, the density is reduced to less than half. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the ordinary etching rate of the single crystal layer.

The method of etching each porous Si includes the following. Etch porous Si with aqueous NaOH solution (G. Bonchil, R. Herino, K. Barr)
la, and j. C. Pfister, J .; Elec
trochem. Soc. , Vol. 130, no.
7, 1611 (1983)).

[0039] Etch porous Si with an etchant capable of etching single crystal Si. It has been known.

In the above method, a hydrofluoric-nitric acid-based etchant is usually used. At this time, the etching process of Si is performed as shown in the order of Si + 2O → SiO ₂ SiO ₂ + 4HF → SiF ₄ + H ₂ O. There is oxidized with nitric acid, then transformed into SiO _2, the etching of Si proceeds by etching the SiO ₂ with hydrofluoric acid.

Similarly, as a method for etching crystalline Si, there are an ethylenediamine-based KOH-based hydrazine-based method and the like in addition to the above-mentioned hydrofluoric-nitric acid-based etchant.

Another important method for selectively etching porous Si is to use hydrofluoric acid or buffered hydrofluoric acid which has no etching effect on crystalline Si. In this etching, hydrogen peroxide acting as an oxidizing agent may be further added. Hydrogen peroxide acts as an oxidizing agent, and the reaction rate can be controlled by changing the ratio of hydrogen peroxide. Further, an alcohol acting as a surfactant may be added. Alcohol acts as a surface active agent, instantaneously removes bubbles of a reaction product gas from the etching surface, and enables uniform and efficient selective etching of porous Si.

FIG. 6 shows the etched porous material when porous Si and non-porous single-crystal Si were infiltrated into a mixed solution of hydrofluoric acid, alcohol and hydrogen peroxide without stirring. 4 shows the etching time dependency of the thickness of Si and single crystal Si.

Hereinafter, the porosity and etching process according to the present invention will be specifically described.

The porous Si is prepared by anodizing single crystal Si, and the conditions are as follows. The starting material of porous Si formed by anodization is not limited to single-crystal Si, but may be Si having another crystal structure.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 Time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) A single crystal having a thickness of about 1 μm by the CVD method on the porous Si substrate 1 prepared under the above conditions. An Si layer 2 was formed.

As shown in FIG. 5B, a light-transmitting glass substrate 3 is prepared and attached to the surface of the single-crystal Si layer 2 on the porous Si substrate 1. This bonding step is performed by bringing the cleaned surfaces into close contact with each other, and then heating to 900 ° C. in an oxygen atmosphere or a nitrogen atmosphere. Prior to this bonding step, an oxide layer 6 may be formed on the surface of the non-porous single-crystal silicon layer 2. Oxide layer 6 is formed to reduce the interface state of single crystal silicon layer 2 which is the final active layer.

If necessary, as an etching prevention film,
An Si ₃ N ₄ layer 5 is deposited, and the whole of the two bonded substrates is covered to form a Si ₃ N ₄ layer on the porous surface of the porous silicon substrate.
₃ N ₄ layer is removed. Si as another etching prevention film
Instead of ₃ N ₄ layer may be used Apiezon Wax.

Next, the bonded substrate is placed at room temperature for 4 hours.
A mixture of 9% hydrofluoric acid, alcohol and hydrogen peroxide solution (1
0: 6: 50) (open circles) without infiltration. The porous Si was rapidly and uniformly etched with a high degree of surface properties. The etching rate depends on the solution concentration and
Depends on temperature.

As described above, in particular, by adding alcohol, air bubbles of the reaction product gas by etching can be instantaneously removed from the etching surface without stirring, and the porous material can be uniformly and efficiently removed. Si can be etched. In particular, by adding hydrogen peroxide solution, the oxidation of Si can be accelerated, and the reaction rate can be increased as compared with the case of no addition, and by further changing the ratio of the hydrogen peroxide solution, The reaction rate can be controlled.

As the alcohol used in the present invention, besides ethyl alcohol, an alcohol such as isopropyl alcohol which can be practically used in the production process and the like and which can achieve the above-mentioned effect of adding alcohol can be used.

In this manner, the porous Si substrate 1 is entirely etched to leave the single crystal silicon layer 2 thinned on the light transmitting glass 3.

Prior to the etching, the porous Si substrate 1 may be thinned in advance from the back side by machining such as grinding or polishing. In particular, in the case where the entire Si substrate is not made porous, it is preferable that the thickness be reduced by machining until the porous layer is exposed.

FIG. 5C shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 5 as an etching prevention film in FIG. 5B, the single crystal Si layer 2 having a crystallinity equivalent to that of a silicon wafer is flattened on the light transmitting glass substrate 3. In addition, it is formed into a large area over the entire area of the light transmissive glass substrate by being uniformly and thinly formed.

The selective insulating region 4 is formed at a predetermined position of the single crystal Si layer 2 on the light transmissive glass substrate 3 thus obtained by ROSOS oxidation or the like, and an element isolation region is formed. The sampling MOS transistor 201 and the buffer capacitance 2 as shown in FIG.
02. The transfer MOS transistor 105 is formed by a normal MOS transistor manufacturing process. (Second Embodiment) FIG. 7 is a partial circuit diagram of a drive circuit of an active matrix liquid crystal display device according to a second embodiment of the present invention, and corresponds to a portion surrounded by a chain line 110 in FIG. . FIG. 8 is a timing chart.

In FIG. 7, reference numerals 106 to 108 denote 3-line video inputs, 201 denotes a sampling MOS transistor, 401 and 402 denote first transfer gates, 403 and 404 denote second transfer gates, 405 and 406 denote buffer capacities, and 407 408 and 408 are first transfer gate pulses, and 409 and 410 are second transfer gate pulses. The three-line video input is the same as in the first embodiment.

Next, the operation will be described with reference to the timing chart of FIG.

First, in the n-th line, the pulse φ _S1 407 is at H level.
Since high (H) and the pulse φ _T1 409 are LOW (L), when the sampling MOS transistor 201 whose signal is sent from the horizontal shift register to the gate is turned on,
The video line signal is held in the first buffer capacity 405.

Next, on the (n + 1) th line, the pulse φ _S1 407
Is L, and the pulse φ _T1 409 is H, so that the charge held in the first buffer capacitance is written to each pixel. At the same time, since the pulse φ _S2 408 is H and the pulse φ _T2 410 is L, the signal of the video line is held in the second buffer capacitor 406 when the sampling MOS transistor 201 whose signal is sent from the horizontal shift register to the gate is turned on. Is done.

By repeating the above operation, the sampling and holding of the video signal in each line and the transfer to each pixel are performed alternately using different buffer capacities.

According to such a driving method, the time required for transfer to each pixel may be one horizontal scanning period.

The horizontal blanking period is as short as 3 μsec.
It may be performed within the sec period, and a margin of 10 times speed is generated.

Note that the circuit configuration of FIG.
As in the first embodiment shown in FIG. 5, a single crystal Si layer is formed on the glass substrate manufactured in the manufacturing process of FIG. (Third Embodiment) FIG. 9 is a partial circuit diagram of a drive circuit of an active matrix liquid crystal display device according to a third embodiment of the present invention, and corresponds to a portion surrounded by a chain line 110 in FIG. . In the present embodiment, in order to suppress flicker on the entire panel of the active matrix liquid crystal display device, writing is performed in mutually adjacent pixels in the vertical or horizontal direction with opposite polarities. FIG. 10 is a timing chart for writing with the opposite polarity in the vertical direction, and FIG. 11 is a timing chart for writing with the opposite polarity in the horizontal direction.

In FIG. 9, 605-607, 608-
610 is a 3-line video input and its inverted signal, 61
1 and 612 are forward / inverting selection pulses, 109 is a transfer pulse, 601 and 602 are sampling MOS transistors, 603 and 604 are forward and inverting transfer gates, respectively, 202 is a buffer capacitor,
105 is a transfer MOS transistor.

First, the operation when writing in mutually adjacent pixels in the vertical direction with opposite polarities will be described with reference to the timing chart of FIG. First, in the n-th line, the pulse φ
_{Since inv} is L and pulse φ _inv ′ (here, the inverted signal is indicated with “′” instead of “￣” unlike the drawing. The same applies to the following), the horizontal shift register When the sampling MOS transistors 601 and 602 are turned on, a non-inverted video signal is sampled and held in the buffer capacitance 202. This signal is transferred to the MO during the next horizontal blanking period.
The S transistor 105 is turned on, and the data is written to each pixel. Next, since the pulse φ _inv is H and the pulse φ _inv ′ is L on the (n + 1) th line, the inverted video signal is sampled and held in the buffer capacity 202. This signal is written to each pixel in the next horizontal blanking period.

Further, the signals of the pulse φ _inv and the pulse φ _inv ′ are inverted every vertical scanning period (one frame).
When viewed at an arbitrary pixel, it is AC driven.

Since the waveform written on a certain line is shifted by one field with respect to the adjacent line, the optical flicker component is shifted by 周期 period, the fundamental wave becomes one field period, and the effective frequency is doubled. Will be. For this reason, flicker is greatly suppressed.

Next, a description will be given of an operation when writing is performed in mutually adjacent pixels in the horizontal direction with opposite polarities in accordance with the timing chart of FIG. Since the pulses φ _inv and φ _inv ′ are synchronized with the clock of the horizontal shift register, video signals of opposite polarities are sampled and held in the buffer capacitors 202 adjacent to each other. This signal is transferred to each pixel in the next horizontal blanking period.

Further, since the signals of the pulse φ _inv and the pulse φ _inv ′ are inverted every vertical scanning period (one frame),
When viewed at an arbitrary pixel, it is AC driven. The effect is the same as in the case of the vertical direction.

It should be noted that the circuit configuration of FIG.
As in the first embodiment shown in FIG. 5, a single crystal Si layer is formed on the glass substrate manufactured in the manufacturing process of FIG.

[0071]

As described above in detail, according to the present invention, higher-speed driving can be performed, high-speed driving with high resolution and high resolution can be achieved, and chip size and cost can be reduced. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a drive circuit of an active matrix liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a portion surrounded by a chain line in FIG.

FIG. 3 is a timing chart of the circuit unit in FIG. 2;

FIG. 4 is a cross-sectional view illustrating a structure of a circuit configuration unit in FIG. 2;

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the circuit configuration section in FIG. 2;

FIG. 6 is a diagram showing the etching time dependence of the thickness of porous Si and single-crystal Si.

FIG. 7 is a partial circuit diagram of a drive circuit of an active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 8 is a timing chart of the circuit section of FIG. 7;

FIG. 9 is a partial circuit diagram of a drive circuit of an active matrix liquid crystal display device according to a third embodiment of the present invention.

FIG. 10 is a timing chart in the case of writing with the opposite polarity in the vertical direction.

FIG. 11 is a timing chart when writing is performed in the opposite direction in the horizontal direction.

FIG. 12 is a diagram showing a conventional basic drive circuit of an active matrix type liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 101 horizontal shift register 102 sample hold (S / H) circuit 103 vertical shift register 104 active matrix liquid crystal panel 105 transfer MOS transistor 106 3-line video input 107 3-line video input 108 3-line video input 109 transfer pulse 201 sampling MOS transistor 202 buffer capacity

Continuation of the front page (56) References JP-A-2-282723 (JP, A) JP-A-3-287291 (JP, A) JP-A-2-82295 (JP, A) JP-A-2-82294 (JP) JP-A-61-14697 (JP, A) JP-A-63-157198 (JP, A) JP-A-63-74035 (JP, A) JP-A-63-74098 (JP, A) JP-A-3-2177891 (JP, A) JP-A-3-180890 (JP, A) JP-A-3-224374 (JP, A) JP-A-61-23199 (JP, A) JP-A-63-55529 (JP, A) A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/133 505 G09G 3/36

Claims (6)

(57) [Claims] [Claim 1, further comprising a sample-and-hold means for sampling and holding in synchronization with the three primary color signals were cyclically recombination horizontal scanning period in the horizontal shift register, the sample holes
Means for using the signal of the horizontal shift register as a control signal
Manufacturing method of active matrix liquid crystal display device having switch means and buffer capacity and transferring held signal to each pixel of line selected by vertical shift register
A least, and the buffer capacity and the switching means, becomes disposed in the single crystal semiconductor layer formed on the light transmissive substrate surface, the single crystal semiconductor layer is porosified Si substrate on of,
On the surface of the non-porous single crystal layer or on the non-porous single crystal layer
Attach the formed insulating layer surface to the light-transmitting substrate,
At least a wet chemical etch is performed on the porous Si substrate.
The light-transmitting group by removing
Or a non-porous single crystal layer formed on the insulating layer.
Manufacturing method of an active matrix liquid crystal display device. 2. The method according to claim 1, wherein the sample-and-hold means and a transfer switch means for transferring a held signal to each pixel on a line selected by a vertical shift register include the single crystal half.
2. The active matrix liquid according to claim 1, which is provided on a conductor layer.
Manufacturing method of crystal display device. 3. The single crystal semiconductor layer is provided with two systems of the sample hold means and the transfer switch means.
Claims, characterized by using alternately every horizontal scanning period
Item 2. A method for manufacturing an active matrix liquid crystal display device according to item 2.
Law. 4. A pixel signal and its polarity inversion signal are alternated in a horizontal scanning cycle or each pixel cycle in synchronization with a horizontal shift register, the three primary color signals cyclically recombined in a horizontal scanning cycle and the polarity inversion signal thereof. Sample and hold means for sample and hold , the sample and hold means,
Switch using the horizontal shift register signal as a control signal
And a stage and buffer capacity, a manufacturing method of the active matrix liquid crystal display device for transferring a hold signal to each pixel of the selected line in the vertical shift registers, at least, and said buffer capacitor and said switch means A single crystal semiconductor layer formed on a light-transmitting substrate surface , wherein the single crystal semiconductor layer is formed on a porous Si substrate.
On the surface of the non-porous single crystal layer or on the non-porous single crystal layer
Attach the formed insulating layer surface to the light-transmitting substrate,
At least a wet chemical etch is performed on the porous Si substrate.
The light-transmitting group by removing
Or a non-porous single crystal layer formed on the insulating layer.
Manufacturing method of an active matrix liquid crystal display device. 5. The single crystal half unit comprising: the sample and hold unit; and a transfer switch unit for transferring a held signal to each pixel of a line selected by a vertical shift register.
5. The active matrix liquid according to claim 4, which is provided on a conductor layer.
Manufacturing method of crystal display device. 6. selectively formed insulating region in a predetermined region of the monocrystalline semiconductor layer, an insulating separation plurality of element regions are, the sample-and-hold means and said switching means to the plurality of isolation regions Claim 1 or claim with
Item 5. A method for manufacturing an active matrix liquid crystal display device according to item 4 .