JP3116178B2 - Reset signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal generating circuit, and more particularly to a reset signal generating circuit for generating a reset signal for initializing a logic circuit when the power of the logic circuit is turned on.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a reset signal generating circuit of this kind includes a resistor 8 and a capacitor 9 for integrating a power supply voltage from a power supply input terminal 1, and an inverter for converting the integrated voltage into a digital signal. Reset circuit 1 with 10
2 and a reset signal for initialization is supplied to the input terminal 11 of the logic circuit 3.

Next, the operation of this conventional example will be described with reference to the waveform diagrams of FIGS. 4, it is assumed that the time when the power is supplied to the power input terminal 1 is T0, and an ideal voltage rise (21 in FIG. 4) occurs at the same time when the power is supplied. The inverter 10 and the logic circuit 3 become operable at the same time when the power is turned on. Here, the capacitor 9
Is an integrated waveform, and becomes an input voltage 22 of the inverter 10. At time t0 when the power is turned on, the inverter 10
Is lower than the threshold voltage 24 of the inverter 10, the output of the inverter 10 outputs a logic "1" during the time t0 to t3 as shown in the lower characteristic diagram of FIG. The logic circuit 3 is reset through the reset signal input terminal 11 of FIG. After a lapse of time, the voltage across the capacitor 9 rises and exceeds the threshold voltage of the inverter 10 at time t3.
The output of 0 outputs a logic "0", and the logic circuit 3 is released from the reset state and becomes operable (23 in FIG. 4).

[0004]

However, in the conventional circuit, as shown in the waveform diagram of FIG. 5, when the actual power supply voltage of the power supply input terminal 1 gradually rises as indicated by 21 in FIG. , Time t3 before time t1 when power supply voltage 23 at which inverter 10 and logic circuit 3 can operate is reached.
In this case, the voltage across the capacitor 9 of the integrating circuit exceeds the threshold voltage of the inverter 10, and the timing at which the reset signal is output may be lost.

[0005]

SUMMARY OF THE INVENTION A reset signal generating circuit according to the present invention comprises a power supply voltage supply circuit for supplying a reset signal to the logic circuit when the power supply voltage rises at an initial stage of power supply supplied to the logic circuit from a power supply input terminal. A reset signal generating circuit including an integrating circuit for integrating the constant voltage and an inverter, a constant voltage diode and a resistor connected in series between the power input terminal and the ground, and a buffer for inputting a voltage at a common connection point between the two. And a switching diode connected from the buffer output to the integration circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the present embodiment. In the embodiment shown in FIG. 1, a constant voltage diode 4, a resistor 5, and a buffer 6 are added to the conventional circuit shown in FIG. In FIG. 1, a constant voltage diode 4
Is selected to have a value exceeding the threshold voltage of the buffer 6 when the power supply voltage reaches a specified voltage.

Next, the operation of this embodiment will be described with reference to FIG. In FIG. 2A, when the power applied to the power input terminal 1 is turned on at time t0, the voltage 21A is applied.
Gradually rises. When time t1 is reached, power supply voltage 23A at which logic circuit 3, buffer 6, and inverter 10 can operate
Becomes At this point, the input voltage of the buffer 6 is changed to the threshold voltage 2 of the buffer 6 by the constant voltage diode 4.
Therefore, the output of the buffer 6 is logic "0". The switching diode 7 connected to the output of the buffer 6 is in the ON state and the capacitor 9
Is in a discharged state, so that the input voltage 22
Since A is equal to or lower than the threshold voltage 24A of the inverter 10, the output of the inverter 10 is logic "1" and the logic circuit 3 is reset. When time elapses from time t1 to time t2, the input voltage 25 of the buffer 6 exceeds the threshold voltage 26 of the buffer 6, the output of the buffer 6 becomes logic "1", and the switching diode 7 is turned off to integrate. Charging of the capacitor 9 of the integrating circuit starts through the resistor 8 of the circuit. As shown in FIG. 2 (c), the charging of the capacitor 9 further proceeds, and the voltage at both ends (the inverter 1
When the 0 input voltage 22A) exceeds the threshold voltage 24A of the inverter 10, the output of the inverter 10 becomes logic "0", and the logic circuit 3 is released from the reset state and becomes operable.

[0008]

As described above, according to the present invention, by adding a constant voltage diode, a resistor and a buffer as a reset circuit, the power supply voltage gradually rises to reach the power supply voltage at which the logic circuit can operate. Since the reset signal is output even after the reset, the logic circuit can be securely initialized when the power is turned on.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a waveform chart in each part of the embodiment.

FIG. 3 is a circuit diagram of a conventional reset signal generation circuit.

FIG. 4 is a waveform diagram of each section when an ideal power supply voltage rises in a conventional example.

FIG. 5 is a waveform diagram of each unit when operation is abnormal in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply input terminal 2 Reset circuit 3 Logic circuit 4 Constant voltage diode 5,8 Resistance 6 Buffer 7 Switching diode 9 Capacitor 10 Inverter 11 Input terminal

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (1)

(57) [Claims] 1. A reset signal, comprising: an integration circuit for integrating a power supply voltage to supply a reset signal to the logic circuit when a power supply voltage rises in an initial stage of power supply supplied to a logic circuit from a power supply input terminal; and an inverter. In the generating circuit, a constant voltage diode and a resistor connected in series between the power supply input terminal and the ground, a buffer for inputting a voltage at a common connection point between the two, and a switching connected from the buffer output to the integration circuit A reset signal generation circuit, comprising: a diode.