JP3114303B2 - Thin film transistor panel and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is a thin film transistor panel 及 used in active matrix liquid crystal display device
And its manufacturing method.

[0002]

2. Description of the Related Art A thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device has the following structure.

FIGS. 3 to 6 show a conventional TFT panel. FIG. 3 is a plan view of a part of the TFT panel, and FIGS. 4, 5 and 6 are lines IV-IV and VV of FIG. And VI-VI
It is an expanded sectional view which follows a line.

In this TFT panel, on a transparent substrate 1 made of glass or the like, a number of pixel electrodes 2, a number of thin film transistors (TFTs) 3 as active elements thereof, and a gate electrode G of each thin film transistor 3 are connected. A gate line GL and a drain line (data line) DL connected to the drain electrode D of each thin film transistor 3 are formed.

[0005] The thin film transistor 3 generally has an inverted staggered structure. As shown in FIGS. 3 and 4, the thin film transistor 3 having the inverted stagger structure has a gate electrode G formed on the substrate 1, a gate insulating film 4 covering the gate electrode G, and An i-type semiconductor layer 5 is formed facing the gate electrode G, and a source electrode S and a drain electrode D are formed on the i-type semiconductor layer 5 via an n-type semiconductor layer 6. The n-type semiconductor layer 6 is a channel region (a region between the source electrode S and the drain electrode D) of the i-type semiconductor layer 5.
Are separated from each other.

The gate electrode G is formed integrally with a gate line GL formed on the substrate 1. The gate line GL and the gate electrode G are made of Al (aluminum) or an Al alloy, Cr (chromium), Ta (Tantalum) or the like. Also, the gate insulating film 4
Is formed of SiN (silicon nitride), the i-type semiconductor layer 5 is formed of a-Si (amorphous silicon), and the n-type semiconductor layer 6 is formed of a-Si doped with n-type impurities.
It is formed with.

On the channel region of the i-type semiconductor layer 4, a blocking layer 7 made of SiN or the like is formed. The blocking layer 7 forms a channel region of the i-type semiconductor layer 5 when a portion corresponding to the channel region of the n-type semiconductor layer 6 formed on the i-type semiconductor layer 5 is separated by etching in manufacturing the thin film transistor 3. Is also formed to prevent etching.

The gate insulating film 4 of the thin film transistor 3
Is formed over substantially the entire surface of the substrate 1 so as to cover the gate line GL, and the pixel electrode 2 and the drain line DL are formed on the gate insulating film (transparent film) 4.

The drain line DL is formed integrally with the drain electrode D of the thin film transistor 3.
The drain line DL, the drain electrode D, and the source electrode S are formed of a metal such as Al or an Al alloy, Cr, or Ta.

The pixel electrode 2 is formed of a transparent conductive film made of ITO or the like. The pixel electrode 2 is formed by forming one end thereof on the source electrode S of the thin film transistor 3. , Is connected to the source electrode S.

Further, the thin film transistor 3 and the drain line DL formed on the gate insulating film 4 are Si
It is covered with a protective insulating film 8 made of N or the like. This protective insulating film 8 is formed on almost the entire surface of the substrate 1 except for the portion on the pixel electrode 2, and the terminal portion DL of the drain line DL is formed.
3A is exposed by removing the protective insulating film 8 thereon as shown in FIGS. 3 and 5, and the terminal portion GLa of the gate line GL is exposed thereover as shown in FIGS. Of the gate insulating film 4 and the protective insulating film 8 are removed.

The above-mentioned TFT panel is manufactured by the following steps.

[Step 1] First, a gate metal film is formed on the substrate 1, and the metal film is patterned by photolithography to form a gate line GL and a gate electrode G.

[Step 2] Next, a gate insulating film 4, an i-type semiconductor layer 5, and a blocking layer 7 are sequentially formed on the substrate 1 so as to cover the gate line GL and the gate electrode G.

[Step 3] Next, the blocking layer 7
Is patterned into a shape covering the channel region of the i-type semiconductor layer 5 by a photolithography method.

[Step 4] Next, an n-type semiconductor layer 6 is formed, and a source and drain metal film is formed thereon.

[Step 5] Next, the source and drain metal films and the n-type semiconductor layer 6 are subjected to photolithography to form source and drain electrodes S and D and a drain line D.
At the same time, the i-type semiconductor layer 5 is patterned to the outer shape of the transistor element region.

In this case, the portion corresponding to the channel region of the n-type semiconductor layer 6 is separated on the blocking layer 7 formed on the i-type semiconductor layer 4, so that the channel of the n-type semiconductor layer 6 is separated. When the region corresponding portion is etched, the channel region of the i-type semiconductor layer 5 is not damaged by being etched. Note that this i
The type semiconductor layer 5 is left not only in the transistor element region but also under the drain line DL over the entire region.

[Step 6] Next, a transparent conductive film (ITO film or the like) is formed on the gate insulating film so as to cover the patterned source and drain metal films (source and drain electrodes S and D and drain line DL). Is formed.

[Step 7] Next, the transparent conductive film is patterned by photolithography to form a pixel electrode 2.

[Step 8] Next, a protective insulating film 8 is formed.

[Step 9] Next, the protective insulating film 8 is formed by photolithography on the portion above the pixel electrode 2 and the terminal portion DLa of the drain line DL and the gate line G.
L is patterned into a shape in which a portion above the terminal portion GLa is removed, and at the same time, a portion of the gate insulating film 4 on the terminal portion GLa of the gate line GL is removed to expose the terminal portions GLa and GLa. Complete the TFT panel.

[0023]

However, in the above-mentioned conventional method of manufacturing a TFT panel, the number of times of forming a resist mask until the TFT panel is completed is large, so that the manufacturing efficiency of the TFT panel is poor and the manufacturing cost is low. Also had the problem of being expensive.

That is, in the above conventional manufacturing method, (1) at the time of patterning the metal film for the gate (2) at the time of patterning the blocking layer 7 (3) the metal film for the source and drain, the n-type semiconductor layer 6 and the i-type At the time of patterning the semiconductor layer 5 (4) At the time of patterning the transparent conductive film (5) At the time of patterning the protective insulating film 8, a resist mask must be formed a total of five times. In addition, the cost becomes high, and in forming these resist masks, it is necessary to manufacture five types of exposure masks used for the exposure processing of the photoresist. This is a factor that increases manufacturing costs.

One object of the present invention is to reduce the amount of resist mass.
TFT that can be manufactured with high efficiency and low cost by the number of times of forming
To provide a panel. Another object of the invention is to provide i
It is an object of the present invention to provide a method capable of manufacturing a TFT panel efficiently and at low cost without damaging a channel region of a mold semiconductor layer and with a small number of times of forming a resist mask.

[0026]

According to the present invention, there is provided a thin film transistor panel comprising: a gate electrode patterned on a substrate;
A gate line and a gate terminal portion, a gate insulating film covering the gate electrode and the gate line, and a transistor element region on the gate insulating film are continuously patterned by the same photolithography process into an outer shape of the transistor element region. The n-type semiconductor layer and the i-type semiconductor layer, the source and drain electrodes patterned so as to be divided on the n-type semiconductor layer, and the n-type semiconductor layer on the terminal portion of the drain line on the gate insulating film. An n-type semiconductor terminal portion, an i-type semiconductor terminal portion, and a first drain terminal metal obtained by patterning the same material film together with patterning of the semiconductor layer, the i-type semiconductor layer, and the source and drain electrodes. and parts, on the source electrode, and the image <br/> element electrode formed by patterning a transparent conductive film, wherein On the first drain terminal metal part, the image
Patterning and forming the transparent conductive film together with the element electrodes
And a second drain terminal metal part. The method of manufacturing a TFT panel according to the present invention includes a first step of forming a gate metal film on a substrate, and patterning the metal film to form a gate line and a gate electrode. A second step of sequentially forming a gate insulating film, an i-type semiconductor layer, an n-type semiconductor layer, and a source / drain metal film covering the gate line and the gate electrode; A third step of patterning the type semiconductor layer and the i-type semiconductor layer into the shape of the drain line and the outer shape of the transistor element region, and covering the patterned source and drain metal films on the gate insulating film. a fourth step of forming a transparent conductive film, the transparent conductive film, the pixel electrode and the source, as well as patterned in the shape of the drain electrode and the drain line, this Using the resist mask used for patterning the transparent conductive film, the source of the transistor element region, and a fifth step of separating the drain metal film and the source electrode portion and the drain electrode portion, of the transparent conductive film A sixth step of performing anodic oxidation of the n-type semiconductor layer while leaving the resist mask used for patterning, and using a portion between the source and drain electrodes of the n-type semiconductor layer as an oxide insulating layer; A seventh step of forming a film, patterning the protective insulating film into a shape in which a portion on a pixel electrode, a portion on a drain line terminal, and a portion on a gate line terminal portion are removed; An eighth step of removing a portion on the gate line terminal portion.

[0027]

The thin film transistor panel of the present invention has a gate electrode.
After patterning at poles, gate lines and gate terminals
In the transistor element region on the gate insulating film, the n-type
Semiconductor layer, i-type semiconductor layer, and source and drain electrodes
Patterning and edge of drain line on gate insulating film
An n-type semiconductor terminal, an i-type semiconductor terminal,
The patterning of the first drain terminal metal part is collectively performed.
And then the transistor on the gate insulator
Along with patterning of the pixel electrode in the element region, the first
The second drain terminal metal part on the drain terminal metal part;
Less pattern as it is formed by turning
And a cleaning process. Soshi
According to the manufacturing method of the present invention, the portion between the source and drain electrodes of the n-type semiconductor layer is electrically separated as an oxide insulating layer by anodic oxidation, and the manufacturing method includes etching the n-type semiconductor layer. Is not something that separates
Even if the blocking layer is not formed on the channel region of the i-type semiconductor layer, no damage is given to the i-type semiconductor layer in the manufacturing process, so that the step of forming the blocking layer is unnecessary.

In this manufacturing method, since the TFT panel is manufactured through the above-described steps, the number of times of forming the resist mask is as follows: (1) when patterning the metal film for the gate; Metal film and n-type semiconductor layer and i
(3) Patterning of the transparent conductive film, separation of metal films for source and drain, and anodic oxidation of the n-type semiconductor layer (4) Protective insulating film A total of four times during patterning is sufficient.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a manufacturing process diagram of a TFT panel,
FIG. 2 is a sectional view of a part of the completed TFT panel. 1A to 1E show cross sections of a thin film transistor portion of a TFT panel, a terminal portion of a drain line, and a terminal portion of a drain line, respectively.

[Step 1] First, as shown in FIG. 1A, a gate metal film made of Al or an Al alloy, Cr, Ta or the like is formed on a transparent substrate 11 made of glass or the like. This metal film is patterned by a photolithography method to form a gate line GL (see FIG. 2) and a gate electrode G. Note that, in FIG.
Is a terminal portion of the gate line GL.

[Step 2] Next, as shown in FIG. 1A, a gate insulating film 12 made of SiN or the like is formed on the substrate 11 so as to cover the gate line GL and the gate electrode G. , A-Si i-type semiconductor layer 13 and n-type impurity doped a-Si n-type semiconductor layer 14
And a source / drain metal film 15 made of Al or Al alloy, Cr, Ta, or the like.

[Step 3] Next, as shown in FIG. 1B, the source / drain metal film 15, n-type semiconductor layer 14, and i-type semiconductor layer 13 are drain-lined by photolithography. It is patterned into the shape of DL (see FIG. 2) and the outer shape of the transistor element region. In FIG. 1B, DLa is a drain line D
L terminal portion.

[Step 4] Next, as shown in FIG. 1B, a transparent conductive film made of ITO or the like is formed on the gate insulating film 12 so as to cover the patterned source / drain metal film 15. 16 is formed.

[Step 5] Next, as shown in FIG. 1C, the transparent conductive film 16 is formed into the shape of the pixel electrode 16a and the source and drain electrodes S and D and the drain line DL by photolithography. In addition to patterning, using the resist mask 18 used for patterning the transparent conductive film 16, the source and drain metal films 15 in the transistor element region are etched. And a drain electrode D portion.

The source and drain electrodes S and D and the drain line DL formed by the above [Step 3] to [Step 5] are a two-layered structure including a source / drain metal film 15 and a transparent conductive film 16 thereon. A film structure, and n
The type semiconductor layer 14 and the i-type semiconductor layer 13 are also left under the drain line DL over the entire area including the terminal portion DLa.

In this embodiment, the transparent conductive film 1
6, the source and drain electrodes S and D and the drain line DL are patterned slightly wider than the patterning width of the source and drain metal film 15, and therefore, the source and drain electrodes S and D on the channel region side are formed. The portion excluding the edge and the drain line DL have a structure in which the side surfaces of the source and drain metal films 15 are also covered with the transparent conductive film 16.

[Step 6] Next, as shown in FIG. 1C, the n-type semiconductor layer 14 is left while the resist mask 18 used for patterning the transparent conductive film 16 is left.
Is performed, and a portion under the source electrode S and a portion under the drain electrode D of the n-type semiconductor layer 14 are electrically separated to complete the thin film transistor 20.

The anodic oxidation of the n-type semiconductor layer 14 is performed as follows.
The substrate 11 is immersed in an electrolytic solution so that the n-type semiconductor layer 14 is opposed to a counter electrode (platinum electrode) in the electrolytic solution.
The operation is performed by using the mold semiconductor layer 14 as an anode and the counter electrode as a cathode and applying a voltage between the two electrodes. As described above, when a voltage is applied between the n-type semiconductor layer 14 and the counter electrode in the electrolytic solution, a region (a region in contact with the electrolytic solution) of the n-type semiconductor layer 14 that is an anode that is not covered with the resist mask 18 is formed. The n-type semiconductor layer 14 is anodized by causing a chemical reaction.
Oxide region becomes the oxide insulating layer 14a.

In this case, the n-type semiconductor layer 14 is oxidized from its surface side, but since the oxidation depth is determined mainly by the applied voltage, the applied voltage depends on the thickness of the n-type semiconductor layer 14. By setting the voltage, the oxidized region of the n-type semiconductor layer 14 can be anodized over its entire thickness.
When the oxidized region of the n-type semiconductor layer 14 is anodized over its entire thickness in this manner, the portion under the source electrode S and the portion under the drain electrode D of the n-type semiconductor layer 14 are electrically separated.

In the above-described anodizing treatment, the n-type semiconductor layer 14 is energized by a drain line DL and a drain electrode D composed of a source / drain metal film 15 laminated thereon and a transparent conductive film 16 thereon. Can be performed as a current path, so that the n-type semiconductor layers 14 of all the thin film transistors 20 formed along the drain line DL can be uniformly anodized.

[Step 7] Next, the resist mask 18
Then, a protective insulating film 17 made of SiN or the like is formed on the substrate 11 as shown in FIG.

[Step 8] Next, as shown in FIG. 1E, the protective insulating film 17 is formed on the pixel electrode 16a, the terminal portion DLa of the drain line DL and the gate line GL by photolithography. Is patterned into a shape in which the portion above the terminal portion GLa is removed, and at the same time, the portion of the gate insulating film 12 above the gate line terminal portion GLa is removed by etching, so that the pixel electrode 16a, the drain line terminal portion DLa and the gate are removed. The line terminal portion GLa is exposed to complete the TFT panel.

That is, in the method of manufacturing the TFT panel, the portion between the source and drain electrodes S and D of the n-type semiconductor layer 14 is electrically separated as an oxide insulating layer 14a by anodizing treatment. Since the method does not separate the n-type semiconductor layer by etching as in the conventional manufacturing method, even if the blocking layer is not formed on the channel region of the i-type semiconductor layer 13, the manufacturing process can be performed. without damaging the i-type semiconductor layer 13;
Therefore, the step of forming the blocking layer is unnecessary.

In the manufacturing method of the above embodiment, since the TFT panel is manufactured in the above-described steps, the number of times of forming the resist mask is as follows: (1) When patterning the gate metal film; , Drain metal film 15 and n-type semiconductor layer 14
And patterning of the i-type semiconductor layer 13 to the shape of the drain line DL and the outer shape of the transistor element region. (3) Patterning of the transparent conductive film 16, separation of the source / drain metal film 15, and anodic oxidation of the n-type semiconductor layer 14. (4) The patterning of the protective insulating film 17 may be performed four times in total (five times in the conventional manufacturing method).

Therefore, according to the above manufacturing method, a TFT panel can be manufactured with high efficiency and low cost without damaging the channel region of the i-type semiconductor layer 13 and with a small number of times of forming a resist mask.

In addition, the above-described manufacturing method includes the steps of:
Since the blocking layer is not formed on the third channel region, the manufacturing yield of the TFT panel can be improved as compared with the conventional manufacturing method.

That is, in the conventional manufacturing method, if there is a pinhole in the i-type semiconductor layer, the blocking layer formed on the i-type semiconductor layer is etched at the time of patterning by photolithography. The etchant reaches the gate insulating film through the pinhole of the i-type semiconductor layer, and this gate insulating film is also etched to generate a pinhole defect. When such a pinhole defect occurs in the gate insulating film, an interlayer short-circuit (short-circuit between the gate electrode and the source / drain electrode or short-circuit between the gate line and the drain line) occurs at a thin film transistor portion or a line intersection. As a result, the manufacturing yield of the TFT panel is deteriorated.

On the other hand, the manufacturing method of the above embodiment is
Since the blocking layer is not formed on the i-type semiconductor layer, the gate insulating film is not etched at the time of patterning the blocking layer as in the conventional manufacturing method. , T
The production yield of the FT panel can be improved.

[0049]

The thin film transistor panel of the present invention has a
Pattern at gate electrode, gate line and gate terminal
In the transistor element area on the gate insulating film after
N-type semiconductor layer, i-type semiconductor layer, and source and drain
Patterning of the drain electrode and the drain line on the gate insulating film.
N-type semiconductor terminal and i-type semiconductor terminal
Pattern and the first drain terminal metal part.
Can be stopped, and then the
With the patterning of the pixel electrode in the transistor element region
A second drain terminal on the first drain terminal metal part;
Because it is formed by patterning the metal part
It can be formed by a small number of patterning steps
Become. According to the manufacturing method of the present invention, a portion between the source and drain electrodes of the n-type semiconductor layer is electrically separated as an oxide insulating layer by anodizing treatment.
Since the isolation is not performed by etching the type semiconductor layer, the i-type semiconductor layer is not damaged in the manufacturing process even if the blocking layer is not formed on the channel region of the i-type semiconductor layer. The step of forming the blocking layer is unnecessary.

According to this manufacturing method, the number of times of forming the resist mask in the manufacturing process of the TFT panel is four.
Since the number of times required is five, the TFT panel can be manufactured with high efficiency and low cost with a small number of times of forming the resist mask as compared with the conventional manufacturing method requiring five times of forming the resist mask.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a TFT panel showing one embodiment of the present invention.

FIG. 2 is a plan view of a part of the completed TFT panel.

FIG. 3 is a plan view of a part of a conventional TFT panel.

FIG. 4 is an enlarged sectional view taken along the line IV-IV in FIG. 3;

FIG. 5 is an enlarged sectional view taken along line VV of FIG. 3;

FIG. 6 is an enlarged sectional view taken along the line VI-VI of FIG. 3;

[Explanation of symbols]

11: substrate, GL: gate line, GLa: terminal, G
... Gate electrode, 12 ... Gate insulating film, 13 ... I-type semiconductor layer, 14 ... N-type semiconductor layer, 14a ... Oxide insulating layer, 15 ...
Source / drain metal film, 16: transparent conductive film, 16a
... pixel electrode, S ... source electrode, DL ... drain line,
DLa: terminal portion, D: drain electrode, 17: protective insulating film, 18: resist mask, 20: thin film transistor.

Claims (2)

(57) [Claims] A gate electrode patterned on a substrate,
A gate line and a gate terminal portion; a gate insulating film covering the gate electrode and the gate line; and a transistor element region on the gate insulating film, which is continuously patterned by the same photolithography process into an outer shape of the transistor element region. The n-type semiconductor layer and the i-type semiconductor layer, the source and drain electrodes patterned so as to be divided on the n-type semiconductor layer, and the n-type semiconductor layer at the terminal portion of the drain line on the gate insulating film. A semiconductor layer, the i-type semiconductor layer, and the source;
An n-type semiconductor terminal portion, i, obtained by patterning the same material film as these together with the drain electrode patterning
Patterning a transparent conductive film on the mold semiconductor terminal portion, the first drain terminal metal portion, and the source electrode;
And it made a pixel electrode, the first drain terminal metal part on the pixel electrode and the preparative
The second is formed by patterning the transparent conductive film .
And a drain terminal metal part. 2. A thin film transistor comprising a gate line, a gate electrode formed on the gate line, a gate insulating film, an i-type semiconductor layer, an n-type semiconductor layer, and a source / drain electrode on a substrate; In a method for manufacturing a thin film transistor panel, comprising: a drain line connected to a drain electrode; a pixel electrode connected to a source electrode of the thin film transistor; and a protective insulating film covering the thin film transistor and the drain line, a metal film for a gate is formed on the substrate. Forming a gate line and a gate electrode by patterning the metal film; and forming a gate insulating film, an i-type semiconductor layer, and an n-type semiconductor on the substrate so as to cover the gate line and the gate electrode. A second step of sequentially forming a layer and a source and drain metal film; A third step of patterning the source / drain metal film, the n-type semiconductor layer, and the i-type semiconductor layer into a shape of a drain line and an outer shape of a transistor element region; Forming a transparent conductive film covering the source and drain metal films;
Step 4 and patterning the transparent conductive film into the shapes of a pixel electrode, a source electrode, a drain electrode and a drain line, and using the resist mask used for patterning the transparent conductive film to form the transparent conductive film in the transistor element region. A fifth step of separating the source and drain metal films into a source electrode portion and a drain electrode portion, and anodizing the n-type semiconductor layer while leaving the resist mask used for patterning the transparent conductive film. A sixth step of forming a portion between the source and drain electrodes of the n-type semiconductor layer as an oxide insulating layer, a seventh step of forming a protective insulating film, and a step of forming the protective insulating film on a pixel electrode. And a pattern in which the terminal portions of the drain line and the terminal portion of the gate line have been removed, Eighth step and method of manufacturing a thin film transistor panel, comprising the removal of part of the down terminal portions.