JP3112870B2 - DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM, and more particularly, to a DRAM having a function of testing a hold characteristic of a DRAM memory cell.

[0002]

2. Description of the Related Art Conventionally, a DRAM of this type has a memory cell array comprising transistors and capacitors arranged in rows and columns, a memory cell array section which is selected by a signal of each word line and which inputs / outputs each data line. Each word line drive circuit for driving each word line of the section. FIG. 10 is a circuit diagram showing a general configuration example of each word line drive circuit in this conventional DRAM.

The conventional word line driving circuit C includes an inverter circuit A composed of a P-channel transistor 1 and an N-channel transistor 2, a buffer circuit B composed of N-channel transistors 3, 4, 5 and an inverter 6. It consists of. Inverter circuit A
Is controlled by a control signal I10 corresponding to a change in an address signal, is supplied with an output potential by a word line high potential supply node VA and a word line low potential supply node GA, and has its output connected to a node N1. Also, the buffer circuit B
Is controlled by a control signal I20 corresponding to an address signal, is supplied with an output potential by a node N1 and a word line low potential supply node GB, and connects its output to a word line W0. The control signals I10, I
The word line signal selectively activated by 20 is amplified to the supply potential of the word line high potential supply node VA or the word line low potential supply nodes GA and GB to drive the word line W0.

FIG. 11 is a timing chart showing an operation example of the word line drive circuit C.

First, a low potential is applied to the control signal I20 as in a period a shown in FIG. At this time, the node N2 becomes low potential, the N-channel transistor 4 becomes non-conductive, the node N3 becomes high potential, and the N-channel transistor 5 becomes conductive. Therefore, the ground potential is supplied to the word line W0 from the ground line connected to the word line low potential supply node GB.

Next, as in a period b shown in FIG. 11, a high potential is applied to the control signal I10, the P-channel transistor 1 is turned off, and the N-channel transistor 2 is turned on. In the state where the ground potential is supplied from the ground line connected to the word line low potential supply node GA,
A high potential is applied to the control signal I20. At this time, the node N2
Becomes high potential, the N-channel transistor 4 becomes conductive, the node N3 becomes low potential, and the N-channel transistor 5 becomes non-conductive. Therefore, the node N is connected to the word line W0.
1 is supplied with the ground potential.

Next, as in a period c shown in FIG. 11, a low potential is applied to the control signal I10 from the state in the period b. At this time, the P-channel transistor 1 is turned on, the N-channel transistor 2 is turned off, and a high potential is supplied to the node N1 from the high potential line VDD connected to the high potential supply node VA. Therefore, the high potential of the high potential line VDD supplied to the node N1 is supplied to the word line W0.

In a transition state where the word line W0 transitions from a low potential to a high potential, the potential at the node N2 is boosted via the gate capacitance of the N-channel transistor 4. At this time, the potential of the node N2 is changed from the high potential supplied to the node N1 to the word line W via the N-channel transistor 4.
A potential is reached that is sufficient to transfer to zero. When the potential of the node N2 is boosted, the potentials of the gate, drain and source of the N-channel transistor 3 are both high, the N-channel transistor 3 is turned off, and the boosted potential of the node N2 is While the control signal I20 is at the high potential, the potential is determined independently of the potential of the control signal I20.

The word line drive circuit C having the above-described configuration and operation is connected to the other word lines of the memory cell array section similarly to the word line W0, although the control signals are different. For example, FIG.
FIG. 4 is a block diagram showing a connection configuration example of a memory cell array unit and each word line drive circuit C, C1, C2, C3 in M.

Referring to FIG. 12, memory cell M00
Is configured by connecting an N-channel transistor T00 and a capacitor C00 at a node Z00. Similarly, the memory cells M01 to M13 are connected to the N-channel transistor T0.
1 to T31 and capacitors C01 to C13 are connected to nodes Z01 to Z1.
3 are connected. The electric charge stored in the capacitance constituting the memory cell, that is, the node Z0
The potentials of 0 to Z13 become data of the memory cell.

The memory cell M00 is connected to the word line W0.
Similarly, the memory cells M01 to M13 are connected to the word lines W0 to W3 and the data line pairs D0 and D0B or the data line pairs D1 and D1B. ing. These data line pairs D0, D0B and D1, D1B are connected to differential amplifiers S0 and S1, respectively.

The combinations of word lines and data line pairs to which the memory cells M00 to M13 are connected are differently connected to each of the memory cells. That is, if the word line and the differential amplifier corresponding to the data line pair are specified, the memory cell can be specified. For example, the memory cell M00 is specified by the word line W0 and the differential amplifier S0.

Next, with reference to FIG. 12, a description will be given of a test of a hold characteristic of a memory cell in a conventional DRAM.

In general, when reading data from a memory cell to a data line or writing data to a memory cell in a DRAM, a word line connected to the memory cell is set to a high potential to form N
Make the channel transistor conductive. When data of a memory cell is to be held, the word line connected to the memory cell is set to a low potential, and N
Turn off the channel transistor.

However, when the word line W0 transitions from the low potential to the high potential, the word line W0 adjacent to the word line W0
The potential of 1 becomes higher than the low potential supplied from the word line driving circuit C1 due to coupling noise generated via the parasitic capacitance P01.

For this reason, the charge stored in the capacitor constituting the memory cell in which the connected word line is held at a low potential is gradually reduced by the weak inversion current of the N-channel transistor constituting the memory cell. After a period of time, called the hold characteristic of the memory cell,
Eventually, it will be reduced to an amount that cannot be read.

The weak inversion current of the N-channel transistor, which deteriorates the hold characteristics of the memory cell, increases as the gate voltage of the N-channel transistor increases. and,
When the word line W0 transitions from the low potential to the high potential, the word line W1 has a potential higher than the low potential supplied from the word line driving circuit C1, and the hold characteristics of the memory cell connected to the word line W1 are The worse the number of times the word line W0 transitions from a low potential to a high potential, the worse.

Therefore, in accurately testing the hold characteristics of the memory cell connected to the word line W1,
During the data retention time of the memory cell, the word line W
It is necessary to continuously change 0 from a low potential to a high potential.

Since the parasitic capacitances P01, P13, and P32 exist between adjacent word lines, to test the hold characteristics of the memory cells in the entire memory cell array,
It is necessary to continuously change all the word lines while sequentially changing the word lines that continuously transition from the low potential to the high potential to the word lines W0, W1, W2, and W3.

[0020]

As described above, a problem with the DRAM having the conventional word line drive circuit is that it takes a very long time to test the hold characteristics of the memory cells.

The reason is that, in order to test the hold characteristics of the memory cells in the entire memory cell array section, it is necessary to perform an operation of continuously transitioning the word lines for each word line during the data holding time of the memory cells. Because there is.

For example, the test time of the DRAM hold characteristic in which the number of word lines is 4096 and the data retention time of the memory cell is 32 milliseconds is 32 milliseconds × 4096 even if only the data retention time included in the test time is included. = 13
One second.

Accordingly, an object of the present invention is to reduce the test time and test cost of a DRAM, and furthermore to provide a DRA.
M to improve productivity.

[0024]

Accordingly, the present invention provides a memory cell array section comprising a plurality of memory cells arranged in rows and columns, which is selected by a signal of each word line and input / output by each data line, an address signal and its address signal. An arbitrary set potential is generated in a DRAM including a word line drive circuit for amplifying each word line signal selectively activated in response to a change to a higher or lower supply potential and driving each word line. And setting means for switching from a power supply terminal potential or a ground terminal potential to the set potential during a test operation and outputting the set potential as the supply potential of each word line drive circuit.

Further, the switching means includes two transistors which are conductive or non-conductive in a complementary manner in response to a test signal indicating a test operation, and wherein the power supply terminal potential or the ground terminal potential and the set potential are set. The switching outputs the supply potential.

The setting means comprises an external terminal for inputting the set potential.

Further, the setting means comprises a voltage source for internally generating the set potential corresponding to the voltage of an external terminal.

Further, another external terminal for inputting the test signal is provided.

[0029]

Next, the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of a DRAM of the present invention.
FIG. 3 is a circuit diagram showing a word line driving circuit and its peripheral portion in FIG.

Referring to FIG. 1, the DRAM of the present embodiment
The word line driving circuit and its peripheral portion in FIG. 1 are provided with setting means E and switching means D in addition to the word line driving circuit C.

The word line drive circuit C according to the present embodiment is similar to that of FIG.
0 in the conventional DRAM shown in FIG.
The only difference is that the supply potential of the word line low potential supply node GB is supplied from the output of the switching means D instead of the ground potential. The internal configuration is the same, and control signals I20 and I1 corresponding to the address signal and its change are provided.
The word line signal selectively activated by 0 is supplied to the word line high potential supply node VA or the word line low potential supply node G.
Amplify to the supply potential of B and drive word line W0. Therefore, redundant description of the internal configuration will be omitted.

The setting means E comprises an external terminal for externally inputting an arbitrary set potential and outputting it to the potential supply node I of the switching means D.

The switching means D includes N-channel transistors 7, 8 and an inverter 9. In the N-channel transistor 7, the source and the drain are connected to the word line low potential supply node GB and the ground, and the gate is connected to the node N4.
The N-channel transistor 8 has a source and a drain connected to the word line low potential supply node GB and the potential supply node I, and a node N5 for inputting a test signal T indicating a test operation is connected to the gate. Further, the inverter 9 outputs the test signal T
And outputs the inverted signal to the node N4. The transistors 7 and 8 switch from the ground terminal potential to the set potential of the external terminal and output the supply potential to the word line low potential supply node GB of the word line drive circuit C during the test operation.

FIG. 2 is a timing chart showing an example of the operation of the word line drive circuit C and its peripheral parts.

Referring to FIG. 1, when the test signal T is at a low potential, the high potential and the low potential are supplied to the nodes N4 and N5, respectively, and the transistors 7 and 8 become conductive and non-conductive, respectively, and the word line low potential is provided. The ground potential is supplied to the supply node GB. Therefore, at this time, the word line drive circuit C performs the same operation as the conventional word line drive circuit shown in FIG.

First, when a low potential is applied to the control signal I20 as in the period a shown in FIG. 2, the nodes N2 and N3 become low potential and high potential, and the N-channel transistors 4, 5
Becomes non-conductive and conductive. Therefore, at this time, the word line W
The ground potential supplied to the word line low potential supply node GB is supplied to 0.

Next, when the test signal T is set to a high potential as in the period b shown in FIG. 2, the nodes N4 and N5 are set to a low potential and a high potential, and the N-channel transistors 7 and 8 are turned off. It becomes conductive, and the potential of the external terminal J is supplied to the word line low potential supply node GB via the potential supply node I. Therefore, an arbitrary potential can be supplied to the word line W0 by the potential of the external terminal J.

The word line driving circuit C having the above-described configuration and operation is connected to other word lines of the memory cell array section, similarly to the word line W0, although the control signals are different. The switching means D and the setting means E, which are peripheral portions of the word line driving circuit C, may be provided for each word line driving circuit, or may be shared by a plurality of word line driving circuits. For example, FIG. 3 shows a memory cell array section and each word line drive circuit C, C in the DRAM of this embodiment.
FIG. 3 is a block diagram showing an example of a connection configuration between the first, C2, and C3 and peripheral portions thereof. Referring to FIG. 3, except for each word line drive circuit and its peripheral portion shown in FIG. 1, it is the same as the connection configuration example in the conventional DRAM shown in FIG.
A duplicate description is omitted.

Next, the test operation of the hold characteristic of the memory cell in the DRAM of this embodiment will be described with reference to the drawings. FIG. 4 is a time chart illustrating an example of a test operation of a hold characteristic of a memory cell in the DRAM of the present embodiment.

First, a high potential is written to the memory cells M00 to M13, and the node Z00 is set as shown in the period a shown in FIG.
To Z13 are set to a high potential.

Next, as in a period b shown in FIG. 4, the test signal T is set to a high potential, and the control signals I10 to I13, I
An arbitrary low potential is supplied to each of the word lines W0 to W3 controlled by 20 to I23. At this time, nodes Z00 to Z13
Of the N-channel transistors T00 to T13 gradually decrease due to a weak inversion current or the like. By holding this state during the data holding time of the memory cell, a test of the hold characteristics of the memory cell is performed.

During the data holding time of the memory cell, the word lines W0 to W3 are set as shown in the period c shown in FIG.
May be varied. Further, as in the period d shown in FIG. 4, the differential amplifiers S0 and S1 are activated, and the data line pair D0 and D0B and the data line pair D1 and D1 are activated.
A high potential and a low potential are applied to D1B, and a write operation is performed as in a period e shown in FIG.
B and the potential of the data line pair D1 and D1B may be set.
By supplying a low potential higher than the ground potential to the word lines W0 to W3 during these periods, the weak inversion currents of the N-channel transistors T00 to T13 increase, and when testing the hold characteristics of the memory cells, An increase in the potential of the word line of interest due to the coupling noise of the adjacent word line can be reproduced in a pseudo manner without causing a continuous transition of the word line.

Further, one or more DRs are used in the test method of the DRAM of the present embodiment and the conventional test method.
The hold characteristics of the AM memory cell were evaluated in advance and 2
The test can be shortened by correlating the hold characteristics of the memory cells obtained by the two test methods. That is, if the low potential supplied to the word lines W0 to W3 is made higher, N
Since the weak inversion current of the channel transistors T00 to T13 further increases, for example, the hold characteristic of the memory cell obtained by the test method in the DRAM of the present embodiment is 1 / n of the hold characteristic of the memory cell obtained by the conventional test method. (N is a positive real number) so that the word lines W0 to W0
Any low potential can be supplied to W3.

As is apparent from the above description, in the DRAM of this embodiment, it is not necessary to perform the operation of continuously transitioning the word line for each word line during the data holding time of the memory cell. Since the data retention time of the memory cell can be reduced to 1 / n while maintaining the correlation with the method, the test time of the hold characteristic of the memory cell can be significantly reduced.

In the test of the hold characteristics of the memory cells in the DRAM of this embodiment, as described above, all the word lines W0 to W3 can be simultaneously subjected to the test of the hold characteristics of the memory cells. However, the DR of this embodiment
As a modified example of the AM, a word line group that simultaneously supplies an arbitrary potential may be divided into k (k is a natural number), and the test may be performed k times. At this time, in the case of the DRAM having the memory cell data holding time tREF, the data holding time included in the test time of the hold characteristics of the memory cells of the entire memory cell array is (tREF ÷ n × k). For example,
When the data holding time tREF of the memory cell is 32 milliseconds and the correlation coefficient is 1 / n, and the word line group k is 1/2 and 2, the data included in the test time of the hold characteristic of the memory cell of the entire memory cell array is obtained. The holding time is 32 milliseconds / 2 × 2 = 32 milliseconds from about 131 seconds of the prior art, and the effect is very large.

Further, as a ripple effect of the DRAM of this embodiment, the threshold value of each of the transistors constituting the memory cell can be measured. This threshold value measuring method will be described next.

FIG. 5 is a timing chart showing an example of threshold value measurement in the DRAM of this embodiment.

First, a high potential is written to the memory cell M00, and the node Z00 is set to a high potential as in a period a shown in FIG.

Next, as in a period b shown in FIG. 5A, the test signal T is set to a high potential and the control signals I10 to I10 are set.
13, each word line W0-W controlled by I20-I23
3 is supplied with an arbitrary low potential. At this time, an arbitrary potential may be supplied to the word lines W1 to W3 which are not considered.

Next, the differential amplifier S0 is activated as in a period c shown in FIG. 5A, and a write operation is performed as in a period d shown in FIG. Line D0,
A ground potential and a high potential are supplied to D0B. At this time, if the difference potential between the low potential supplied to the word line W0 and the ground potential supplied to the data line, that is, the low potential supplied to the word line W0 is smaller than the threshold value of the N-channel transistor T00, the N-channel transistor T00 Is non-conductive,
Although the potential of the node Z00 gradually decreases due to the weak inversion current of the N-channel transistor T00, etc., FIG.
As in the period d shown in FIG. 7A, a high potential required for reading is held.

However, if the low potential supplied to the word line W0 is larger than the threshold value of the N-channel transistor T00, the N-channel transistor T00 becomes conductive, and FIG.
As in the period e shown in (B), the ground potential supplied to the data line D0 is supplied to the node Z00, and the node Z00
The fact that 00 has become the ground potential can be known by reading data from the memory cell M00.

Therefore, the data reading of the memory cell M00 is repeated by changing the low potential supplied to the word line from the potential at which the node Z00 holds the high potential to the ground potential at any step, thereby obtaining the memory. Cell M0
It is possible to know the threshold value of the N-channel transistor T00 constituting 0. Further, by performing the same measurement for all the memory cells, the threshold value of the transistor forming the memory cell can be measured for each memory cell.

FIG. 6 is a circuit diagram showing a word line drive circuit and its peripheral portion in a second embodiment of the DRAM of the present invention.

Referring to FIG. 6, the DRAM of the present embodiment
1 includes a setting means E and a switching means D in addition to the word line driving circuit C, similarly to the DRAM of the first embodiment shown in FIG.

The word line drive circuit C according to the present embodiment is similar to that of FIG.
As compared with the word line drive circuit in the DRAM of the first embodiment, the supply potential of the word line high potential supply node VA is supplied from the output of the switching means D instead of the power supply terminal potential, and the word line low potential supply node GB is grounded. Only the differences.
Its internal configuration is the same, and control signals I20, I1
The word line signal selectively activated by 0 is supplied to the word line high potential supply node VA or the word line low potential supply node G.
Amplify to the supply potential of B and drive word line W0. Therefore, redundant description of the internal configuration will be omitted.

The setting means E is the DRA of the first embodiment shown in FIG.
Like M, an external terminal for externally inputting an arbitrary set potential and outputting it to the potential supply node I of the switching means D.

The switching means D includes a P-channel transistor 1
A 0, N-channel transistor 11 is provided. In the P-channel transistor 10, the source and the drain are connected to the word line high potential supply node VA and the power supply terminal VDD, and the gate is connected to the node N6 to which the test signal T is input. In the N-channel transistor 11, the source and the drain are connected to the word line high potential supply node VA and the potential supply node I, and the gate is connected to the node N6. The transistors 10 and 11 switch from the power supply terminal potential to the set potential of the external terminal and output the supply potential to the word line high potential supply node VA of the word line drive circuit C during the test operation.

FIG. 7 is a timing chart showing an example of the operation of the word line drive circuit C and its peripheral parts.

Referring to FIG. 7, when test signal T is at a low potential, a low potential is supplied to node N6, P-channel transistor 10 and N-channel transistor 11 are turned on and off, and the word line high-potential supply node is turned on. A power supply terminal potential is supplied to VA. Therefore, at this time, the word line drive circuit C performs the same operation as the conventional word line drive circuit shown in FIG.

First, when the test signal T is set to a high potential as in the period a shown in FIG. 7, the node N6 is set to a high potential,
P-channel transistor 10, N-channel transistor 1
1 is non-conductive and conductive, and the word line high potential supply node VA
Is supplied with the potential of the external terminal J via the potential supply node I.

Next, when a high potential is applied to the control signal I20 and a low potential is applied to the control signal I10 as in a period b shown in FIG. 7, the nodes N2 and N3 become high potential and low potential, respectively. The channel transistors 4 and 5 become conductive and non-conductive,
P-channel transistor 1, N-channel transistor 2
Becomes conductive and non-conductive. Therefore, the word line W0
The potential of the external terminal J is supplied via the node N1 and the word line high potential supply node VA. Therefore, the word line W0
Can be supplied with an arbitrary potential depending on the potential of the external terminal J.

FIG. 8 is a circuit diagram showing a word line drive circuit and its peripheral portion in a third embodiment of the DRAM of the present invention.

Referring to FIG. 8, the DRAM of this embodiment is
1 includes a setting means E and a switching means D in addition to the word line driving circuit C, similarly to the DRAM of the first embodiment shown in FIG.

The word line drive circuit C according to the present embodiment is similar to the one shown in FIG.
Compared with the word line drive circuit in the DRAM of the first embodiment, the supply potential of the word line low potential supply node GA is supplied not from the ground potential but from the output of the switching means D, and the word line low potential supply node GB is grounded. Only the point is different. The internal configuration is the same, and a word line signal selectively activated by an address signal and control signals I20 and I10 corresponding to the change is applied to a word line high potential supply node V.
A is amplified to the supply potential of A or the word line low potential supply node GA, and the word line W0 is driven. Therefore, redundant description of the internal configuration will be omitted.

The setting means E comprises a voltage source H for internally generating a set potential corresponding to the voltage of the external terminal J.

The switching means D corresponds to the DRA of the first embodiment shown in FIG.
This is the same as the switching means D in M, and redundant description will be omitted.

FIG. 9 is a timing chart showing an example of the operation of the word line drive circuit C and its peripheral parts.

When the test signal T is at a low potential, each node N
4, N5 are supplied with a high potential and a low potential, the N-channel transistors 7, 8 are turned on and off, and the ground potential is supplied to the word line low potential supply node GA. Therefore, at this time, the word line drive circuit C performs the same operation as the conventional word line drive circuit shown in FIG.

First, when a high potential is applied to the test signal T as in a period a shown in FIG. 9, a low potential and a high potential are supplied to the nodes N4 and N5, and the N-channel transistors 7 and
8 is nonconductive and conductive, and the word line low potential supply node GA
Is supplied with an output potential of a voltage source H that internally generates a set potential corresponding to the voltage of the external terminal J via a potential supply node I.

Next, when a high potential is applied to both the control signals I20 and I10 as in the period b shown in FIG.
2, N3 become high potential and low potential, the N-channel transistors 4 and 5 become conductive and non-conductive, and the P-channel transistor 1 and N-channel transistor 2 become non-conductive and conductive. Therefore, the output potential of the voltage source H that internally generates the set potential corresponding to the voltage of the external terminal J is supplied to the word line W0 via the node N1 and the low potential supply node GA. Therefore, an arbitrary potential can be supplied to the word line W0 by the potential of the external terminal J.

Also in the above-described DRAMs of the second and third embodiments, the test operation of the hold characteristic of the memory cell described in the first embodiment and the measurement of the threshold value of each of the transistors constituting the memory cell can be realized. it is obvious.

[0072]

The effect of the present invention is that the test of the hold characteristic of the memory cell of the DRAM can be performed in a short time, and the cost of the DRAM test can be reduced. Also, D
The number of DRAMs that can be tested in a limited amount of time with a limited amount of equipment for testing the RAM increases the number of DRAMs, thereby improving the DRAM productivity.

The reason is that, when testing the hold characteristics of the memory cell, an arbitrary potential can be supplied to the word line during the data retention time of the memory cell, and the correlation with the conventional test method can be strongly maintained. It is.

Further, as a ripple effect according to the present invention, there is an effect that a threshold value of a transistor constituting a memory cell can be measured for each memory cell.

The reason is that an arbitrary potential can be supplied to the word line.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a word line drive circuit and a peripheral portion thereof in a first embodiment of a DRAM of the present invention.

FIG. 2 is a time chart showing an operation example of the word line drive circuit of FIG. 1 and its peripheral portion.

FIG. 3 is a block diagram illustrating a connection configuration example in a DRAM according to the first embodiment;

FIG. 4 is a time chart illustrating a test operation example of a hold characteristic of a memory cell in the DRAM of the first embodiment.

FIG. 5 is a timing chart showing an example of threshold measurement in the DRAM of the first embodiment.

FIG. 6 is a circuit diagram showing a word line driving circuit and a peripheral portion thereof according to a second embodiment of the DRAM of the present invention;

7 is a timing chart showing an operation example of the word line drive circuit of FIG. 6 and its peripheral portion.

FIG. 8 is a circuit diagram showing a word line drive circuit and a peripheral portion thereof according to a third embodiment of the DRAM of the present invention.

FIG. 9 is a timing chart showing an operation example of the word line drive circuit of FIG. 8 and its peripheral portion.

FIG. 10 is a circuit diagram showing a word line drive circuit in a conventional DRAM.

11 is a timing chart showing an operation example of the word line drive circuit of FIG.

FIG. 12 is a block diagram showing a connection configuration example in a conventional DRAM.

[Explanation of symbols]

1,10 P-channel transistor 2-5,7,8,11, T00-T13 N-channel transistor 6,9 Inverter a-e period A Inverter circuit B Buffer circuit C, C1, C2, C3 Word line drive circuit C00-C13 Capacitance D Switching means D0, D0B, D1, D1B Data line E Setting means GA, GB Word line low potential supply node H Voltage source I Potential supply node I10-I23 Control signal J External terminal M00-M13 Memory cells N1-N6, Z00 To Z13 Nodes P01, P13, P32 Parasitic capacitance S0, S1 Differential amplifier T Test signal VA Word line high potential supply node W0 to W3 Word line

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-199298 (JP, A) JP-A-10-269800 (JP, A) JP-A-10-247398 (JP, A) JP-A-10-199 340597 (JP, A) JP-A-6-176598 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 11/407 G11C 11/401

Claims (5)

(57) [Claims] 1. A memory cell array section comprising a plurality of memory cells arranged in rows and columns, each row being selected by a signal of each word line and inputting / outputting by each data line, and selectively controlling activation according to an address signal and its change. Including a word line drive circuit for amplifying each word line signal to a higher or lower supply potential and driving each word line
, A setting means for generating an arbitrary set potential, and a switching means for switching from a power supply terminal potential or a ground terminal potential to the set potential during a test operation and outputting the set potential as the supply potential of each word line drive circuit. DRAM. 2. The switching means includes two transistors that are conductive or non-conductive in a complementary manner in response to a test signal indicating a test operation, and that sets the power supply terminal potential or the ground terminal potential and the set potential. 2. The DRAM according to claim 1, wherein the switching outputs the supply potential. 3. The DRA according to claim 1, wherein said setting means comprises an external terminal for inputting said set potential.
M. 4. The DRAM according to claim 1, wherein said setting means comprises a voltage source for internally generating said set potential corresponding to a voltage of an external terminal. 5. The DRAM according to claim 2, further comprising another external terminal for inputting said test signal.