JP3107968B2 - NRZ-RZ signal conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conversion circuit for converting an NRZ signal into an RZ signal used in a demodulation circuit for asynchronous digital communication, and more particularly, to a conversion circuit capable of stably converting an RZ signal into an RZ signal. .

[0002]

2. Description of the Related Art In a radio communication, an NRZ (Nonreturn to Zero) signal, which has a small harmonic component and is advantageous in terms of a required bandwidth when modulated, is used as a transmission code.
In transmission of a baseband signal, an RZ (Return to Zero) code is widely used from the viewpoint of easy synchronization. Therefore, in the demodulation circuit of the receiver, an operation for converting the NRZ signal into the RZ signal is required.

A conventional NRZ-RZ signal conversion circuit is shown in FIG.
As shown in FIG. 5, when the NRZ signal 8 including jitter is input, a D flip-flop 13 that outputs the signal delayed by one clock of the clock signal 10, a two-input AND gate 14 that detects the rising of the NRZ signal 8, A two-input NOR gate 15 that outputs a load signal of the counter 16, a 4-bit loadable counter 16 that starts counting up from the loaded value, and a counter 16 that outputs a middle value corresponding to the data 1 of the NRZ signal. A D flip-flop 17 for inverting the signal level only after counting and counting the highest numerical value and outputting the RZ signal 12 is provided.

The NRZ signal 8 including the jitter is an NRZ signal demodulated from a signal of asynchronous communication, and is synchronized with the clock signal 10 in a state including a temporal expansion or contraction of about one to two cycles of the clock signal 10. ing. On the other hand, the NRZ signal obtained by demodulating the signal of the synchronous communication is 8
The signal has a cycle interval of one unit, and does not include any temporal expansion or contraction.

The NRZ signal 8 including jitter indicates LOW in a steady state, and at this time, the reset signal 9 of the 4-bit loadable counter 16 is also LOW. When an NRZ signal 8 including jitter is input, this data must be 1
, One of the inputs of the two-input AND gate 14 becomes HIGH. The output NQ of the D flip-flop 13 input to the other of the two-input AND gate 14 is HIGH until the next clock signal 10 is input to the D flip-flop 13.
Is maintained, the two-input AND gate 14 detects the first rising edge of the NRZ signal 8 including the jitter during one cycle of the clock signal and outputs HIGH. At the same time, the reset signal 9 becomes HIGH and the loadable counter
Operation 16 starts.

The RCO of the loadable counter 16 at this time is
Is in a LOW state. The output of the two-input NOR gate 15 changes from the HIGH state so far to LOW for one cycle of the clock signal 10 due to the detection of the rise of the NRZ signal 8 including jitter, and returns to HIGH.
Therefore, the input to the LOAD terminal of the loadable counter 16 becomes LOW for one cycle, and the output of the loadable counter 16 includes (Q ₃ , Q ₂ , Q ₁ , Q ₀ ) = (1, 0, 0,
0) is loaded.

The loadable counter 16 starts from the loaded value and sequentially (1, 0, 0, 1) (1, 0, 1, 0) (1, 0, 1, 1) at the rising edge of the clock signal 10.
1) (1,1,0,0) (1,1,0,1) (1,1,
(1,0) (1,1,1,1). At this time, (1, 0, 0, 0) (1, 0, 0, 1) (1,
0,1,0) (1,0,1,1) until the output Q ₂ of the loadable counter 16 LOW, D flip-flop
Since the input to the CLK terminal 17 remains LOW, D
The NQ output of the flip-flop 17 is HIGH. When the count of the loadable counter 16 is (Q ₃ , Q ₂ ,
When Q ₁ , Q ₀ ) = ( ₁ , ₁ , ₀ , ₀ ), the output Q ₂
Becomes HIGH is started, D flip-flop 17 at the rising edge output Q ₂ of the loadable counter 16 samples the NRZ signal 8 including jitter, the output of the D flip-flop 17 changes from HIGH to LOW. This timing basically samples the center of the NRZ signal whose signal unit is eight periods of the clock signal 10.

The loadable counter 16 continues counting up at the rising edge of the clock signal 10, and (Q
₃ , Q ₂ , Q ₁ , Q ₀ ) = ( ₁ , ₁ , ₁ , ₁ ), and at the same time, the RCO is set to L for one cycle of the clock signal 10.
Change from OW to HIGH. This RCO output is a 2-input N
Input to OR gate 15. At this time, NR including jitter
The Z signal 8 indicates whether the next data is 1 or 0,
Since there is no change from LOW to HIGH, the output of the two-input AND gate 14 maintains the LOW state.
Therefore, the two-input NOR gate 15 changes the high level of the clock signal 10 from the high level by the RCO output.
It goes LOW only during the period and returns to HIGH.

The output of the two-input NOR gate 15 is applied to the LOAD terminal of the loadable counter 16, and (Q ₃ , Q ₂ , Q ₁ , Q ₀ ) = (1,
(0,0,0) is loaded. That is, the outputs (Q ₃ , Q ₂ , Q ₁ , Q ₀ ) of the loadable counter 16 are (1, 1, 1).
(1,1) is replaced by (1,0,0,0).

The output of the D flip-flop 17 is 2
When the output of the input NOR gate 15 becomes LOW, an asynchronous reset is applied, and the output returns to HIGH.

Subsequently, the loadable counter 16 counts up at the rising edge of the clock signal 10 as before, and the D flip-flop 17
16 when the output Q ₂ becomes HIGH, samples the center of the NRZ signal 8 including jitter. If the sampled data is 0, that is, LOW, the D flip-flop 17
Output remains HIGH, and if the sampled data is 1, that is, HIGH, the output of the D flip-flop 17 becomes LOW. The loadable counter 16 continues counting up, and when counting to the highest number, RC
O becomes HIGH for one cycle of the clock signal 10, and the output of the two-input NOR gate 15 becomes LO for one cycle of the clock signal 10.
W. Therefore, the D flip-flop 17 is asynchronously reset, and the output becomes HIGH. By such a series of operations, the D flip-flop 17 outputs the RZ signal.
12 is output.

The output of the loadable counter 16 (Q ₃ , Q
₂ , Q ₁ , Q ₀ ) are basically counted up from ( ₁ , ₀ , ₀ , ₀ ) to (1, 1, 1, 1), and (1, 1, 1, 1)
After (1,1,1), (1,0,0,0) is loaded. However, when the D flip-flop 13 and the two-input AND gate 14 detect the rise of the NRZ signal 8 including jitter, the two-input NOR gate 15 immediately sends the clock signal 10 to the LOAD terminal of the loadable counter 16. A LOW signal is input during the period, and (1, 0, 0, 0) is loaded. That is, regardless of the state of the output (Q ₃ , Q ₂ , Q ₁ , Q ₀ ), when the NRZ signal 8 is input, the loadable counter 16 outputs the output (1,
(0,0,0). Therefore, even when the input NRZ signal 8 includes jitter, it can be converted into an RZ signal while synchronizing with the clock signal 10.

[0013]

However, the conventional NRZ
-The RZ signal conversion circuit extracts the RZ signal from the D flip-flop 17 which does not receive the clock signal,
The rise of the RZ signal 12 from LOW to HIGH is controlled by the reset signal of the D flip-flop 17.
Therefore, the obtained RZ signal 12 becomes asynchronous with respect to the clock signal 10, and the operation of signal conversion lacks stability,
Or a signal delay occurs. As a result, this conversion circuit has a problem that high-speed communication cannot be performed or a malfunction occurs in a severe vehicle environment.

The present invention solves such a conventional problem, and can convert an NRZ signal including jitter into an RZ signal completely synchronized with a clock signal.
An object of the present invention is to provide an NRZ-RZ signal conversion circuit capable of performing stable high-speed operation.

[0015]

Therefore, according to the present invention, an NRZ signal including jitter and a clock signal are input and
A rising differential circuit that outputs a rising differential signal of the RZ signal in synchronization with the clock signal, and receives the rising differential signal and the clock signal as inputs, resets the synchronous differential signal in synchronization with the clock signal, and synchronizes with the clock signal. An n-ary counter that counts up
A decoder which receives an output of a binary counter as an input and outputs a decoded signal of an output of an n-ary counter,
A two-input AND gate receiving the RZ signal, a D flip-flop receiving the output of the two-input AND gate and the clock signal, and receiving the output of the D flip-flop and the clock signal as input and synchronizing with the clock signal RZ
An NRZ-RZ signal conversion circuit is constituted by a sequencer that outputs a signal.

[0016]

Therefore, when the NRZ signal rises, the n-ary counter receiving the output of the rising differentiating circuit starts counting up in synchronization with the clock signal, and when the count reaches a predetermined number, the decoder changes the decode signal to two. Input AND
Output to the gate. The two-input AND gate outputs a signal for sampling using the decode signal, and the D flip-flop synchronizes the output of the two-input AND gate with the clock signal. The output of the D flip-flop enters the sequencer, and the sequencer inverts the output signal for the period of the clock signal set in the program after the output of the D flip-flop. Therefore, the sequencer outputs an RZ signal completely synchronized with the clock signal.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, an NRZ-RZ signal conversion circuit according to an embodiment of the present invention comprises a rising differential circuit 1 for outputting a rising differential signal 7 of an NRZ signal 8 including jitter in synchronization with a clock signal 10. , Reset asynchronously with the clock signal 10 by the reset signal 9,
The clock signal 10 is generated by the rising differential signal 7 of the RZ signal 8.
Octal counter 2 reset in synchronism with the above, a decoder 3 for decoding the output of the octal counter 2, and a two-input AN for generating a signal for sampling the NRZ signal 8 including jitter
A D-gate 4, a D-flip-flop 5 for synchronizing the output of the two-input AND gate 4 with the clock signal 10, and a program for receiving the output of the D-flip-flop 5 and outputting an RZ signal 11 synchronized with the clock signal 10 And an operating sequencer 6.

Next, the operation of the NRZ-RZ signal conversion circuit of the embodiment will be described. FIG. 2 shows a timing chart of each part of the conversion circuit of the embodiment. In this figure, the solid line of the NRZ signal 8 (b) shows the case where the NRZ signal is synchronized with the clock signal 10 (a), and the dotted line shows the time of about 1 to 2 periods of the clock signal 10. The “NRZ signal including jitter” which is synchronized with the clock signal 10 including the expansion and contraction is shown. Synchronous communication signal N
When demodulated to an RZ signal, it becomes a solid line, and the unit of the signal is eight periods of the clock signal 10.

At the input timing (b) of the NRZ signal 8 including the jitter, the reset signal 9 is input as shown in FIG. Octal counter 2
2 shows the case of an NRZ signal containing no jitter in d1 of FIG. 2 and the case of an NRZ signal containing jitter in d2 of FIG. In any case, counting from 0 is started in accordance with the clock signal a following the output signal 7 (c) of the rising differentiating circuit. In the case of an NRZ signal containing no jitter, the count from 0 to 7 is repeated regularly, but in the case of an NRZ signal 8 containing jitter, the time position of the output signal 7 (c) of the rising differentiating circuit deviates from the solid line.
The count number is irregular accordingly.

The decoder 3 receives the output of the octal counter 2 and outputs HIGH (FIG. 2e) when the output of the octal counter 2 is 3.

The two-input AND gate 4 inputs the output (e) of the decoder 3 and the NRZ signal 8 (b) including jitter. When the output of the decoder 3 is HIGH and the data of the NRZ signal 8 is 1, Only for one cycle of the clock signal 10
An IGH signal (FIG. 2f) is output. If the NRZ signal contains jitter, it becomes like a dotted line. The two-input AND gate 4 uses the output of the decoder 3 to output an NR including jitter.
The Z signal 8 is sampled.

The D flip-flop 5 receives the output of the two-input AND gate 4 and the clock signal 10, synchronizes the output of the two-input AND gate 4 with the clock signal 10,
The signal of FIG. 2g is output.

The sequencer 6 performs an operation based on the state transition diagram shown in FIG. 3 according to a program. That is, D
The output of flip-flop 5 (FIG. 2g) is clock signal 10
Is LOW for one cycle of H.
Outputs IGH. On the other hand, when the output of the D flip-flop 5 is HIGH for one period of the clock signal 10, the output of the RZ signal synchronized with the clock signal 10 is changed to LOW.
And this continues for four periods of the clock signal 10 before returning to a HIGH output.

The output of the sequencer 6 is shown in FIG. This output is R
This becomes the Z signal output 11.

As described above, in the NRZ-RZ signal conversion circuit of the embodiment, when the data 1 of the NRZ signal including the jitter is input, the data is transmitted over the four periods of the clock signal 10 from the sequencer 6 correspondingly. Since the RZ signal 11 which becomes LOW is output, it can be converted into an RZ signal completely synchronized with the clock signal. Since this conversion is completely synchronized with the clock signal, the operation is stable, and high-speed operation can be performed without delay.

In the embodiment, since the basic period of the NRZ signal including jitter is set to be equal to eight periods of the clock signal, an octal counter, that is, an n-ary counter of n = 8 is used. Is output according to the NRZ signal.
, The program is set so as to output an RZ signal which becomes LOW only for four cycles of the clock signal.

However, the basic period of the NRZ signal including the jitter can be between n periods of the clock signal, where n is an arbitrary integer. In this case, an n-ary counter is used as the counter, and the output of the n-ary counter from the decoder is n / 2−1 or n / 2 ± 0.5 (one of which is an integer). Sometimes output the decode signal,
In addition, the sequencer outputs the clock signal over the period of the numerical value of n / 2 or n / 2 ± 0.5 (one of which is an integer) corresponding to the data 1 of the NRZ signal. Is programmed to be inverted.

[0028]

As is apparent from the above description of the embodiment, the NRZ-RZ signal conversion circuit of the present invention, when generating an RZ signal from an NRZ signal containing jitter, is capable of generating an RZ signal completely synchronized with a clock signal. Since a signal can be output, the conversion operation is stable and a delay can be avoided. Therefore, high-speed communication is possible, and stable operation can be performed even in a severe vehicle environment.

The NRZ-RZ signal conversion circuit according to the present invention is also synchronized with a clock signal when the circuit according to the present invention is programmed and used in a logic circuit such as an FPGA which can be freely written by a user. It does not depend on the delay specific to each device. Therefore, there is no need to change the circuit configuration, and any device can be supported.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an NRZ-RZ signal conversion circuit according to the present invention;

FIG. 2 is a timing chart in the NRZ-RZ signal conversion circuit of the embodiment;

FIG. 3 is a state transition diagram of a sequencer used in the NRZ-RZ signal conversion circuit according to the embodiment;

FIG. 4 is a block diagram showing a conventional NRZ-RZ signal conversion circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 rising differential circuit 2 octal counter 3 decoder 4, 14 2 input AND gate 5, 13 D flip-flop 6 sequencer 7 rising differential signal 8 NRZ signal including jitter 9 reset signal 10 clock signal 11 RZ signal synchronized with clock signal 12 RZ signal 13 D flip-flop 15 2-input NOR gate 16 4-bit loadable counter 17 D flip-flop with reset terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 5/06

Claims (1)

(57) [Claims] 1. A signal conversion circuit for converting an NRZ signal into an RZ signal, comprising: an input of an NRZ signal including jitter and a clock signal;
A rising differential circuit for outputting a rising differential signal of the NRZ signal in synchronization with the clock signal; and receiving the rising differential signal and the clock signal as inputs, resetting the rising differential signal in synchronization with the clock signal, An n-ary counter that counts up in synchronization with the clock signal, a decoder that receives an output of the n-ary counter as an input, and outputs a decode signal of the output of the n-ary counter, and outputs the output of the decoder and the NRZ signal. Input 2
An input AND gate; a D flip-flop that receives the output of the two-input AND gate and the clock signal; and an RZ signal that receives the output of the D flip-flop and the clock signal and is synchronized with the clock signal. NRZ-R comprising a sequencer for outputting
Z signal conversion circuit.