JP3102634B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLL circuit using a DDS.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a basic configuration of a PLL circuit in the prior art. In the figure, 1 is a voltage controlled oscillator (hereinafter referred to as VCO), 2 is a programmable counter (PC), 3 is a phase comparator (φD), 4 is a low-pass filter (LPF) connected in a loop, and this loop circuit And a reference oscillator (REF) 5 that outputs a phase comparison signal to the phase comparator 3.

Here, assuming that the reference oscillation frequency is R and the frequency division value of the programmable counter 2 is N, the minimum step of the output frequency of the PLL circuit is R of the oscillation frequency of the reference oscillator 5. When the output frequency of the VCO 1 is f, the variable range is the set value N of the programmable counter 2.
N times the frequency of The variable range of the output frequency is a range in which the frequency division value N set in the programmable counter 2 is set.

FIG. 2 shows a conventional PL with DDS.
FIG. 2 is a block diagram illustrating a configuration of an L circuit, the configuration being:
A loop circuit including a VCO 1, a programmable counter (PC) 2, a phase comparator (φD) 3, and a low-pass filter (LPF) 4 has a reference oscillator 5 and a DDS (Direct Digit) that uses the reference oscillation frequency as a phase comparison signal.
tal Synthesizer) 6 for sampling, and using the output signal as a phase comparison signal as a phase comparator 3
And the phase of the output signal obtained by dividing the output of the VCO 1 by the dividing ratio N by the programmable counter 2 is compared.
The frequency division setting of the programmable counter 2 is set by the control unit 7 by the CPU. The setting of the DDS is set by inputting the selection of the rotary encoder 8 to the control unit 7, and the product of the dividing ratio N and the phase comparison signal output from the DDS 6 is PLL.
The output frequency of the circuit.

The operation of the PLL circuit shown in FIG. 2 will be described. The DDS 6, which takes in the frequency oscillated by the reference oscillator 7 as a clock signal, inputs a desired frequency set value by a rotary encoder 8 by a dial operation, and the data is transmitted. By outputting the DDS 6 from the CPU of the control unit 7 for setting, a phase comparison signal based on the setting data is output to the phase comparator 3. On the other hand, the oscillation frequency f output from the VCO 1 is frequency-divided by the programmable counter 2 by the frequency division values Nmin to Nmax set by the control unit 7 and supplied to the phase comparator 3. Therefore, the phase is compared by the phase comparison signal input from the DDS 6, and the error signal output from the phase comparator 3 is smoothed through the LPF 4 and supplied to the VCO 1 as an oscillation frequency control signal. When the PLL circuit locks up, a stable desired frequency is output from the VCO 1. This is the basic operation of the PLL circuit.

The reference frequency R of the reference oscillator 5 is set to a relatively large frequency to increase the variable range of the oscillation frequency f of the VCO 1, and the set value of the phase comparison signal output of the DDS 6 based on the reference frequency R is changed by the rotary encoder 8. The interval between the minimum steps of the PLL circuit, which are variably set by the control unit 7 in accordance with the set numerical values and in which the divided values Nmin to Nmax of the programmable counter 2 are set, can be changed in smaller steps, for example, 100 Hz steps. Therefore, not only can the variable range of the oscillation frequency f of the VCO 1 be expanded, but also the minimum step
A circuit has become possible.

FIG. 4 shows a DD for realizing a minute step.
A mixer 10 converts the output of S6 with the output of another oscillator 9 by a mixer 10, mixes the output with the output of a VCO 1 by a mixer 11, and outputs the mixed output to a programmable counter 2 to obtain even smaller steps. It is a block diagram of a circuit. In the figure, 9 is an oscillator (OS
C) 10 and 11 are mixers. This mixdown method uses DDS6 to realize a micro step.
This is a typical LL circuit. Oscillator 9 and mixer 1
0 is provided for the purpose of shifting the output frequency of the DDS 6 to a higher frequency, so that malfunction of the programmable counter 2 due to the output image of the mixer 11 is generally prevented.

[0008]

In the case of the PLL circuit shown in FIG. 2, the variable range of the oscillation frequency f of the VCO is widened.
In addition, the minimum step of the oscillation frequency f is also small, but if the frequency division value of the programmable counter is N, the oscillation frequency f of the VCO is N times the minimum step of the DDS. Therefore, the frequency division value of the programmable counter is 1N, 2N, 3
If the division value of the maximum oscillation frequency band of the VCO is aN, the minimum step becomes a times as large as the division value of 1N, and the minimum step value changes the division value of the programmable counter. Will change with it. For this reason, in a device in which the frequency is set by a dial-type rotary encoder, when the frequency division value of the programmable counter is changed from Nmin to Nmax, the change in the frequency with respect to the rotation angle of the dial is not constant, so that a feeling of operation discomfort occurs.

In the case of the circuit shown in FIG. 4, since the change in the output frequency of the DDS is reflected on the oscillation frequency f of the VCO by sum or difference, the amount of change in the frequency with respect to the rotation angle of the dial is converted into the value of the dividing value N of the programmable counter. Regardless, it is relatively easy to keep it constant, but as shown in the figure, the circuit configuration is more complicated than that of FIG. 2, and there is a disadvantage that the spurious is larger than that of FIG. . The object of the present invention is to provide a PLL circuit which uses the circuit of FIG. 2 and which makes the rotation of the dial correspond to the change of the minimum step and which is less affected by spurious.

[0010]

A loop circuit comprising a voltage controlled oscillator, a programmable counter for dividing the output of the voltage controlled oscillator, a phase comparator for comparing the phase of the output of the programmable counter, and a low-pass filter is provided with a reference oscillator. And a DDS for converting the output of the phase comparator into a phase comparison signal and outputting the output to a phase comparator. The oscillation frequency is set by a dial encoder input by a control unit.
In a circuit, a selection setting means for making a product of a setting value of a division ratio of the programmable counter and a minimum step value within a variable range of the DDS always constant, and changing one step of the dial encoder to the minimum step of the DDS And a dial encoder control means for setting the minimum step of the operation state irrespective of the operation of the PLL circuit, wherein the minimum step of the PLL oscillation frequency and the minimum step of the dial encoder are always constant irrespective of the change of the division ratio of the programmable counter. It is.

[0011]

FIG. 1 is a flowchart showing the operation of the PLL circuit of the present invention in the PLL circuit of FIG. First, the operation of the PLL circuit of FIG. 2 will be described based on the frequency divisions shown in Table 1. The output range of the oscillation frequency of the VCO 1 is set to a range from 64 MHz to 1024 MHz, and the minimum step is set to 100 Hz. DDS 6 is 2 MH based on the selection by rotary encoder 8 in control unit 7.
The output is controlled so as to be in the range of 1 octave from z to 4 MHz, and outputs a predetermined phase comparison signal to the phase comparator 3.

The output frequency of the PLL circuit shown in Table 1 is 64 MHz.
In the range a to 128 MHz, the frequency division ratio N of the programmable counter 2 is 32. When the frequency division ratio N = 32, the minimum step of the PLL circuit must be 100 Hz. 100 Hz ÷ 32 = 3.15 Hz, so
The minimum step A is 3.15 Hz. When the output of DDS6 is 2 MHz, the output frequency of VCO1 is 64 MHz,
When one step is performed by the rotary encoder, the output of the DDS 6 becomes 2.00300015 MHz. In the next step, the phase comparison signal sequentially changed to 2.0000063 MHz is input to the phase comparator 3 and the programmable counter 2
The output signal of the VCO 1 is compared with the value obtained by dividing the frequency by N = 32, and the error signal output is smoothed through the low-pass filter 4 and supplied to the VCO 1 as an oscillation frequency control voltage. Frequency 64.0001M
Hz and then 64.0002 MHz.

[Table 1]

By rotating the rotary encoder 8, the DDS
6 is changed to 4 MHz, and when the output frequency of the VCO 1 becomes 128 MHz, the PLL output frequency in the range b in Table 1 is changed from 128 MHz to 256 MHz, and the frequency division ratio N of the programmable counter 2 is set to 64 by the control of the control unit 7. Change to Also, the phase comparison signal of DDS6 is 2M.
Hz, and the minimum step A is also changed and set to 1.5625 Hz. This minimum step is set in correspondence with one step of the rotary encoder 8, but all setting changes are
It is controlled by the control unit 7 by the PU. In this state, DDS6
Is 2 MHz, the output frequency of the VCO 1 is 128 MHz, the rotary encoder 8 outputs a phase comparison signal of 2.0000015625 MHz from the DDS 6 in the next step, and the output frequency of the VCO 1 is 1
28.0001 MHz. When the phase comparison signal of DDS6 becomes 4 MHz, the output frequency of VCO1 becomes 256
MHz. Even in this frequency band, the minimum step A of the DDS 6 is set to one step of the rotary encoder 8, so that one step of the rotary encoder 8 is
Is 100 Hz, and the change of the minimum step does not change.

Even if the PLL output frequency is changed from 256 MHz in the range c in Table 1 to 512 MHz in this way, if the division ratio of the programmable counter 2 is 128, DD
The minimum step of S6 is set to 0.78125 Hz, and one step of the rotary encoder 8 is set correspondingly. In addition, the PLL output frequency is increased from 512 MHz in the d range to 10 MHz.
24 MHz, the frequency division ratio of the programmable counter 2 is set to 256, and the output of the phase comparison signal of the DDS 6 is 2M.
The minimum step A from Hz to 4 MHz is 0.3906
By setting the frequency to 25 Hz and setting it to one step of the rotary encoder 8, the minimum step change of 100 Hz is always one step of the rotary encoder 8 in any frequency band, and the correlation remains unchanged. Although the method of sequentially increasing the frequency has been described, when the frequency decreases, the frequency division ratio set value of the programmable counter 2 is similarly reduced, and the frequency of the DDS 6 is increased in inverse proportion thereto. This means that A × N = constant by the dividing ratio N and the DDS minimum step A, and one step of the rotary encoder 8 is always the minimum step A
1 step by dial rotation and VCO1
The change of the output frequency in the minimum step 100 Hz is always constant.

A flowchart showing the operation of the PLL circuit of FIG. 1 according to the present invention will be described in comparison with Table 1. Processing S
When the output frequency of the VCO 1 of the PLL circuit is set to 200 MHz in the process S2, the dividing ratio N of the programmable counter 2
Is set to 64, and the minimum step A of DDS6 is also 1.
Set to 5625 Hz. Next, in step S3, one step of the rotary encoder 8 for changing the frequency is
The minimum step A of DS6 is set to 1.5625 Hz.

In the decision box H1, the rotary encoder 8
Is determined to rotate in the direction in which the frequency increases by one step, and if yes, it is determined by the determination box H4 whether the frequency is outside the frequency range of the range b. If not, process S
7, the frequency division has entered the c range.
The CO output frequency is changed from 256 MHz to a 512 MHz band. Therefore, the dividing ratio of the programmable counter 2 is set to 1
The minimum step A is also set to 0.78125 Hz for the phase comparison signal of DDS6. Subsequently, in step S8, one step by the rotation of the rotary encoder 8 is performed by the DDS.
The minimum step A of 6 is set to 0.78125 Hz.
Thereby, even within the range c, one step of the rotary encoder 8 and the minimum step 1 of the VCO output frequency of the PLL circuit
00 Hz can be varied without change. Next, in process S9, D
Add the minimum step A to the output of DS6 and make a decision box H
Return to 1 and execute again.

If the rotation by the rotary encoder is not rotating in the direction of increasing the frequency by the rotary encoder in the decision box H1, the process proceeds to the decision box H2 to determine whether the frequency by the rotary encoder 8 is decreasing. If NO, the process returns to the decision box H1 and is executed again. I do. If the answer is yes, the process moves to the decision box H3, and it is determined whether or not the person has moved out of the range b. If it is determined that the frequency is out of the range, the dividing ratio N of the programmable counter 2 in the range a is set to 32 in step S4, and the minimum step A of the DDS 6 is set to 3.1.
Set to 25 Hz. Subsequently, in step S5, one step by the rotation of the rotary encoder 8 is set to the minimum step A of the DDS6 = 3.125 Hz. Processing S5 and processing S9
After that, the process returns to the decision box H1, and the same operation is repeated again. All of the above operations are controlled by the CPU of the control unit 7.

[0018]

According to the present invention, the reference oscillation frequency is set to DD.
As a phase comparison signal sampled at S and set to the minimum step A, the phase of the signal input to the phase comparator through the programmable counter having the frequency dividing ratio N is compared with the VCO output frequency of the PLL circuit. In the PLL circuit, the product of the minimum step A of the phase comparison signal and the frequency division ratio N is kept constant in all the operation states, and one step of the rotary encoder is set to the minimum step of the DDS in the operation state. Then, a rotary encoder rotated by a dial and a VCO of a PLL circuit
Since the minimum steps of the output frequency coincide with each other, there is an advantage that the rotation of the dial and the change in the frequency do not cause a feeling of strangeness.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an operation of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a PLL circuit having a DDS used in the present invention.

FIG. 3 is a block diagram of a conventional PLL circuit.

FIG. 4 is a block diagram of another PLL circuit of the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 voltage controlled oscillator (VCO) 2 programmable counter (PC) 3 phase comparator (φD) 4 low-pass filter (LPF) 5 reference oscillator (REF) 6 DDS 7 control unit (CPU) 8 rotary encoder

Claims (1)

(57) [Claims] An output of a reference oscillator is supplied to a loop circuit including a voltage controlled oscillator, a programmable counter for dividing the output of the voltage controlled oscillator, a phase comparator for comparing the output of the programmable counter, and a low-pass filter. DDS to convert to phase comparison signal and output to phase comparator
In a PLL circuit in which the oscillation frequency is set by a dial encoder input by a control unit, a product of a set value of a division ratio of the programmable counter and a minimum step value within a variable range of the DDS is provided. Selection setting means that is always constant and one of the rotations of the dial encoder
Regardless of changing the minimum step of DDS,
Dial encoder control means for setting the minimum step of the operation state, wherein the minimum step of the PLL oscillation frequency and one step of the dial encoder are always constant regardless of the change of the division ratio of the programmable counter. PLL circuit.