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JP3100668B2 - Method for manufacturing photovoltaic element - Google Patents

Method for manufacturing photovoltaic element

Info

Publication number
JP3100668B2
JP3100668B2 JP03131585A JP13158591A JP3100668B2 JP 3100668 B2 JP3100668 B2 JP 3100668B2 JP 03131585 A JP03131585 A JP 03131585A JP 13158591 A JP13158591 A JP 13158591A JP 3100668 B2 JP3100668 B2 JP 3100668B2
Authority
JP
Japan
Prior art keywords
crystal semiconductor
semiconductor layer
type non
type
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03131585A
Other languages
Japanese (ja)
Other versions
JPH04333289A (en
Inventor
靖 藤岡
豪人 吉野
直 芳里
正博 金井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP03131585A priority Critical patent/JP3100668B2/en
Publication of JPH04333289A publication Critical patent/JPH04333289A/en
Application granted granted Critical
Publication of JP3100668B2 publication Critical patent/JP3100668B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、ip,in,pin,
nip,pinpin,nipnip,pinpinp
in,nipnipnip接合等少なくともi型非単結
晶半導体層を含む非単結晶半導体の接合からなる光起電
力素子の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ip, in, pin,
nip, pinpin, nipnip, pinpinp
The present invention relates to a method for manufacturing a photovoltaic element including a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer such as an in, nipnipnip junction.

【0002】[0002]

【従来の技術】従来、ip,in,pin,nip,p
inpin,nipnip,pinpinpin,ni
pnipnip接合等少なくともi型非単結晶半導体層
を含む非単結晶半導体の接合からなる光起電力素子の製
造において、i型非単結晶半導体層とp型またはn型非
単結晶半導体層との接合は各非単結晶半導体層を堆積さ
せて積層することにより形成していた。すなわち、i型
非単結晶半導体層の堆積後にp型またはn型非単結晶半
導体層を堆積して、あるいはp型またはn型非単結晶半
導体層の堆積後にi型非単結晶半導体層を堆積して積層
し、非単結晶半導体の接合を形成していた。
2. Description of the Related Art Conventionally, ip, in, pin, nip, p
inpin, nipnip, pinpinpin, ni
In the manufacture of a photovoltaic element comprising a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer such as a pnipnip junction, a junction between an i-type non-single-crystal semiconductor layer and a p-type or n-type non-single-crystal semiconductor layer Was formed by depositing and stacking each non-single-crystal semiconductor layer. That is, a p-type or n-type non-single-crystal semiconductor layer is deposited after depositing an i-type non-single-crystal semiconductor layer, or an i-type non-single-crystal semiconductor layer is deposited after depositing a p-type or n-type non-single-crystal semiconductor layer. To form a junction of a non-single-crystal semiconductor.

【0003】例えば、従来、基板上にn,i,p型非単
結晶半導体層をこの順に積層した構造のアモルファスシ
リコンからなる光起電力素子を製造するには、基板上に
n型アモルファスシリコン層、i型アモルファスシリコ
ン層を順に堆積した後、p型非単結晶半導体層の主成分
元素のSiを含有するSiH4 等のガスと、i型アモル
ファスシリコン層にp型の伝導型を付与せしめる不純物
元素を含有するBF3等のガスとの混合ガスのグロー放
電などによりp型のアモルファスシリコン層を堆積し、
アモルファスシリコンのnip接合構造を形成してい
た。
For example, conventionally, in order to manufacture a photovoltaic element made of amorphous silicon having a structure in which n, i, and p-type non-single-crystal semiconductor layers are stacked in this order on a substrate, an n-type amorphous silicon layer is formed on the substrate. , After sequentially depositing an i-type amorphous silicon layer, a gas such as SiH 4 containing Si as a main element of the p-type non-single-crystal semiconductor layer and an impurity for imparting a p-type conductivity type to the i-type amorphous silicon layer Depositing a p-type amorphous silicon layer by glow discharge of a mixed gas with a gas such as BF 3 containing an element,
A nip junction structure of amorphous silicon was formed.

【0004】しかし、従来のこのような膜堆積による方
法では非単結晶半導体層を大面積に薄く均一に再現性良
く堆積するには限界があり、どうしても所望の厚さより
薄すぎたり厚すぎたりする膜厚のバラツキや、場所によ
る膜厚のムラを生じやすく、素子特性のバラツキやムラ
を生じる原因になっていた。
However, in such a conventional method of film deposition, there is a limit in depositing a non-single-crystal semiconductor layer over a large area uniformly and with good reproducibility, and it is inevitably too thin or too thick as desired. Variations in the film thickness and unevenness in the film thickness depending on the location are liable to occur, which causes unevenness and unevenness in the element characteristics.

【0005】非単結晶半導体層を極薄く堆積するために
は、堆積時間を短くするか堆積速度を遅くする必要があ
る。ところが膜堆積時間を短くすると膜形成条件が安定
しないうちに膜の堆積が行なわれてしまい膜厚の繰り返
し再現性が損なわれて膜厚がバラツキやすく、膜堆積速
度を遅くするために膜の原料の供給量を少なくすると膜
の原料を大面積にわたって均一に供給することが難しく
なり膜厚ムラを生じやすくなるのである。
In order to deposit a non-single-crystal semiconductor layer extremely thinly, it is necessary to reduce the deposition time or the deposition rate. However, if the film deposition time is shortened, the film is deposited before the film formation conditions are unstable, and the reproducibility of the film thickness is impaired, and the film thickness tends to vary. If the supply amount is small, it is difficult to uniformly supply the raw material of the film over a large area, and the film thickness tends to be uneven.

【0006】特に、光起電力素子でi型非単結晶半導体
層の光入射側に配置される不純物ドープ層は、該不純物
ドープ層での光吸収によってi型非単結晶半導体層に入
る光量が減少するのを防ぐため、その層厚を必要最小限
に薄くする必要がある。
In particular, in a photovoltaic element, an impurity-doped layer disposed on the light incident side of the i-type non-single-crystal semiconductor layer has a light quantity entering the i-type non-single-crystal semiconductor layer due to light absorption by the impurity-doped layer. In order to prevent the reduction, the layer thickness must be reduced to the minimum necessary.

【0007】しかし、従来の膜の堆積による方法では膜
厚の制御が難しく、該不純物ドープ層の膜厚にバラツキ
やムラを生じて短絡電流や開放電圧等の素子特性に大き
なバラツキやムラが生じることが多かった。
However, it is difficult to control the film thickness by the conventional method of depositing a film, and the film thickness of the impurity-doped layer becomes uneven or uneven, resulting in large unevenness or unevenness in the element characteristics such as short-circuit current and open voltage. There were many things.

【0008】一方、p型またはn型非単結晶半導体層を
形成する方法としては他に、イオン注入法が従来から知
られている。イオン注入法によれば不純物イオンを打ち
込む強さを加速電圧によって制御することでp型または
n型非単結晶半導体層の層厚を制御することができる
が、不純物イオンを打ち込むためのイオン注入装置は、
一般的に、イオンを発生させる装置系、イオンをビーム
状にして引き出す装置系、ビームを走査する装置系など
からなり、構成が複雑で装置も高価であるため、非単結
晶半導体の太陽電池のような大面積の光起電力素子を生
産性良く、低コストで製造するには適しておらず、不純
物ドープ層の形成手段として採用されてはいなかった。
On the other hand, as another method for forming a p-type or n-type non-single-crystal semiconductor layer, an ion implantation method is conventionally known. According to the ion implantation method, the thickness of the p-type or n-type non-single-crystal semiconductor layer can be controlled by controlling the intensity of implanting impurity ions by an acceleration voltage, but an ion implantation device for implanting impurity ions is used. Is
Generally, the system consists of a system for generating ions, a system for extracting ions in the form of beams, and a system for scanning beams. Such a large-area photovoltaic element is not suitable for manufacturing with good productivity at low cost, and has not been adopted as a means for forming an impurity-doped layer.

【0009】1990年第51回応用物理学会学術講演
会講演予稿集29p−MF−9には、イオンをビーム状
にせずにシャワー状で加速する大面積イオンドーピング
装置を用いて、非単結晶シリコン膜へ不純物ドーピング
を行なう薄膜トランジスタの製法が示されており、従来
からの一般的なイオン注入法に比較し、ドーピング面積
の大面積化と装置の簡素化が可能であることが開示され
ている。
[0009] A non-single-crystal silicon is used for the 29p-MF-9 in the 51st Annual Meeting of the Japan Society of Applied Physics, 1990, using a large-area ion doping apparatus that accelerates ions in the form of a shower instead of a beam. A method of manufacturing a thin film transistor in which a film is doped with impurities is disclosed, and it is disclosed that the doping area can be increased and the device can be simplified as compared with a conventional general ion implantation method.

【0010】ところが、この製法においてもイオンを数
kVもの加速電圧で引き出し、加速して半導体膜に打ち
込むためにイオンの加速装置系が必要であり、また良好
な素子特性を得るにはイオンの打ち込み後に熱アニール
の後処理が必要であった。
However, even in this manufacturing method, an ion accelerator system is required to extract ions at an acceleration voltage of several kV, accelerate the ions, and drive the ions into the semiconductor film. Later, post-treatment of thermal annealing was required.

【0011】[0011]

【発明が解決しようとする課題】本発明の目的は、少な
くともi型非単結晶半導体層を含む非単結晶半導体の接
合からなる光起電力素子の製造方法における上記の問題
点を解決し、i型非単結晶半導体層上にp型またはn型
の非単結晶半導体層を薄く均一な膜厚に再現性良く形成
し、光起電力素子を大面積にわたって素子特性のムラな
く、再現性良く得られる製造方法を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in a method of manufacturing a photovoltaic device comprising a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer. A p-type or n-type non-single-crystal semiconductor layer is formed on the non-single-crystal semiconductor layer in a thin and uniform thickness with good reproducibility, and a photovoltaic element can be obtained over a large area without unevenness of the device characteristics and with good reproducibility. To provide a manufacturing method.

【0012】また、本発明の他の目的は、上記目的を過
大な設備投資を行なうことなく簡易な構成の装置によっ
て、しかも熱アニール等の後処理をすることなく実現す
る製造方法を提供することにある。
Another object of the present invention is to provide a manufacturing method which realizes the above-mentioned object by an apparatus having a simple structure without excessive investment in equipment and without post-processing such as thermal annealing. It is in.

【0013】[0013]

【課題を解決するための手段】本発明による光起電力素
子の製造方法は、少なくともi型非単結晶半導体層を含
む非単結晶半導体の接合からなる光起電力素子の製造方
法であって、前記i型非単結晶半導体層を堆積形成後、
該i型半導体単結晶半導体層を堆積したプラズマ放電室
とは別のプラズマ放電室内に該i型非単結晶半導体層を
移動し、該別のプラズマ放電室内で該i型非単結晶半導
体層にp型またはn型の伝導型を付与せしめる不純物元
素を含有し、該i型非単結晶半導体層の主成分元素を含
有しないガス、あるいは該ガスと希釈用ガスとの混合ガ
スのグロー放電分解プラズマに該i型非単結晶半導体層
表面をさらし、膜の堆積なしに不純物ドープ層を形成し
前記非単結晶半導体の接合を形成せしめた後、該不純物
ドープ層上に続いて透明導電膜を設けることを特徴とし
ている。
A method for manufacturing a photovoltaic device according to the present invention is a method for manufacturing a photovoltaic device comprising a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer, After depositing and forming the i-type non-single-crystal semiconductor layer,
The i-type non-single-crystal semiconductor layer is moved into a plasma discharge chamber different from the plasma discharge chamber in which the i-type semiconductor single-crystal semiconductor layer is deposited, and the i-type non-single-crystal semiconductor layer is moved into the other plasma discharge chamber. Glow discharge decomposition plasma of a gas containing an impurity element imparting p-type or n-type conductivity and not containing a main component element of the i-type non-single-crystal semiconductor layer, or a mixed gas of the gas and a diluting gas after the i-type exposing a non-single-crystal semiconductor layer surface was allowed form a bond formed <br/> the non-single-crystal semiconductor impurity doped layer without film deposition to, the impurity
Following on the doped layer is provided a transparent conductive film is characterized in Rukoto.

【0014】すなわち、本発明の製造方法では、i型非
単結晶半導体層を堆積形成後、該i型半導体単結晶半導
体層上にp型またはi型非単結晶半導体層を形成するた
めに、従来の様にp型またはn型の非単結晶半導体層を
堆積するのではなく、該i型半導体単結晶半導体層を堆
積したプラズマ放電室とは別のプラズマ放電室内に該i
型非単結晶半導体層を移動し、該別のプラズマ放電室内
プラズマ処理によってi型非単結晶半導体層の表面
近傍をp型またはn型非単結晶半導体に変化させるもの
である。
That is, in the manufacturing method of the present invention, after depositing and forming an i-type non-single-crystal semiconductor layer, a p-type or i-type non-single-crystal semiconductor layer is formed on the i-type semiconductor single-crystal semiconductor layer. Instead of depositing a p-type or n-type non-single-crystal semiconductor layer as in the prior art, the i-type semiconductor single-crystal semiconductor layer is deposited.
In a plasma discharge chamber different from the plasma discharge chamber
Type non-single-crystal semiconductor layer is moved to another plasma discharge chamber.
In those that alter the vicinity of the surface of the i-type non-single-crystal semiconductor layer on the p-type or n-type non-single-crystal semiconductor by the plasma treatment.

【0015】尚、ここでのプラズマ処理は、i型非単結
晶半導体層の主成分元素を含有しないガスあるいは該ガ
スと希釈用ガスとの混合ガスのグロー放電プラズマに該
i型非単結晶半導体層表面をさらすという簡単な方法に
よって行なう。
Here, the plasma treatment is performed by applying a glow discharge plasma of a gas not containing a main component element of the i-type non-single-crystal semiconductor layer or a mixed gas of the gas and the diluting gas to the i-type non-single-crystal semiconductor layer. It is performed by a simple method of exposing the layer surface.

【0016】グロー放電プラズマによって不純物元素に
与えられたエネルギーは、イオンを加速するイオン注入
法によって与えられるエネルギーに比べて極めて低く、
イオンを加速しないグロー放電プラズマでは不純物元素
はi型非単結晶半導体層の表面からごく浅い領域迄にし
かドープされない。
The energy given to the impurity element by the glow discharge plasma is extremely lower than the energy given by the ion implantation method for accelerating ions.
In a glow discharge plasma that does not accelerate ions, the impurity element is doped only from the surface of the i-type non-single-crystal semiconductor layer to a very shallow region .

【0017】ところが、本発明者らがi型非単結晶半導
体膜の表面を該i型非単結晶半導体膜にp型またはn型
の伝導型を付与せしめる不純物元素を含有し、該i型非
単結晶半導体膜の主成分元素を含有しないガスのグロー
放電プラズマにさらして試料を作成し、該試料の不純物
元素の膜厚方向の分布を二次イオン分析(SIMS)に
よって調べたところ、グロー放電プラズマの形成条件に
応じて数十ないし数百オングストロームの深さまでi型
層の主成分元素に不純物元素がドープされた層が大面積
にわたってムラなく再現性良く形成されていた。
However, the present inventors have made the surface of the i-type non-single-crystal semiconductor film contain an impurity element which imparts p-type or n-type conductivity to the i-type non-single-crystal semiconductor film, and A sample was prepared by exposing the single crystal semiconductor film to a glow discharge plasma of a gas not containing a main component element, and the distribution of impurity elements in the sample in the thickness direction was examined by secondary ion analysis (SIMS). A layer in which the main element of the i-type layer is doped with an impurity element has been formed over a large area with good uniformity and reproducibility to a depth of several tens to several hundreds of angstroms depending on the plasma formation conditions.

【0018】さらに本発明者らが非単結晶半導体の接合
からなる光起電力素子のi型非単結晶半導体層上の不純
物ドープ層をかかるグロー放電プラズマによって形成し
てみたところ、良好な素子特性をもつ光起電力素子を得
ることができた。
Further, when the present inventors have formed an impurity-doped layer on an i-type non-single-crystal semiconductor layer of a photovoltaic device comprising a junction of a non-single-crystal semiconductor by using such a glow discharge plasma, good device characteristics were obtained. Was obtained.

【0019】少なくともi型非単結晶半導体層を含む非
単結晶半導体の接合からなる光起電力素子では、不純物
ドープ層は充分な不純物濃度が得られるのであれば、光
吸収が少ないということで薄い方が良く、本発明の方法
では膜へのダメージが少なく熱アニールなどの構造緩和
処理の不要なグロー放電プラズマによって良好な不純物
ドープ層が形成されたものと考えられる。
In a photovoltaic element comprising a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer, the impurity-doped layer is thin because it absorbs less light as long as a sufficient impurity concentration can be obtained. It is more preferable that the method of the present invention forms a good impurity-doped layer by glow discharge plasma which causes little damage to the film and does not require structural relaxation treatment such as thermal annealing.

【0020】図1は、本発明の製造方法による製造過程
の一例を示す概略断面図である。nip接合構造の光起
電力素子の製造過程において、(a)は基板上にn,i
型の非単結晶半導体層を堆積によって形成し積層した状
態であり、(b)は(a)の状態からi型非単結晶半導
体層表面を該i型層にp型の伝導型を付与せしめる不純
物元素を含有するガスのグロー放電プラズマにさらして
p型非単結晶半導体層を形成した後の状態を示してい
る。
FIG. 1 is a schematic sectional view showing an example of a manufacturing process according to the manufacturing method of the present invention. In the process of manufacturing a photovoltaic device having a nip junction structure, (a) shows n, i on a substrate.
FIG. 4B shows a state in which a non-single-crystal semiconductor layer of a type is formed by deposition and stacked, and FIG. 4B shows that the surface of the i-type non-single-crystal semiconductor layer is changed from the state of FIG. This figure shows a state after forming a p-type non-single-crystal semiconductor layer by exposing to a glow discharge plasma of a gas containing an impurity element.

【0021】図中、101は基板、102は堆積によっ
て形成したn型非単結晶半導体層、103は同じく堆積
によって形成したi型非単結晶半導体層、104はi型
非単結晶半導体層の表面近傍をプラズマ処理により変化
させて形成したp型非単結晶半導体層である。
In the drawing, 101 is a substrate, 102 is an n-type non-single-crystal semiconductor layer formed by deposition, 103 is an i-type non-single-crystal semiconductor layer formed by deposition, and 104 is the surface of the i-type non-single-crystal semiconductor layer. This is a p-type non-single-crystal semiconductor layer formed by changing the vicinity by plasma treatment.

【0022】i型非単結晶半導体層にp型またはn型の
伝導型を付与せしめる不純物元素を含有するガスのグロ
ー放電を生起すると、たとえ該ガス中にi型非単結晶半
導体層の主成分元素を含有しなくても、たとえばi型非
単結晶半導体層がアモルファスシリコンの場合に該i型
非単結晶半導体層にp型の伝導型を付与せしめるホウ素
原子を含有するガスのグロー放電プラズマでアモルファ
スボロン層を堆積し得るように、不純物元素を主成分と
する半導体膜が堆積する場合があり得る。
When a glow discharge of a gas containing an impurity element imparting p-type or n-type conductivity to the i-type non-single-crystal semiconductor layer occurs, the main component of the i-type non-single-crystal semiconductor layer is contained in the gas. Even if no element is contained, for example, when the i-type non-single-crystal semiconductor layer is amorphous silicon, a glow discharge plasma of a gas containing a boron atom that imparts a p-type conductivity to the i-type non-single-crystal semiconductor layer is used. In some cases, a semiconductor film containing an impurity element as a main component may be deposited so that an amorphous boron layer can be deposited.

【0023】しかし、本発明者らが本発明の製造方法に
おいて、基板上にi型非単結晶半導体層まで堆積させた
素子の他に、コーニング7059ガラス板および単結晶
シリコンウェハをプラズマにさらされる空間に同時に入
れてプラズマ処理を行なったところ、本発明の効果はコ
ーニング7059ガラス板上あるいは単結晶シリコンウ
ェハ上に、光学的および電気的にみて全く膜の堆積が認
められない場合でも明確に確認され、膜の堆積が認めら
れた場合には、かえって効果が薄められる事が判明し
た。
However, in the manufacturing method of the present invention, in addition to the device having the i-type non-single-crystal semiconductor layer deposited on the substrate, the Corning 7059 glass plate and the single-crystal silicon wafer are exposed to plasma. When plasma treatment was performed simultaneously in the space, the effect of the present invention was clearly confirmed even when no film deposition was observed optically and electrically on Corning 7059 glass plate or single crystal silicon wafer. It was found that when the deposition of the film was observed, the effect was rather reduced.

【0024】このことから、本発明の効果は不純物元素
を主成分とする半導体膜の堆積によるものではなく、あ
くまでプラズマ処理によってi型非単結晶半導体層の表
面が変化するためであると確認できた。
From the above, it can be confirmed that the effect of the present invention is not due to the deposition of the semiconductor film containing the impurity element as a main component, but to the change of the surface of the i-type non-single-crystal semiconductor layer due to the plasma treatment. Was.

【0025】本発明において、非単結晶半導体とは単結
晶以外の半導体、すなわちアモルファスから多結晶まで
の構造の半導体をさし、所謂微結晶半導体もこの範ちゅ
うに入ることは言うまでもない。
In the present invention, a non-single-crystal semiconductor refers to a semiconductor other than a single crystal, that is, a semiconductor having a structure from amorphous to polycrystalline, and it goes without saying that a so-called microcrystalline semiconductor also falls into this category.

【0026】以下、本発明においてi型非単結晶半導体
層がSi,SiC,SiGe等の周期律表第IV族の元素
を主成分とする場合を例に挙げて、さらに詳しく説明す
る。周期律表第IV族の元素を主成分とするi型非単結晶
半導体層にp型の伝導型を付与する不純物元素として
は、周期律表第III族のB,Al,Ga,In,Tl等
が挙げられ、n型の伝導型を付与せしめる不純物元素と
しては、周期律表第V族のP,As,Sb,Bi等が挙
げられる。
Hereinafter, the case where the i-type non-single-crystal semiconductor layer in the present invention mainly contains an element belonging to Group IV of the periodic table such as Si, SiC, or SiGe will be described in more detail. Examples of the impurity element that imparts p-type conductivity to an i-type non-single-crystal semiconductor layer mainly containing an element of Group IV of the periodic table include B, Al, Ga, In, and Tl of Group III of the periodic table. Examples of the impurity element that imparts the n-type conductivity include P, As, Sb, Bi, and the like, which belong to Group V of the periodic table.

【0027】これら不純物元素を含有するガスとして
は、常温常圧でガス状態であるか、あるいは少なくとも
グロー放電条件下で気体であり、適宜の気化器で容易に
気化し得る化合物として、BF3,BCl3,BBr3
26,B410,AlCl3,PH3,P25,PF3
PF5,PCl3,AsH3,AsF3,AsF5,AsC
3,SbH3,SbF3等が挙げられ、必要とされる
p,nの伝導型に応じて選択されるこれらの1種、ある
いは2種以上をi型非単結晶半導体層のプラズマ処理用
のガスに含有させる。
The gas containing these impurity elements may be in a gaseous state at normal temperature and normal pressure, or at least a gas under glow discharge conditions, and may be BF 3 , a compound which can be easily vaporized by an appropriate vaporizer. BCl 3 , BBr 3 ,
B 2 H 6 , B 4 H 10 , AlCl 3 , PH 3 , P 2 H 5 , PF 3 ,
PF 5 , PCl 3 , AsH 3 , AsF 3 , AsF 5 , AsC
l 3 , SbH 3 , SbF 3, and the like. One or more of these selected according to the required p and n conductivity types are used for plasma treatment of an i-type non-single-crystal semiconductor layer. Gas.

【0028】該プラズマ処理用のガスには放電を安定さ
せるためにHe,Ne,Ar等の不活性ガスを含有させ
てもよいが、i型非単結晶半導体層の主成分であるS
i,C,Ge等の元素は膜の堆積をさせないがために含
有させてはならない。
The plasma processing gas may contain an inert gas such as He, Ne, or Ar for stabilizing the discharge. However, S, which is a main component of the i-type non-single-crystal semiconductor layer, may be used.
Elements such as i, C, and Ge should not be contained because they do not deposit the film.

【0029】以上、i型非単結晶半導体層が周期律表第
IV族の元素を主成分とする場合について、i型非単結晶
半導体層形成後のプラズマ処理用のガスの例を示した
が、その他の元素あるいは化合物の場合には、そのi型
非単結晶半導体層に対してp型またはn型の伝導型を付
与せしめる不純物元素を含有し、i型非単結晶半導体層
の主成分元素を含有しないガスを選択して用いる。
As described above, the i-type non-single-crystal semiconductor layer corresponds to the first part of the periodic table.
In the case where a group IV element is a main component, an example of a plasma processing gas after forming an i-type non-single-crystal semiconductor layer has been described. In the case of another element or compound, the i-type non-single-crystal A gas containing an impurity element that imparts p-type or n-type conductivity to the semiconductor layer and not containing a main component element of the i-type non-single-crystal semiconductor layer is selected and used.

【0030】本発明において、これらのガスのグロー放
電プラズマを発生させるための励起手段としては、公知
の高周波放電、低周波放電、直流放電、マイクロ波放電
等の電気エネルギー、ヒーター加熱等の熱エネルギー、
光エネルギー等のエネルギー付与手段が挙げられる。
In the present invention, as an exciting means for generating glow discharge plasma of these gases, known electric energy such as high-frequency discharge, low-frequency discharge, DC discharge, microwave discharge, and thermal energy such as heater heating are used. ,
Means for applying energy such as light energy may be used.

【0031】また本発明において、グロー放電プラズマ
にi型非単結晶半導体層の表面をさらすというのは、グ
ロー放電によって活性化された不純物元素がi型非単結
晶半導体層の表面に供給されるようにすることであり、
具体的にはi型非単結晶半導体層まで堆積させた素子を
配置した空間に不純物元素を含むガスのグロー放電プラ
ズマを発生させること等によって行なう。
In the present invention, exposing the surface of the i-type non-single-crystal semiconductor layer to the glow discharge plasma means that the impurity element activated by the glow discharge is supplied to the surface of the i-type non-single-crystal semiconductor layer. Is to do
Specifically, this is performed by generating glow discharge plasma of a gas containing an impurity element in a space where an element deposited up to the i-type non-single-crystal semiconductor layer is arranged.

【0032】さらに、本発明者らは本発明の製造方法に
よって様々な構造の光起電力素子を、該素子のi型非単
結晶半導体層にp型またはn型の伝導型を付与せしめる
不純物元素を含有するガスの中に様々な種類のガスを添
加して製造し、添加するガスの種類と製造される光起電
力素子の特性の対応を調べるうちに、次のような関係を
見い出した。
Further, the present inventors have made photovoltaic devices having various structures by the manufacturing method of the present invention an impurity element for imparting p-type or n-type conductivity to the i-type non-single-crystal semiconductor layer of the device. Various types of gases were added to a gas containing, and the following relationship was found while examining the correspondence between the type of gas to be added and the characteristics of the photovoltaic device to be manufactured.

【0033】すなわち、i型非単結晶半導体層にp型ま
たはn型の伝導型を付与せしめる不純物元素を含有する
ガスに水素ガスを含有させた場合、水素ガスを含有させ
ない場合に比較して製造される光起電力素子の開放電圧
が上昇し、光電変換効率が向上することを見い出したの
である。
That is, when the hydrogen gas is contained in the gas containing the impurity element that imparts the p-type or n-type conductivity to the i-type non-single-crystal semiconductor layer, the production is made in comparison with the case where the hydrogen gas is not contained. It has been found that the open-circuit voltage of the photovoltaic element increases and the photoelectric conversion efficiency improves.

【0034】ip,in,pin,nip,pinpi
n,nipnip,pinpinpin,nipnip
nip等、本発明の適応されるあらゆる接合構造の光起
電力素子を製造し、その素子特性を測定したが、いずれ
の場合にも水素ガスの添加による素子性能の向上が認め
られた。
Ip, in, pin, nip, pinpi
n, nipnip, pinpinpin, nipnip
Photovoltaic devices having any junction structure applicable to the present invention, such as Nip and the like, were manufactured and their device characteristics were measured. In each case, the improvement of device performance was confirmed by the addition of hydrogen gas.

【0035】本発明の光起電力素子の製造方法を実施す
るにあたっては適宜の装置を使用することができるが、
好適なものとしては図2に示す類の装置構成のものを挙
げることができる。
In carrying out the method for manufacturing a photovoltaic device of the present invention, an appropriate apparatus can be used.
As a preferable example, an apparatus having a configuration shown in FIG. 2 can be used.

【0036】図2において、201,202,203は
ステンレス製のプラズマ放電室、204,205は基板
の投入室、取り出し室であり、それぞれのプラズマ放電
室はゲートバルブ206によって接続されている。20
7は基板で、不図示の移動機構により各プラズマ放電室
を移動させることができ、3つのプラズマ放電室でその
表面に非単結晶半導体層の堆積または非単結晶半導体層
表面のプラズマ処理が行なわれ、少なくともi型非単結
晶半導体層を含む非単結晶半導体の接合からなる光起電
力素子が形成される。201〜203の各プラズマ放電
室には基板を裏面から加熱する赤外線ヒーター208、
不図示のガス供給手段から供給されるガスをプラズマ放
電室に導入するガス導入管209、不図示の排気手段に
よりプラズマ放電室を排気する排気管210、プラズマ
放電室内のガスにエネルギーを与えて放電を生起するマ
イクロ波電力を供給するマイクロ波電源211、導波管
212、誘電体のマイクロ波導入窓213が設けられて
いる。
In FIG. 2, reference numerals 201, 202, and 203 denote plasma discharge chambers made of stainless steel, 204 and 205 denote chambers for loading and unloading substrates, and the respective plasma discharge chambers are connected by a gate valve 206. 20
Reference numeral 7 denotes a substrate, which can move each plasma discharge chamber by a moving mechanism (not shown). Three plasma discharge chambers are used to deposit a non-single-crystal semiconductor layer on the surface or perform plasma processing on the surface of the non-single-crystal semiconductor layer. As a result, a photovoltaic element including a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer is formed. An infrared heater 208 for heating the substrate from the back side in each of the plasma discharge chambers 201 to 203;
A gas introduction pipe 209 for introducing a gas supplied from a gas supply unit (not shown) into the plasma discharge chamber, an exhaust pipe 210 for exhausting the plasma discharge chamber by an exhaust means (not shown), and discharging by applying energy to the gas in the plasma discharge chamber. , A microwave power supply 211 for supplying microwave power, a waveguide 212, and a microwave introduction window 213 made of a dielectric material.

【0037】また、本発明の製造方法を実施するための
装置は、図3に示す構成の装置であってもよい。
Further, an apparatus for carrying out the manufacturing method of the present invention may be an apparatus having a configuration shown in FIG.

【0038】図3に示す装置は図2に示した装置のマイ
クロ波電力に代えて高周波電力を用いてグロー放電を生
起するもので、図中301〜309で示されるものは図
2における201〜209に対応している。本装置にお
いて、高周波電力は高周波電源311から供給され、放
電電極312と基板307との間で放電を生起するもの
である。
The device shown in FIG. 3 generates glow discharge by using high-frequency power instead of the microwave power of the device shown in FIG. 2, and the devices denoted by reference numerals 301 to 309 in FIG. 209. In this device, high-frequency power is supplied from a high-frequency power supply 311 and causes a discharge between the discharge electrode 312 and the substrate 307.

【0039】[0039]

【実施例】以下、実施例により本発明を具体的に説明す
るが、本発明はこれらの実施例により何等限定されるも
のではない。
EXAMPLES The present invention will now be described specifically with reference to examples, but the present invention is not limited to these examples.

【0040】実施例1 図2に示した装置を用い、本発明の方法により、以下に
示す操作によって基板上にnip構造のアモルファスシ
リコン光起電力素子を製造した。
Example 1 Using the apparatus shown in FIG. 2, an amorphous silicon photovoltaic device having a nip structure was manufactured on a substrate by the following operation according to the method of the present invention.

【0041】先ず、幅30cm、長さ30cm、厚さ
0.5mmの表面を鏡面研磨したステンレス基板207
を供給室204にセットした後、ゲートバルブ206を
閉じた状態で供給室204、プラズマ放電室201,2
02,203、取り出し室205のすべての真空チャン
バーをそれぞれの排気管210から十分に排気した。
First, a stainless steel substrate 207 having a width of 30 cm, a length of 30 cm and a thickness of 0.5 mm was mirror-polished on its surface.
Is set in the supply chamber 204, and then the supply chamber 204, the plasma discharge chambers 201,
02, 203, and all the vacuum chambers of the extraction chamber 205 were sufficiently evacuated from the respective exhaust pipes 210.

【0042】次に、ゲートバルブ206を開き、基板を
プラズマ放電室201に移動させた後にゲートバルブ2
06を閉じ、ガス導入管209からn型非単結晶半導体
層の原料ガスを導入しつつ、排気量を調節してプラズマ
放電室201内を所定の圧力に調整した。
Next, the gate valve 206 is opened, and the substrate is moved to the plasma discharge chamber 201.
06 was closed, and while the source gas for the n-type non-single-crystal semiconductor layer was being introduced from the gas introduction pipe 209, the exhaust amount was adjusted to adjust the inside of the plasma discharge chamber 201 to a predetermined pressure.

【0043】ヒーター208により基板207を所定の
温度に加熱し、マイクロ波導入窓213から2.45G
Hzのマイクロ波電力を導入してプラズマ放電室201
内にグロー放電プラズマを生起させ、基板上にn型アモ
ルファスシリコン層を堆積させた。所定時間放電を続け
た後、放電とガスの導入を止め、プラズマ放電室を十分
に排気した。
The substrate 207 is heated to a predetermined temperature by the heater 208, and the microwave is introduced from the microwave introduction window 213 to 2.45 G.
Hz microwave power is introduced to the plasma discharge chamber 201.
A glow discharge plasma was generated in the inside, and an n-type amorphous silicon layer was deposited on the substrate. After the discharge was continued for a predetermined time, the discharge and gas introduction were stopped, and the plasma discharge chamber was sufficiently evacuated.

【0044】続いて、同様にして基板をプラズマ放電室
202に移動し、i型非単結晶半導体層の原料ガスのマ
イクロ波グロー放電プラズマによりi型アモルファスシ
リコン層を堆積させた。各プラズマ放電室での膜の堆積
条件を表1に示す。
Subsequently, the substrate was similarly moved to the plasma discharge chamber 202, and an i-type amorphous silicon layer was deposited by microwave glow discharge plasma of a source gas for the i-type non-single-crystal semiconductor layer. Table 1 shows film deposition conditions in each plasma discharge chamber.

【0045】[0045]

【表1】 以上の様にしてi型非単結晶半導体層までの膜堆積を行
なった基板をプラズマ放電室203に移動させ、前記i
型非単結晶半導体層のアモルファスシリコン膜にp型の
伝導型を付与せしめる不純物であるホウ素原子を含有す
るBF3と、希釈用のガスであるHeの混合ガスをガス
導入管209から、マイクロ波電力をマイクロ波導入窓
213からプラズマ放電室203に導入してグロー放電
プラズマを生起させ、i型非単結晶半導体層の表面をグ
ロー放電プラズマにさらしp型層を形成させた。プラズ
マ処理の条件を表2に示す。
[Table 1] The substrate on which the film has been deposited up to the i-type non-single-crystal semiconductor layer as described above is moved to the plasma discharge chamber 203,
A mixed gas of BF 3 containing boron atoms, which is an impurity for imparting a p-type conductivity to the amorphous silicon film of the non-single-crystal semiconductor layer, and He, which is a diluting gas, is supplied through a gas introduction tube 209 to a microwave. Power was introduced from the microwave introduction window 213 into the plasma discharge chamber 203 to generate glow discharge plasma, and the surface of the i-type non-single-crystal semiconductor layer was exposed to the glow discharge plasma to form a p-type layer. Table 2 shows the conditions of the plasma treatment.

【0046】[0046]

【表2】 プラズマ処理の後、アモルファスシリコン膜を堆積させ
た基板を取り出し室205に移動させ、装置から取り出
した。
[Table 2] After the plasma treatment, the substrate on which the amorphous silicon film was deposited was moved to the take-out chamber 205 and taken out of the apparatus.

【0047】上記方法で得られたnip接合構造のアモ
ルファスシリコン膜を形成させた30cm角の基板を1
0cm角の大きさに9等分に切り離して真空蒸着装置に
入れ、表3に示す条件でITO透明導電膜を、さらにマ
スクを用いてAgのグリッド状の集電電極を真空蒸着法
によって形成させ、図4の概略断面図に示す光起電力素
子を製造した。図4において、401はステンレス基
板、402はn型非単結晶半導体層、403はi型非単
結晶半導体層、404はp型非単結晶半導体層、405
はITO透明導電膜、406は集電電極である。
A 30 cm square substrate on which an amorphous silicon film having a nip junction structure obtained by the above method was formed,
It was cut into 9 pieces each having a size of 0 cm square and put into a vacuum deposition apparatus. An ITO transparent conductive film was formed under the conditions shown in Table 3, and a grid-shaped Ag current collecting electrode was formed by a vacuum deposition method using a mask. The photovoltaic element shown in the schematic sectional view of FIG. 4 was manufactured. 4, reference numeral 401 denotes a stainless steel substrate; 402, an n-type non-single-crystal semiconductor layer; 403, an i-type non-single-crystal semiconductor layer; 404, a p-type non-single-crystal semiconductor layer;
Denotes an ITO transparent conductive film, and 406 denotes a current collecting electrode.

【0048】[0048]

【表3】 以上の製造方法により、30cm角のステンレス基板
を10枚投入して同じ条件で10cm角の光起電力素子
を90個製造し、製造した光起電力素子をAM1.5、
100mW/cm2の擬似太陽光のもとで各素子の開放
電圧、短絡電流等の素子特性を測定した。
[Table 3] According to the above manufacturing method, 10 pieces of 30 cm square stainless steel substrates are put in, 90 pieces of 10 cm square photovoltaic elements are manufactured under the same conditions, and the manufactured photovoltaic elements are AM1.5,
The device characteristics such as open-circuit voltage and short-circuit current of each device were measured under 100 mW / cm 2 simulated sunlight.

【0049】その結果、開放電圧、短絡電流は、従来の
堆積による方法で適正な膜厚のp型非単結晶半導体層を
i型非単結晶半導体層上に形成できた場合の光起電力素
子の特性値を100とした比較で、開放電圧は100〜
102、短絡電流は99〜101という値であり、良好
な特性を大面積にわたって再現性良く得られていた。ま
た、光起電力素子の製造後、グロー放電プラズマ処理を
行なったプラズマ放電室203の内壁を光学的、電気的
手段により分析したが、膜、粉体の付着は全く認められ
ず、プラズマ放電室203の内部は全く汚染されていな
かった。
As a result, the open-circuit voltage and short-circuit current can be reduced by the conventional photovoltaic element in the case where a p-type non-single-crystal semiconductor layer having an appropriate thickness can be formed on the i-type non-single-crystal semiconductor layer. The open circuit voltage is 100 to
102, the short-circuit current was 99 to 101, and good characteristics were obtained with good reproducibility over a large area. After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 203 which was subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. The inside of 203 was not contaminated at all.

【0050】比較例1 プラズマ放電室203に導入するガスを表4に示したよ
うにi型非単結晶半導体層の主成分元素であるSiを含
有する様に変え、p型アモルファスシリコン層を堆積に
よって形成するようにした以外は実施例1と同様にし
て、ステンレス基板上にnipアモルファスシリコン層
を積層した10cm角の光起電力素子を90個製造し、
AM1.5、100mW/cm2の擬似太陽光のもとで
各素子の開放電圧、短絡電流を測定した。
COMPARATIVE EXAMPLE 1 As shown in Table 4, the gas introduced into the plasma discharge chamber 203 was changed to contain Si, which is a main component of the i-type non-single-crystal semiconductor layer, and a p-type amorphous silicon layer was deposited. In the same manner as in Example 1 except that the photovoltaic element was formed as above, 90 pieces of 10 cm square photovoltaic elements each having a nip amorphous silicon layer laminated on a stainless steel substrate were manufactured.
The open-circuit voltage and short-circuit current of each element were measured under simulated sunlight of AM 1.5 and 100 mW / cm 2 .

【0051】[0051]

【表4】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のp型非単結晶半導体層をi型非単結晶半導体
層上に形成できた場合の光起電力素子の特性値を100
とした比較で、開放電圧は91〜100、短絡電流は8
5〜100と投入基板ごとに、あるいは基板内の場所に
より素子性能に大きなムラ、バラツキがあった。
[Table 4] As a result, the open-circuit voltage and the short-circuit current are reduced by 100 to the characteristic value of the photovoltaic element when a p-type non-single-crystal semiconductor layer having an appropriate thickness can be formed on the i-type non-single-crystal semiconductor layer by a deposition method.
The open-circuit voltage is 91 to 100 and the short-circuit current is 8
There was large unevenness and variation in element performance from 5 to 100 for each input substrate, or depending on the location in the substrate.

【0052】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室203の内壁を
光学的、電気的手段により分析したところ、p型アモル
ファスシリコン膜の付着が認められ、微小の膜片が内壁
から剥れてプラズマ放電室203内部に舞っており、ま
たマイクロ波導入窓213の内面にも膜が付着し、内部
を清掃せずにこれ以上製造を続行することは困難な状況
であった。
After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 203 which had been subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. Film pieces are peeled off from the inner wall and flow inside the plasma discharge chamber 203, and a film adheres to the inner surface of the microwave introduction window 213, and it is difficult to continue the manufacturing without cleaning the inside. It was a situation.

【0053】後の実験は汚染されたプラズマ放電室20
3内部を充分清掃して膜が残留しない状況で行なった。
The subsequent experiment was performed in a contaminated plasma discharge chamber 20.
3 The inside was thoroughly cleaned and no film remained.

【0054】実施例2 プラズマ放電室203に導入するガスを表5に示したよ
うに変え、p型に伝導型を付与せしめる不純物元素を含
有するガスに水素ガスを含有した以外は実施例1と同様
にして、ステンレス基板上にnip接合構造のアモルフ
ァスシリコン層を積層した10cm角の光起電力素子を
90個製造し、AM1.5、100mW/cm2の擬似
太陽光のもとで各素子の開放電圧、短絡電流を測定し
た。
Example 2 The procedure of Example 1 was repeated except that the gas introduced into the plasma discharge chamber 203 was changed as shown in Table 5 and that the gas containing the impurity element for imparting conductivity to the p-type contained hydrogen gas. Similarly, 90 10 cm square photovoltaic elements in which an amorphous silicon layer having a nip junction structure is laminated on a stainless steel substrate are manufactured, and each element is simulated under simulated sunlight of AM 1.5 and 100 mW / cm 2 . The open circuit voltage and short circuit current were measured.

【0055】[0055]

【表5】 その結果、開放電圧、短絡電流は、従来の堆積による
方法で適正な膜厚のp型非単結晶半導体層をi型非単結
晶半導体層上に形成できた場合の光起電力素子の特性値
を100とした比較で、開放電圧は108〜110、短
絡電流は100〜101であった。開放電圧が高く、良
好な特性の光起電力素子をムラ、バラツキなく大面積に
わたって再現性良く得られていた。
[Table 5] As a result, the open-circuit voltage and the short-circuit current are the characteristic values of the photovoltaic element when the p-type non-single-crystal semiconductor layer having an appropriate thickness can be formed on the i-type non-single-crystal semiconductor layer by the conventional deposition method. The open-circuit voltage was 108 to 110 and the short-circuit current was 100 to 101. A photovoltaic element having a high open-circuit voltage and good characteristics was obtained with good reproducibility over a large area without unevenness or variation.

【0056】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室203の内壁を
光学的、電気的手段により分析したが、膜、粉体の付着
は全く認められず、プラズマ放電室203の内部は全く
汚染されていなかった。
After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 203 which had been subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. The inside of the plasma discharge chamber 203 was not contaminated at all.

【0057】実施例3 図2に示した装置を用いてステンレス基板を204から
投入し、プラズマ放電室203,202でマイクロ波に
よりp,i型非単結晶半導体層の堆積を、プラズマ放電
室201でi型非単結晶半導体層表面のプラズマ処理を
行い、pin構造のアモルファスシリコン膜を形成し
た。p,i層の形成条件を表6に、i型非単結晶半導体
層表面のプラズマ処理の条件を表7に示す。アモルファ
スシリコン膜の形成後、実施例1と同様にしてITO透
明導電膜、集電電極を積層して10枚の基板から90個
の光起電力素子を製造し、AM1.5、100mW/c
2の擬似太陽光のもとで各素子の開放電圧、短絡電流
を測定した。
Example 3 A stainless steel substrate was loaded from 204 using the apparatus shown in FIG. 2, and p and i type non-single-crystal semiconductor layers were deposited by microwaves in plasma discharge chambers 203 and 202. Then, plasma treatment was performed on the surface of the i-type non-single-crystal semiconductor layer to form an amorphous silicon film having a pin structure. Table 6 shows conditions for forming the p and i layers, and Table 7 shows conditions for plasma treatment of the surface of the i-type non-single-crystal semiconductor layer. After the formation of the amorphous silicon film, an ITO transparent conductive film and a collecting electrode were laminated in the same manner as in Example 1 to manufacture 90 photovoltaic elements from 10 substrates, and AM1.5, 100 mW / c.
under the open voltage of each element of the pseudo sunlight of m 2, and to measure the short-circuit current.

【0058】[0058]

【表6】 [Table 6]

【0059】[0059]

【表7】 その結果、開放電圧、短絡電流は、従来の堆積による
方法で適正な膜厚のn型非単結晶半導体層をi型非単結
晶半導体上に形成できた場合の光起電力素子の特性値を
100とした比較で、開放電圧は100〜101、短絡
電流は100〜102と良好な特性の光起電力素子をム
ラ、バラツキなく大面積にわたって再現性良く得られて
いた。
[Table 7] As a result, the open-circuit voltage and the short-circuit current depend on the characteristic value of the photovoltaic element when an n-type non-single-crystal semiconductor layer having an appropriate thickness can be formed on an i-type non-single-crystal semiconductor by a conventional deposition method. As compared with 100, the open-circuit voltage was 100 to 101, and the short-circuit current was 100 to 102. Photovoltaic devices having good characteristics were obtained with good reproducibility over a large area without unevenness or variation.

【0060】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室201の内壁を
光学的、電気的手段により分析したが、膜、粉体の付着
は全く認められず、プラズマ放電室201の内部は全く
汚染されていなかった。
After the photovoltaic device was manufactured, the inner wall of the plasma discharge chamber 201 subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. The inside of the plasma discharge chamber 201 was not contaminated at all.

【0061】比較例2 プラズマ放電室201に導入するガスを表8に示すよう
にi型層の主成分元素であるSiを含有するように変
え、n型アモルファスシリコン層を堆積によって形成す
るようにした以外は実施例3と同様にして、ステンレス
基板上にpin接合構造のアモルファスシリコン層を積
層した10cm角の光起電力素子を90個製造し、AM
1.5、100mW/cm2の擬似太陽光のもとで各素
子の開放電圧、短絡電流を測定した。
Comparative Example 2 As shown in Table 8, the gas introduced into the plasma discharge chamber 201 was changed to contain Si, which is a main component element of the i-type layer, and an n-type amorphous silicon layer was formed by deposition. Except for the above, 90 photovoltaic elements of 10 cm square in which an amorphous silicon layer having a pin junction structure was laminated on a stainless steel substrate were manufactured in the same manner as in Example 3, and AM
The open-circuit voltage and short-circuit current of each element were measured under simulated sunlight of 1.5 and 100 mW / cm 2 .

【0062】[0062]

【表8】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のn型非単結晶半導体層をi型非単結晶半導体
層上に形成できた場合の光起電力素子の特性値を100
とした比較で、開放電圧は85〜100、短絡電流は8
0〜100と投入基板ごとに、あるいは基板内の場所に
より素子性能に大きなバラツキ、ムラがあった。
[Table 8] As a result, the open-circuit voltage and the short-circuit current are reduced by 100 to the characteristic value of the photovoltaic element when an n-type non-single-crystal semiconductor layer having an appropriate thickness can be formed on the i-type non-single-crystal semiconductor layer by a deposition method.
The open circuit voltage was 85 to 100 and the short circuit current was 8
There was large variation and unevenness in the element performance depending on the input substrate from 0 to 100, or depending on the location in the substrate.

【0063】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室201の内壁を
光学的、電気的手段により分析したところ、n型アモル
ファスシリコン膜の付着が認められ、微小の膜片が内壁
から剥れてプラズマ放電室201内部に舞っており、ま
たマイクロ波導入窓213の内面にも膜が付着し、内部
を清掃せずにこれ以上製造を続行することは困難な状況
であった。
After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 201 subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. Film pieces are peeled off from the inner wall and flow inside the plasma discharge chamber 201, and the film adheres to the inner surface of the microwave introduction window 213, so that it is difficult to continue the production without cleaning the inside. It was a situation.

【0064】後の実験は汚染されたプラズマ放電室20
1内部を充分に清掃して膜が残留していないことを確認
した後に行なった。
A subsequent experiment was conducted using the contaminated plasma discharge chamber 20.
1 was carried out after sufficient cleaning of the inside to confirm that no film remained.

【0065】実施例4 プラズマ処理のガスを表9に示すように水素ガスに変え
た以外は実施例3と同様にして90個の光起電力素子を
製造し、AM1.5、100mW/cm2の擬似太陽光
のもとで各素子の開放電圧、短絡電流を測定した。
Example 4 Ninety photovoltaic elements were manufactured in the same manner as in Example 3 except that the gas for the plasma treatment was changed to hydrogen gas as shown in Table 9, and AM 1.5, 100 mW / cm 2 The open-circuit voltage and short-circuit current of each element were measured under simulated sunlight.

【0066】[0066]

【表9】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のn型非単結晶半導体層を形成できた場合の値
を100とした比較で、開放電圧は113〜114、短
絡電流は100〜101と開放電圧が高く、良好な特性
の光起電力素子をムラ、バラツキなく大面積にわたって
再現性良く得られていた。
[Table 9] As a result, the open-circuit voltage and short-circuit current were 113 to 114, and the open-circuit voltage and short-circuit current were 113 to 114, respectively, when the value obtained when an n-type non-single-crystal semiconductor layer having an appropriate thickness could be formed by a deposition method was 100. The open-circuit voltage was as high as 100 to 101, and a photovoltaic element having good characteristics was obtained with good reproducibility over a large area without unevenness or variation.

【0067】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室201の内壁を
光学的、電気的手段により分析したが、膜、粉体の付着
は全く認められず、プラズマ放電室201の内部は全く
汚染されていなかった。
After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 201 which had been subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. The inside of the plasma discharge chamber 201 was not contaminated at all.

【0068】実施例5 放電用のエネルギー源を高周波電源に変えた以外は図2
と同様の図3に示す装置を用いて、表10に示す条件で
n,i層を堆積し、表11に示す条件でプラズマ処理を
行ない、ステンレス基板上にアモルファスシリコンから
なる10cm角の光起電力素子を90個製造し、AM
1.5、100mW/cm2の擬似太陽光のもとで各素
子の開放電圧、短絡電流を測定した。
Example 5 FIG. 2 was changed except that the energy source for discharging was changed to a high frequency power source.
The n and i layers are deposited under the conditions shown in Table 10 using the same apparatus shown in FIG. 3 and subjected to plasma treatment under the conditions shown in Table 11, and a 10 cm square photovoltaic film made of amorphous silicon is formed on a stainless steel substrate. 90 power elements were manufactured and AM
The open-circuit voltage and short-circuit current of each element were measured under simulated sunlight of 1.5 and 100 mW / cm 2 .

【0069】[0069]

【表10】 [Table 10]

【0070】[0070]

【表11】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のp型非単結晶半導体層を形成できた場合の値
を100とした比較で、開放電圧は114〜115、短
絡電流は100〜101と良好な特性の光起電力素子を
ムラ、バラツキなく大面積に再現性良く得られていた。
[Table 11] As a result, the open-circuit voltage and short-circuit current were 114 to 115, and the open-circuit voltage and short-circuit current were 114 to 115, respectively. A photovoltaic element having characteristics as good as 100 to 101 was obtained over a large area with good reproducibility without unevenness or variation.

【0071】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室303の内壁を
光学的、電気的手段により分析したが、膜、粉体の付着
は全く認められず、プラズマ放電室303の内部は全く
汚染されていなかった。
After the manufacture of the photovoltaic element, the inner wall of the plasma discharge chamber 303 subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. The inside of the plasma discharge chamber 303 was not contaminated at all.

【0072】比較例3 プラズマ放電室303に導入するガスを表12に示した
ように変え、p型アモルファスシリコン層を堆積によっ
て形成するようにした以外は実施例5と同様にして、ス
テンレス基板上にnip接合構造のアモルファスシリコ
ン層を積層した10cm角の光起電力素子を90個製造
し、AM1.5、100mW/cm2の擬似太陽光のも
とで各素子の開放電圧、短絡電流を測定した。
Comparative Example 3 A stainless steel substrate was formed in the same manner as in Example 5 except that the gas introduced into the plasma discharge chamber 303 was changed as shown in Table 12, and a p-type amorphous silicon layer was formed by deposition. 90 pieces of 10 cm square photovoltaic elements were manufactured by laminating an amorphous silicon layer with a nip junction structure, and the open-circuit voltage and short-circuit current of each element were measured under simulated sunlight of AM 1.5 and 100 mW / cm 2. did.

【0073】[0073]

【表12】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のp型非単結晶半導体層を形成できた場合の値
を100とした比較で、開放電圧は88〜100、短絡
電流は85〜100と投入基板ごとに、あるいは基板内
の場所により素子性能に大きなバラツキ、ムラがあっ
た。
[Table 12] As a result, the open-circuit voltage and the short-circuit current were 88 to 100, and the open-circuit voltage and the short-circuit current were 88 to 100, respectively. From 85 to 100, there was a great variation and unevenness in the element performance depending on each input substrate or depending on the location in the substrate.

【0074】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室303の内壁を
光学的、電気的手段により分析したところ、p型アモル
ファスシリコン膜およびポリシラン粉の付着が認めら
れ、プラズマ放電室303の内部はかなり汚染されてい
た。
After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 303 that had been subjected to the glow discharge plasma treatment was analyzed by optical and electrical means. As a result, the adhesion of the p-type amorphous silicon film and the polysilane powder was observed. As a result, the inside of the plasma discharge chamber 303 was considerably contaminated.

【0075】後の実験は汚染されたプラズマ放電室30
3内部を充分に清掃して膜が残留しない状況で行なっ
た。
The subsequent experiment was performed in the contaminated plasma discharge chamber 30.
3 The cleaning was performed in a state where the inside was sufficiently cleaned and no film remained.

【0076】実施例6 i型非単結晶半導体層の形成条件を表13に示すように
変え、i型非単結晶半導体層をアモルファスシリコンゲ
ルマニウムに変えた以外は実施例5と同様にして、ステ
ンレス基板上に10cm角の光起電力素子を90個製造
し、AM1.5、100mW/cm2の擬似太陽光のも
とで各素子の開放電圧、短絡電流を測定した。
Example 6 A stainless steel was produced in the same manner as in Example 5 except that the conditions for forming the i-type non-single-crystal semiconductor layer were changed as shown in Table 13 and the i-type non-single-crystal semiconductor layer was changed to amorphous silicon germanium. 90 photovoltaic elements of 10 cm square were manufactured on the substrate, and the open-circuit voltage and short-circuit current of each element were measured under simulated sunlight of AM 1.5 and 100 mW / cm 2 .

【0077】[0077]

【表13】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のp型非単結晶半導体層を形成できた場合の値
を100とした比較で、開放電圧は113〜114、短
絡電流は100〜102と良好な特性の光起電力素子を
ムラ、バラツキなく再現性良く得られていた。
[Table 13] As a result, the open-circuit voltage and the short-circuit current were 113 to 114, and the open-circuit voltage and the short-circuit current were 113 to 114, respectively. Photovoltaic elements having characteristics as good as 100 to 102 were obtained with good reproducibility without unevenness or variation.

【0078】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室303の内壁を
光学的、電気的手段により分析したが、膜、粉体の付着
は全く認められず、プラズマ放電室303の内部は全く
汚染されていなかった。 実施例7 i型非単結晶半導体層の形成条件を表14に示すように
変え、i型非単結晶半導体層をアモルファスシリコン炭
素に変えた以外は実施例5と同様にして、ステンレス基
板上に10cm角の光起電力素子を90個製造し、AM
1.5、100mW/cm2の擬似太陽光のもとで各素
子の開放電圧、短絡電流を測定した。
After the manufacture of the photovoltaic element, the inner wall of the plasma discharge chamber 303 subjected to the glow discharge plasma treatment was analyzed by optical and electrical means, but no film or powder was found to adhere. The inside of the plasma discharge chamber 303 was not contaminated at all. Example 7 An i-type non-single-crystal semiconductor layer was formed on a stainless steel substrate in the same manner as in Example 5 except that the conditions for forming the i-type non-single-crystal semiconductor layer were changed as shown in Table 14, and the i-type non-single-crystal semiconductor layer was changed to amorphous silicon carbon. 90 photovoltaic elements of 10 cm square were manufactured, and AM
The open-circuit voltage and short-circuit current of each element were measured under simulated sunlight of 1.5 and 100 mW / cm 2 .

【0079】[0079]

【表14】 その結果、開放電圧、短絡電流は、堆積による方法で適
正な膜厚のp型非単結晶半導体層を形成できた場合の値
を100とした比較で、開放電圧は110〜111、短
絡電流は100〜101と良好な特性の光起電力素子を
ムラ、バラツキなく再現性良く得られていた。
[Table 14] As a result, the open-circuit voltage and the short-circuit current are 110 to 111, and the open-circuit voltage and the short-circuit current are 110 to 111, respectively, when the value obtained when a p-type non-single-crystal semiconductor layer having an appropriate film thickness can be formed by a deposition method is 100. Photovoltaic devices having characteristics as good as 100 to 101 were obtained with good reproducibility without unevenness or variation.

【0080】また、光起電力素子の製造後、グロー放電
プラズマ処理を行なったプラズマ放電室303の内壁を
光学的、電気的手段により分析したが、膜、粉体の付着
は全く認められず、プラズマ放電室303内部は全く汚
染されていなかった。
After the photovoltaic element was manufactured, the inner wall of the plasma discharge chamber 303 which had been subjected to the glow discharge plasma treatment was analyzed by optical and electrical means, but no film or powder was found to adhere. The inside of the plasma discharge chamber 303 was not contaminated at all.

【0081】[0081]

【発明の効果】以上説明したように、本発明の光起電力
素子の製造方法によれば、少なくともi型非単結晶半導
体層を含む非単結晶半導体の接合からなる光起電力素子
の製造において前記i型非単結晶半導体層上にp型また
はn型の非単結晶半導体層を大面積にわたって薄く均一
な膜厚に再現性良く形成することができ、素子特性にム
ラ、バラツキがほとんど無い光起電力素子を大面積に再
現性良く製造することができる。
As described above, according to the method for manufacturing a photovoltaic device of the present invention, a method for manufacturing a photovoltaic device comprising a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer is provided. A p-type or n-type non-single-crystal semiconductor layer can be formed on the i-type non-single-crystal semiconductor layer over a large area with a thin and uniform film thickness with good reproducibility, and there is almost no unevenness or variation in device characteristics. An electromotive element can be manufactured over a large area with good reproducibility.

【0082】また、本発明の光起電力素子の製造方法に
よれば、上記効果を過大な設備投資を行なうことなく簡
易な構成の装置によって、しかも熱アニール等の後処理
をすることなく得ることができる。
Further, according to the method for manufacturing a photovoltaic element of the present invention, the above effects can be obtained by an apparatus having a simple configuration without excessive capital investment and without post-treatment such as thermal annealing. Can be.

【0083】さらに、本発明の光起電力素子の製造方法
によれば、i型非単結晶半導体層上のp型またはn型の
非単結晶半導体層を形成するプラズマ放電室の内部を汚
染することなく、大量の光起電力素子を製造装置内部の
清掃を行なうことなしに連続して製造することができ、
装置生産性を高めることができる。
Further, according to the method of manufacturing a photovoltaic device of the present invention, the inside of the plasma discharge chamber for forming the p-type or n-type non-single-crystal semiconductor layer on the i-type non-single-crystal semiconductor layer is contaminated. Without a large number of photovoltaic elements can be manufactured continuously without cleaning the inside of the manufacturing equipment,
Equipment productivity can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の製造方法による製造過程を示す概略断
面図である。
FIG. 1 is a schematic sectional view showing a manufacturing process according to a manufacturing method of the present invention.

【図2】本発明の光起電力素子の製造方法を実現するプ
ラズマ放電装置の一例を示す模式的概略図である。
FIG. 2 is a schematic diagram showing an example of a plasma discharge device for realizing a method for manufacturing a photovoltaic element according to the present invention.

【図3】本発明の光起電力素子の製造方法を実現するプ
ラズマ放電装置の他の一例を示す模式的概略図である。
FIG. 3 is a schematic diagram showing another example of a plasma discharge device for realizing the method for manufacturing a photovoltaic element of the present invention.

【図4】本発明の方法を実施して製造される光起電力素
子の層構成を示す概略斜視図である。
FIG. 4 is a schematic perspective view showing a layer configuration of a photovoltaic element manufactured by performing the method of the present invention.

【符号の説明】[Explanation of symbols]

101,207,307,401 基板 102,402 n型非単結晶半導体層 103,403 i型非単結晶半導体層 104,404 p型非単結晶半導体層 201,202,203,301,302,303
プラズマ放電室 204,205,304,305 基板投入、取り出
し室 206,306 ゲートバルブ 208,308 赤外線ヒーター 209,309 ガス導入管 210,310 排気管 211 マイクロ波電源 212 導波管 213 マイクロ波導入窓 311 高周波電源 312 放電電極 405 ITO透明導電膜 406 集電電極
101, 207, 307, 401 Substrate 102, 402 n-type non-single-crystal semiconductor layer 103, 403 i-type non-single-crystal semiconductor layer 104, 404 p-type non-single-crystal semiconductor layer 201, 202, 203, 301, 302, 303
Plasma discharge chamber 204, 205, 304, 305 Substrate loading / unloading chamber 206, 306 Gate valve 208, 308 Infrared heater 209, 309 Gas introduction pipe 210, 310 Exhaust pipe 211 Microwave power supply 212 Waveguide 213 Microwave introduction window 311 High frequency power supply 312 Discharge electrode 405 ITO transparent conductive film 406 Current collecting electrode

フロントページの続き 合議体 審判長 東森 秀朋 審判官 田部 元史 審判官 青山 待子 (56)参考文献 特開 昭58−9321(JP,A) 特開 平2−252235(JP,A) 特開 昭55−125681(JP,A) 特開 平4−299576(JP,A) 特開 昭55−78524(JP,A)Continuation of the front page Judge, Hidetomo Higashimori Judge, Motofumi TABE Judge, Ms. Ayako Aoyama (56) References JP-A-58-9321 (JP, A) JP-A-2-252235 (JP, A) -125681 (JP, A) JP-A-4-299576 (JP, A) JP-A-55-78524 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 少なくともi型非単結晶半導体層を含む
非単結晶半導体の接合からなる光起電力素子の製造方法
であって、前記i型非単結晶半導体層を堆積形成後、該
i型半導体単結晶半導体層を堆積したプラズマ放電室と
は別のプラズマ放電室内に該i型非単結晶半導体層を移
動し、該別のプラズマ放電室内で該i型非単結晶半導体
層にp型またはn型の伝導型を付与せしめる不純物元素
を含有し、該i型非単結晶半導体層の主成分元素を含有
しないガス、あるいは該ガスと希釈用ガスとの混合ガス
のグロー放電分解プラズマに該i型非単結晶半導体層表
面をさらし、膜の堆積なしに不純物ドープ層を形成し
記非単結晶半導体の接合を形成せしめた後、該不純物ド
ープ層上に続いて透明導電膜を設けることを特徴とする
光起電力素子の製造方法。
1. A method for manufacturing a photovoltaic element comprising a junction of a non-single-crystal semiconductor including at least an i-type non-single-crystal semiconductor layer, wherein the i-type non-single-crystal semiconductor layer is deposited and formed. The i-type non-single-crystal semiconductor layer is moved to a plasma discharge chamber different from the plasma discharge chamber where the semiconductor single-crystal semiconductor layer is deposited, and the i-type non-single-crystal semiconductor layer is p-type or The glow discharge decomposition plasma of a gas containing an impurity element imparting an n-type conductivity and not containing a main component element of the i-type non-single-crystal semiconductor layer, or a mixed gas of the gas and a diluting gas is used. exposing the mold non-single-crystal semiconductor layer surface, after brought form a bond before <br/> Symbol non-single crystal semiconductor to form an impurity doped layer without film deposition, the impurity de
Method of producing a photovoltaic element characterized Rukoto a transparent conductive film following the-loop layer.
【請求項2】 前記希釈用ガスが水素ガスを含有するこ
とを特徴とする請求項1に記載の光起電力素子の製造方
法。
2. The method according to claim 1, wherein the diluting gas contains hydrogen gas.
【請求項3】 前記i型非単結晶半導体層を堆積する前
記プラズマ放電室と前記i型非単結晶半導体層を堆積す
る該プラズマ放電室とは別のプラズマ放電室はゲートバ
ルブによって接続されている請求項1に記載の光起電力
素子の製造方法。
3. The plasma discharge chamber for depositing the i-type non-single-crystal semiconductor layer and another plasma discharge chamber for depositing the i-type non-single-crystal semiconductor layer are connected by a gate valve. The method for manufacturing a photovoltaic device according to claim 1.
JP03131585A 1991-05-08 1991-05-08 Method for manufacturing photovoltaic element Expired - Fee Related JP3100668B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03131585A JP3100668B2 (en) 1991-05-08 1991-05-08 Method for manufacturing photovoltaic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03131585A JP3100668B2 (en) 1991-05-08 1991-05-08 Method for manufacturing photovoltaic element

Publications (2)

Publication Number Publication Date
JPH04333289A JPH04333289A (en) 1992-11-20
JP3100668B2 true JP3100668B2 (en) 2000-10-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP03131585A Expired - Fee Related JP3100668B2 (en) 1991-05-08 1991-05-08 Method for manufacturing photovoltaic element

Country Status (1)

Country Link
JP (1) JP3100668B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3169337B2 (en) * 1995-05-30 2001-05-21 キヤノン株式会社 Photovoltaic element and method for manufacturing the same
US5716480A (en) * 1995-07-13 1998-02-10 Canon Kabushiki Kaisha Photovoltaic device and method of manufacturing the same

Also Published As

Publication number Publication date
JPH04333289A (en) 1992-11-20

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