JP3100011B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus, and more particularly to a solid-state image pickup apparatus using a photoelectric conversion element such as a semiconductor photodiode and a charge-coupled device (CCD) and a driving method thereof.

[0002]

2. Description of the Related Art A solid-state image pickup device of a CCD transfer system is known, and is used for an electronic camera, a copying machine, and other video equipment. A large number of photodiodes are vertically and horizontally arranged to form a pixel matrix. Further, a vertical charge transfer path (VCCD) is formed adjacent to each photodiode row,
A horizontal charge transfer path (HCC) adjacent to the end of each VCCD
D) is formed.

In recent years, there has been a strong demand for miniaturization of solid-state imaging devices. Chip size from 1 inch to 2/3 inch, 1
When the size is reduced to 1/2 inch or 1/3 inch, the number of photodiodes does not change because the number of pixels in the vertical direction of the solid-state imaging device is determined by standards such as NTSC and PAL.

In order to independently read out the charges of the photodiodes all at once, a vertical CCD needs two or more electrodes per photoresist in order to prevent charge mixing.
In order to perform further transfer, generally three or more transfer electrodes are required for each photodiode. However, as the chip size is reduced, there is a limit to the fine processing, and it becomes difficult to form three or more electrodes per photodiode.

[0005] By the way, in the standards such as NTSC and PAL, it is only necessary to obtain an image signal of an interlace system.
It suffices if scanning is performed every other line and one screen can be obtained by scanning twice. Therefore, a VCCD having two transfer electrodes per row of photodiodes is used.

However, when a high-definition still image is captured by flash exposure, since the flash light is instantaneous, the exposure start time is the same for all photodiodes. If the exposure end time is different, the exposure time will change. High-definition images are not good unless the imaging times are the same. Also,
To obtain a high-definition image, the number of pixels is preferably as large as possible. Therefore, it is desired to take out the charges of all the photodiodes at once.

A frame transfer type solid-state imaging device having a light receiving section including a plurality of vertical transfer paths having a photoelectric conversion function and a charge transfer function, and a storage section including a plurality of vertical transfer paths connected to these charge transfer paths. Devices are also known.

An accordion transfer method has been proposed as a method for simultaneously reading out all the stored charges in this type of device (PHILIPS TECHNICAL REVIEW VOL. 43, No. 1 /).
2, 1986, AJP Theuwissen and CHL Weijte
ns).

FIG. 11 shows an accordion transfer system. FIG. 11A is a conceptual diagram showing how the potential under the electrode of the transfer path changes over time. FIG. 11B is a conceptual plan view showing how charges move by the accordion transfer method.

[0010] In this specification, the term "potential" refers to the energy of a position, and the lower the potential is, the more stable the state is, regardless of whether the charge is positive or negative. FIG.
In (A), the electrodes of the transfer path are odd-numbered electrodes Od.
And even-numbered electrodes Ev. A cell of a charge transfer path is formed below each of these electrodes. First, the potential under the odd-numbered electrodes is lowered, a potential well is formed, and charges qa, qb, and qc are accumulated. If the potential barrier disposed between the potential wells is lowered in this state, charge mixing occurs.

Therefore, the potential under the rightmost even-numbered electrode is first reduced, and the potential well is extended to two electrodes. Then, the electric charge qa is distributed on the right side by one electrode. Next, when the potential of the left side portion of the potential well storing the charge qa is raised and the potential of the right side potential barrier portion is lowered at the same time, the charge qa moves to the right side by one electrode while being distributed over two electrodes.

Then, a potential barrier for two electrodes is formed between the charges qa and qb. Thereafter, by sequentially increasing the potential of the left portion of the charge qa and decreasing the potential of the right portion, the charge qa is sequentially transferred to the right.

When a potential barrier corresponding to two electrodes is generated between the electric charges qa and qb, if the potential of the electric potential barrier on the right side of the electric charge qb is lowered, the electric charge qb is spread and distributed over the two electrodes. become. At this time, since there is a potential barrier for at least one electrode, usually two electrodes, between the charges qa and qb, charge mixing does not occur.

In this way, by transferring the electric charges accumulated every other electrode to a double pitch and distributing them, electric charges can be transferred. FIG. 11B schematically shows the distribution of charges transferred in this manner. In the figure, the horizontal axis indicates a time change, and the vertical axis indicates the electrodes of the transfer path. In the leftmost state, charges qa, qb, qc, and qd are accumulated in every other electrode in the upper half of the transfer path. Among these charges, the charges are transferred downward while sequentially forming a two-electrode-length potential well and a two-electrode-length potential barrier from the lower charge.

That is, the charge during the transfer is 2
A potential barrier for two electrodes is formed between the charges during the transfer and distributed between the electrodes. In this way, it is possible to transfer the charges accumulated every other electrode while preventing charge mixing. In the rightmost state where the transfer is completed, the electric charges qa, qb, qc, and qd are distributed again every other electrode.

Since the appearance of the potential well and the potential barrier at the time of transfer is similar to the case where the accordion of the musical instrument is gradually widened and then closed again, this charge transfer method is an accordion transfer method. Called.

As can be seen from the potential diagram of FIG. 11A, the drive signal of the accordion transfer system is a four-phase signal. The present applicant has proposed a transfer method for performing similar charge transfer in a solid-state imaging device including a photodiode matrix, a vertical charge transfer path, and a horizontal charge transfer path.
In this method, the transfer path is not a photodiode, but C
Become a CD. The drive signal is also interline CCD
Was transferred by a four-phase drive similar to the above. However, at the time of transfer, only one signal could be transferred per two rows of photodiodes.

FIG. 12 shows the FIT proposed by the present applicant earlier.
It is a figure explaining a pseudo frame electronic shutter. FIG.
12A is a schematic plan view showing the configuration, and FIG. 12B is a conceptual diagram showing the operation.

In FIG. 12A, for example, a p-type silicon substrate is doped with an n-type impurity, so that a large number of photodiodes P are arranged in a matrix, and a plurality of photodiodes P are arranged adjacent to each column of the photodiodes. Is formed.

A transfer gate G is formed between the photodiode P and the charge transfer path L. In the charge transfer path L, two electrodes are formed for each row of photodiodes.

The charge transfer path L extends from a region where photodiodes are distributed to a region where photodiodes are not distributed, and has a light receiving portion R and a storage portion S. At the end of the storage section of each charge transfer path L,
One HCCD is connected, and the output of the HCCD is taken out via a charge detection amplifier.

The photodiodes P distributed in a matrix are classified into odd-numbered photodiodes PA and even-numbered photodiodes PB. Odd-numbered photodiode P
A forms the A field, and the even-numbered photodiodes PB form the B field, and these two fields constitute a screen of one frame.

Since the charge transfer path L includes only two electrodes per row of photodiodes, if charges are read from all photodiodes and transferred at the same time, charge mixing occurs.

Therefore, the following operation is performed in order to read out the charges accumulated in all the photodiodes without causing charge mixing. FIG. 12B schematically shows an operation for reading out charges from the photodiode in FIG.

First, the charges accumulated in the odd-numbered photodiodes PA are read out to the light receiving portion L (R) of the charge transfer path L. In this state, one charge signal is read out to four electrodes in the charge transfer path L.

Next, the charge read out to the charge transfer path L (R) of the light receiving section is transferred to the charge transfer path L (S) of the storage section S. This transfer can be performed by, for example, four-phase driving,
At this time, no charge mixing occurs.

After the charges accumulated in the odd-numbered photodiodes are stored in the charge transfer path L (S) of the storage section, the charges accumulated in the even-numbered photodiodes PB are stored in the charge transfer path L (R) of the light receiving section. read out. Thus, in the charge transfer path L, the charge signal of the A field is stored in the storage portion thereof.
The charge signal of the B field is stored in the light receiving section.

Next, the charges in the charge transfer path L (S) of the storage section are transferred to the HCCD one row at a time, and the HCCD is transferred in the horizontal direction and taken out of the charge detection amplifier. After all the electric signals of the A field stored in the storage unit are read out in this manner, the electric charge signals stored in the electric charge transfer path L (R) of the light receiving unit are transferred downward, and the HCCD is transferred one row at a time. To the horizontal direction through the HCCD and taken out of the charge detection amplifier.

By the above operation, the charge signals accumulated in all the photodiodes PA and PB can be read. However, in this method, the imaging time is shifted between the A field and the B field, and the imaging is not performed at the same time. The charge transfer in the charge transfer path L is performed by an interline type C.
Data is transferred by four-phase driving similar to CD.

[0030]

In accordion-type charge transfer or domino-type charge transfer, the charge signal on the transfer path is extended and transferred, so that the time required for transfer becomes longer. That is, it is necessary to apply a drive signal to the vertical CCD for a long time, and the required power is large.

Further, the electric charge stored in the upper part of the transfer path needs to be held at a certain position in the electric charge transfer path for a longer time than the electric charge stored in the lower part of the transfer path. by the way,
A dark current is generated in the charge transfer path. The electric charge read out from the photodiode to the charge transfer path is held at a certain position in the charge transfer path for a different time depending on the position, and then transferred. The dark current is small while the transfer is repeated in a short cycle, but increases when it is held at a certain location.

The magnitude of the dark current is not uniform in the charge transfer path, but has a distribution (variation) in place.
For this reason, the dark current received by the charge signal held at a certain location has a fixed pattern.

An object of the present invention is to provide a driving method of a solid-state imaging device which can reduce power consumption. Another object of the present invention is to provide a method for driving a solid-state imaging device capable of reducing the generated dark current.

Another object of the present invention is to provide a solid-state imaging device capable of reducing generated dark current and reducing power consumption.

[0035]

According to a method of driving a solid-state imaging device of the present invention, a plurality of photoelectric conversion elements arranged in a matrix and a photoelectric conversion element arranged adjacent to each column of the photoelectric conversion elements are provided. A plurality of columns of vertical CCDs that can take in the electric charges accumulated in the elements, and a horizontal CCD that is connected to the plurality of columns of the vertical CCDs and that can receive electric charges transferred from the vertical CCDs in parallel and output them in series. A driving method for a solid-state imaging device, wherein each of the vertical CCDs has an m-stage configuration, and each of the vertical CCDs has k rows. A step of taking in the vertical CCDs, applying a drive signal to the vertical CCDs, sequentially transferring the charges taken from the photoelectric conversion elements to the horizontal CCDs, and empty packets in which no charges are present from the horizontal CCDs to the respective vertical CCDs. The and a transfer step of feeding, the period for charge transfer for one line in the horizontal CCD, an empty packet is within the vertical CCD motion of two or more rows, the vertical CCD
In the area where empty packets are distributed, a driving signal that changes the voltage is supplied only to the stage that moves the empty packet, and the driving signals of the other stages do not change the voltage, and at the end of the vertical CCD where the electric charge becomes empty. Stops the drive signal.

[0036]

[0037]

[0038]

The power consumption can be reduced by not applying a drive signal to a portion where the electric charge of the vertical CCD becomes empty.

[0039]

The effect of the dark current on the stored charge becomes more pronounced as the stay time of the stored charge becomes longer. By moving the stored charge in a predetermined cycle, the influence of the dark current on the stored charge can be reduced.

Further, by changing the position of the stored charge, the influence of the dark current having a spatial distribution is averaged,
The occurrence of fixed pattern noise can be prevented.

[0042]

FIG. 1 shows a method for driving a solid-state imaging device according to an embodiment of the present invention. The figure shows the time change of the charge distribution in the vertical CCD (VCCD) 2 and the horizontal CCD (HCCD) 5. In the figure, VCCD2 and HCCD are arranged vertically.
5 shows the distribution of electric charges within 5, and shows the time change in the horizontal direction.

FIG. 2 schematically shows a configuration of a solid-state imaging device for implementing the driving method of FIG. In FIG. 2, a large number of photodiodes (PD) 1 are arranged in a matrix in a photosensor plane. A transfer gate (TG) 7 is formed on the right side of each photodiode 1 and is connected to a vertical CCD (VCCD) 2 arranged in a vertical direction. VC
The CD 2 includes a portion of the electrode 3 connected to the photodiode 1 via the transfer gate 7 and a portion of the electrode 4 interposed between the electrodes 3.

The electric charges accumulated in the PD 1 in the form of a matrix are taken into the corresponding VCCD 2 through the TG 7,
The data is transferred in the vertical direction in the VCCD 2 and the horizontal CCD (HC
CD) 5. The HCCD 5 to which the charges for each row have been transferred from the VCCD 2 performs the charge transfer in the horizontal direction, and outputs the signal charges for each row from the output amplifier 8.

In a state where electric charges are read out from all the photodiodes 1 to the VCCD 2, electric charges are accumulated under each electrode 3 of the VCCD 2. If the potential under the electrode 4 is lowered in order to transfer all the charges in this state, mixing between adjacent charges occurs.

FIG. 1 is a schematic diagram for explaining a domino type charge transfer in which all charges can be read out without causing charge mixing in the configuration as shown in FIG. In the figure, the left end shows one column of the photodiode PD and the associated transfer gates TG and VCCD2 and HCCD5, and the right side shows the charge transfer state in the VCCD2 and HCCD5. The horizontal axis shows the time change.

First, at the timing of the field shift FS, the accumulated charge is taken into the VCCD from each PD. It is assumed that there are 1000 PDs (1000 rows) in each column, and charges are numbered from 1 to 1000.

In the first horizontal scanning period 1H, the lowermost charge is transferred from the VCCD to the HCCD, and then transferred to the HCCD, and the next charge is transferred to the position where the lowermost charge was located.

In the second horizontal scanning period 2H, the second charge transferred to the lowermost stage is transferred to the HCCD 5, and
The charges are transferred horizontally in the CCD 5 and the third and fourth charges from the bottom are transferred downward.

As described above, the charges for one row are transferred to the HCCD 5 for each horizontal scanning period H, and are read out. VCC
The transfer of the charges in D2 is started for two rows every one horizontal scanning period H. Considering the case where there are 1000 rows of photodiodes PD, the transfer of the 1000th charge read at the top starts at the 500th H. And 50
The uppermost charge that has started to be transferred at 0H is transferred to the HCCD 5 at 1000H.

The 501st horizontal scanning period 50
At 1H, no charge is present at the upper end of VCCD2. It is unnecessary to supply a drive signal to a portion where there is no charge, and wasteful power is wasted.

Therefore, in the region where the electric charge no longer exists, the driving of the VCCD is stopped. For example, VC
If the CD is driven in four phases and driven in units of two rows, it is not necessary to drive the electrodes of the topmost VCCD in two rows at 502H. Thereafter, two rows from the top need not be driven every 1H.

When the VCCD is driven in units of four rows, it is not necessary to drive the top end of the VCCD at 503H. Therefore, the power consumption can be reduced by stopping the driving of the VCCD in an area where the charge is no longer present on the side farther from the HCCD due to the charge transfer in the VCCD.

FIG. 3 shows an example of a drive circuit for performing such a drive. FIG. 3A shows a drive circuit using a microcomputer. A drive signal φ is applied to the electrodes 3 and 4 of the VCCD 2 via the transistor Tr.

The drive signal φ includes four-phase drive signals φ1, φ2,
φ3 and φ4, which drive the VCCD with two rows as one unit. The gate electrodes of these transistors Tr are grouped in groups of four and controlled by a control signal from the microcomputer 9.

When starting the charge transfer, the microcomputer 9 first turns on the control signal S1, and turns off the other control signals. Next, the control signals S1 and S2 are turned on. In this manner, the microcomputer 9 sequentially expands the transfer area of the VCCD 2 from the HCCD 5 side. When the charge transfer further proceeds after the transfer area in the VCCD 2 reaches the upper end, no charge is present above the VCCD 2 as shown in FIG.

FIG. 3B shows the waveform of the control signal when no electric charge exists at the upper end of the VCCD 2. In the figure, HD is a horizontal drive signal, _Sf is a control signal at the top, S
_f-1 is a control signal of the next stage, and _Sf-2 is a control signal of the next stage.

[0058] When the charge in the region corresponding to the top of the control signal S _f is no longer present, down to a low level control signal S _f in the horizontal scanning period, turns off the corresponding transistors Tr, the driving signal φ Is not transmitted to the VCCD. In the next horizontal scanning period, _Sf and _Sf-1 fall to low level, and the corresponding transistor Tr is turned off.

As described above, as the charges are transferred downward, the region to which the control signal S is applied gradually narrows downward. Therefore, in a region where no charge is present and the charge transfer is unnecessary, the voltage of the electrode of the VCCD 2 is not driven, so that power consumption is reduced.

FIG. 3C shows a configuration of a drive circuit using a shift register. The drive signal of the VCCD is applied to the transistor Tr via the shift register SR1.
The drive signal supplied from the shift register SR1 has a region to which the drive signal is applied sequentially spread upward from below. Such a shift register can be configured using a shift register based on a MOS circuit proposed by the present applicant.

On the other hand, another shift register SR2 applies a control signal to the gate signal of the transistor Tr. The shift register SR2 is configured such that the transistor Tr
Are sequentially turned off from the upper side to the lower side. Such a shift register can be configured by inverting the output of the above-described shift register or the like.

Control of shift register SR2 is performed by a signal from control circuit 10. This control circuit 10
Can be constituted by an external microcomputer or a circuit such as a PLD, for example.

According to the driving method shown in FIGS. 1 to 3, the position of the electric charge read at the uppermost stage does not change during the first half of the electric charge reading period. If the electric charge is fixed in one place of the CCD, the generated dark current increases with time. Further, when the generated dark current has a spatial distribution, a fixed pattern also occurs. In order to reduce such a dark current, it is preferable that charges are not fixed but transferred.

FIG. 4 shows an empty packet supply type charge transfer method. In the figure, one VCCD is shown in the vertical direction,
The temporal change is shown in the horizontal direction. In the lower part, HCC
D is also shown.

In the cycle c1 shown at the left end of FIG.
The accumulated charges are taken into the VCCD 2 from all the photodiodes 1. As shown in FIG.
Two transfer electrodes 3, 4 are formed per row, one of which 3 is connected to the photodiode 1 via a transfer gate 7. In FIG. 4, only the electrode 3 is shown in the VCCD 2.

Therefore, all photodiodes 1
In the cycle c1 in which the charge is taken in the CD2,
Electric charges are taken under every other electrode 3 of the VCCD 2. In this state, the electrode 3 into which the electric charge has been taken
If the potential under the electrode 4 forming the barrier between the electrodes 3 and 3 is lowered, charge mixing will occur.

In the cycle c1, the HCCD5
Has no stored charge and has an empty packet 6. In the next cycle c2, the empty packet 6 existing in the HCCD 5 is transferred to the second lower electrode of the VCCD. For this reason, the electric charges accumulated under the second to lower electrodes of the VCCD 2 are transferred one by one. At this time, the charge at the bottom of the VCCD 2 is transferred to the HCCD 5 first, and then the charge existing under the second electrode is transferred to the lower electrode. Empty packet 6 without VCC
D.

Thereafter, the empty packets 6 are sequentially sent upward by two lines while proceeding to the cycles c3, c4 and c5. In this way, in the cycle cn, the empty packet 6 is sent from the bottom to (n-1) × the second electrode.

Cycles c1 to cn are defined as one cycle,
Here, charge transfer of the HCCD 5 is performed. The charge transferred to the HCCD 5 is output,
A blank packet for one row is formed in 5. This state is indicated by a cycle c (n + 1).

From the cycle c (n + 2), the HCCD
The empty packets 6 in 5 are sent into the VCCD 2 and sequentially transferred upward. This step is the same as the steps from cycle c2 to cn.

As described above, in cycle c (2n), the empty packet 6 sent into the VCCD 2 in cycle c (n + 2) is transferred again to a predetermined position. Here, in the cycle c (2n + 1), the charges accumulated in the HCCD are transferred again, and an empty packet is formed in the HCCD5.

By repeating such an operation, H
Each time the CCD 5 performs one horizontal charge transfer, the empty packet 6 moves by 2 (n-1) rows in the VCCD. When the empty packet 6 passes, the electric charge at that position changes the position for one line.

The moving speed of the empty packet is 2 (n-1) times the moving speed of the accumulated charges, and can be sufficiently high. For this reason, the electric charge at a position distant from the HCCD is prevented from being held at a fixed location for a long time, and the electric charge changes its position every predetermined time. Therefore, the influence of the dark current is reduced, and the generation of the fixed pattern is prevented.

FIG. 5 is a potential diagram showing the state of charge transfer in such a VCCD. The vertical axis indicates potential. When the charge is an electron, the downward direction is the positive direction of the voltage. The VCCD 2 is divided into units of two rows, and the symbols A, B, C,...
In the figure, the lapse of time is shown in the vertical direction. Elapse of time of eight stages, for example, t11 to t18, corresponds to one cycle c shown in FIG.

In FIG. 4, the empty packet is 2
(N-1) One distribution per row, but in FIG.
This shows a case where one empty packet is distributed every 0 rows. Also, in FIG. 4, only the electrode at the position connected to the photodiode 1 in the VCCD is shown, but in FIG.
The electrode 3 connected to the photodiode and the electrode 4 between them are shown together.

At time t08, empty packets are distributed below the electrodes A4 and F4. At the next time t11, the potentials of the B1 electrode and the G1 electrode are changed to the middle level V _M.
To form a potential well under the electrode. Therefore, the electric charge stored under the B2 electrode and the G2 electrode is 3
It becomes distributed under one of the electrodes A4-B2 and F4-G2.

Next, at time t12, the electrodes B2 and G2
Lower potential is raised. For this reason, the charges distributed over the three electrodes are below the electrodes A4, B1 and F4, G
It is pushed into two electrodes below one.

Next, at time t13, the potential on the right side of the potential barrier formed over the two electrodes, that is, the potential under the electrodes B3 and G3 is lowered, and the potential of the electrode B4 is reduced.
And the electric charge accumulated under G4 is distributed over two electrodes.

At time t14, electrodes B1 and G
The potential under 1 is raised, and the electric charge distributed over the two electrodes A4 and B1 and the two electrodes F4 and G1 is confined under one electrode A4 and F4.
At this stage, the electric charges accumulated under the electrodes B2 and G2 are as follows.
It has moved one line below the electrodes A4 and F4.

At the next timing t15, the electrode B
2 and 2 by lowering the potential under G2
The barrier portion formed over the electrodes is defined as one electrode,
The charges distributed over the two electrodes B3, B4 and G3 and G4 are replaced with the three electrodes B2 to B4 and G2 to G4.
Distribute over 4.

Next, at t16, the electrodes B4 and G4
By raising the lower potential, the charge distributed over three electrodes is reduced to two electrodes. Subsequently, at time t17, the potential under the electrodes B3 and G3 is further increased, and the electric charge distributed over two electrodes is confined in one electrode. At this stage, the charges accumulated under the electrodes B4 and G4 have moved to the electrodes B2 and G2 by one line.

Next, at time t18, when the potential under the electrodes B4 and G4 is lowered, an empty packet is formed there. By such an operation, empty packets existing in A4 and F4 at time t08 are changed to time t8.
At 18, the position has been moved to positions B4 and G4 moved by two lines. That is, the empty packet moves two rows while the electric charge in the B stage moves one row.

The charge transfer in the period from time t11 to t18 is performed only by controlling the potential under each of the B-stage and G-stage electrodes. That is, during this time, the A-stage and the C-F stages are kept in a stopped state fixed to a predetermined potential. By not changing the voltage of unnecessary electrodes, power consumption is reduced. The same cycle is repeated five times for each of the accumulated charges from the A-th stage to the E-stage to move by one row.

From time t21 to time t28, the potentials of the C and H stages (not shown) are controlled, and
By performing the same operation from 11 to t18,
The empty packets existing in B4 and G4 are moved to C4 and H4 (not shown). By repeating such charge transfer, empty packets can be moved into the VCCD at a speed ten times faster than the charge transfer speed in the VCCD.

Further, for example, the charge existing under electrodes B2 and B4 is moved under electrodes A4 and B2 by one cycle from time t11 to t18. Such movement of the charge position reduces the occurrence of dark current. Further, the time during which the same charge is held at the same position is limited. Therefore, generation of fixed pattern noise is also prevented.

Returning to FIG. 4, the empty packet is transferred in the VCCD at, for example, 10 times the speed of the charge readout. For example, when the VCCD2 has 1000 rows, the charge of the VCCD2 is read out when the charge for 100 rows is read out. An empty packet reaches the top. Thereafter, empty packets are sequentially transferred to the upper part of the VCCD 2, and the area where the charges exist is in the VCCD 2.
Move to the lower side in 2.

As shown on the right side of FIG. 4, a drive signal is not supplied to the area of the VCCD 2 where the charge is no longer present, and the area is set as a non-transfer area. This non-transfer area extends from the upper side to the lower side of the VCCD 2 as the charge transfer proceeds. Such a supply stop of the drive signal of the VCCD can be realized by using a microcomputer, a shift register or the like as described in FIG.

FIG. 6 is a timing chart of a control signal for performing the charge transfer as shown in FIGS.
FIG. 6A shows input signals φIN, φA, φ to the control circuit.
B, and drive signals φ1, φ2, φ3, φ4 applied to the four types of electrodes shown in FIG. 5 and a drive signal φH applied to the HCCD 5.

FIG. 6B is an enlarged timing chart showing drive signals φ1, φ2, φ3, and φ4 applied to four types of electrodes. In FIG. 6B, at time t8, drive signals φ1 and φ3 are at low level L, and φ2 and φ4 are at middle level M. This state corresponds to t08, t18, and t28 in FIG.

At time t1, drive signal φ1 changes from low level L to middle level M. The low level is, for example, a potential of -8 to -9 V, and the middle level M is, for example, a potential of 0 V. When the drive signal φ1 changes to the middle level, the area under the corresponding electrode changes from the barrier state to the well state.

In FIG. 5, the electrodes B1, G at time t11
1 and the electrode C1 at time t21 correspond to this state.
In FIG. 6B, at time t2, the drive signal φ
2 changes from the middle level M to the low level L. Due to the change in the drive signal φ2, the state below the corresponding second electrode changes from the well state to the barrier state. Time t2 in FIG. 6B corresponds to t12, t22,... In FIG.

At time t3 in FIG. 6B,
The drive signal φ3 changes from the low level L to the middle level M. By this change in the drive signal, the state below the corresponding third electrode changes from the barrier state to the well state. FIG.
The time t3 in (B) is the time t13, t2 in FIG.
Corresponds to 3, ...

At time t4 in FIG. 6B,
The drive signal φ1 changes from the middle level M to the low level L. Due to the change of the drive signal φ1, the state below the corresponding first electrode changes from the well state to the barrier state. This state corresponds to times t14, t24,... In FIG.

At time t5 in FIG. 6B,
The drive signal φ2 changes from the low level L to the middle level M. That is, the state under the corresponding second electrode changes from the barrier state to the well state. This state corresponds to times t15, t25,... In FIG.

At time t6 in FIG. 6B,
The drive signal φ4 changes from the middle level M to the low level L. Under the corresponding fourth electrode, the state changes from the well state to the barrier state. This state corresponds to time t1 in FIG.
6, t26,...

At time t7 in FIG. 6B,
The drive signal φ3 changes from the middle level M to the low level L. Under the corresponding third electrode, the state changes from the well state to the barrier state. This state corresponds to time t1 in FIG.
7, t27,...

At time t8 in FIG. 6B,
A state similar to the first time t8 is realized, and every other well and barrier are distributed in the VCCD. In one cycle from t1 to t8, the empty packet arranged in the VCCD moves by two rows.

Note that such a control signal is applied only to the stage where an empty packet is to be moved. The other stages are kept in a stopped state for holding the accumulated charge. For example, a middle-level potential is applied below the electrode 3 storing the charge, and a low-level potential is applied below the electrode 4 forming the barrier portion without storing the charge.

In the embodiment described above, VCCD
An empty packet is transferred at a speed sufficiently higher than the speed at which charges are transferred to the CCD, for example, several times to several tens times faster.
Can be distributed within. For this reason, the position of the electric charge taken into the upper part of the VCCD also changes promptly. By moving the position without stopping the charge at a fixed position, the generation of dark current is reduced, and the generation of a fixed pattern is prevented.

In the above embodiment, first, the HCCD
Each time a vacant packet sent to the VCCD moves a predetermined distance, charge transfer in the HCCD is performed. Until the first empty packet reaches the top of the VCCD, VC
The charges taken into the upper stage of the CD are held at the same position, and during this time, horizontal charge transfer is performed several times.

Further, power consumption can be reduced by not supplying a drive signal to unnecessary electrodes. Figure 7 shows the HCCD
Eliminates the time required for transfer and more quickly converts empty packets to V
An example is shown that can be distributed throughout the CCD. In FIG. 7, one column of VCCD and HCCD is shown in the vertical direction in the figure, and time change is shown in the horizontal direction.

The VCCD includes a pixel section 11 having the number of rows corresponding to the number of one column of the photodiode, and an empty packet section 12 not corresponding to the photodiode. In this embodiment, it is assumed that one empty packet is distributed in four rows.

For example, when the pixel section is 1036 rows, if one empty packet is distributed in four rows, charges of 259 rows overflow from the pixel section 11 downward. In order to accommodate the overflowing charges while arranging empty packets for one row in four rows, the empty packet part 12 of 324 to 325 rows is required. Note that the uncertainty for one row is V
This is caused by adjusting the length of a unit for distributing empty packets at the end of the CCD.

In cycle c0, the accumulated charges from all the photodiodes are taken into the VCCD. In this state, all the rows of the pixel section 11 of the VCCD take in the accumulated charges. In addition, although two electrodes are formed in each row,
Only the electrodes corresponding to the photodiodes are shown.

In the cycle c1, an empty packet is sent from the empty packet section 12 to the pixel section 11 of the VCCD.
In this embodiment, it is assumed that an empty packet moves four lines in one cycle. In the subsequent cycles c2 and c3, empty packets are sent to the pixel unit 11, and the fourth row from the bottom, the eighth row from the bottom, and the twelfth row from the bottom are made empty packets.

In this way, when empty packets are sequentially sent, if the empty packet part 12 has 324 rows, the cycle c
In 258, the charge overflowing from the pixel unit 11 to the empty packet unit 12 by sending the empty packet reaches the bottom row of the empty packet 12.

In the next cycle c259, at the same time as another empty packet is sent to the VCCD, the accumulated charges overflowing from the VCCD are transferred to the HCCD 5. Here, the charges transferred to the HCCD 5 are transferred in the horizontal direction, and an image for one row is read.

Subsequent cycles c260, c261,...
In each case, HCCD is transferred by HCCD image transfer.
The empty packets formed in the CD are sequentially sent to the empty packet section 12 of the VCCD 2, whereby the accumulated charges of each row are transferred to the HCCD, and the image signals are read by transferring the charges in the horizontal direction.

When empty packets begin to accumulate in the upper part of the VCCD, no drive signal is supplied to the empty packet portion. That is, a non-transfer area is formed from cycle C262, and is sequentially expanded downward.

In this embodiment, an empty packet is
The process of distributing to D is performed in the vertical blanking period VBLK, and reading of the image signal of each row is performed in the subsequent H scanning period. Since the charge transfer in the VCCD in this embodiment is performed in units of four rows, it can be performed by an eight-phase drive signal.

FIG. 8 is a circuit diagram showing the entire solid-state imaging device including the CCD shown in FIG. VCCDs 2 are arranged corresponding to the respective columns of the photodiodes 1 distributed in a matrix. The VCCD 2 includes a pixel unit 11 arranged in a region where photodiodes are distributed and an empty packet unit 12 arranged in a region where no photodiode is present. VC
An HCCD 5 is arranged at an end of the empty packet section 12 of the CD, and a charge signal is read out via an output amplifier 16.

On the left side of the pixel section 11, a control circuit 17 for supplying a charge holding signal to a row to which no drive signal is applied is arranged. On the right side of the pixel section 11, a control circuit for executing charge transfer in the VCCD is provided. A circuit 18 is provided. The control circuit 17 includes a photodiode 1 and a VCCD 2
And a circuit for applying a signal φ _FS for performing a field shift for taking in electric charges.

Control circuit 18 includes wiring and switching transistors for providing eight-phase control signals V1 to V8 for realizing eight-phase driving, and microcomputer 19 for supplying signals for controlling the switching transistors. The microcomputer 19 has essentially the same function as the microcomputer 9 shown in FIG.

FIG. 9 is a timing chart of a control signal for performing charge transfer in the circuit of FIG. FIG.
(A) shows control signals φ _FS , φ _IN ,
φ _G , φ _A , φ _B , φ _RS , V1 to V8 and H1, H2
Is shown. For example, the period between pulses at which the control signals φ _FS 1 and 3 rises is, for example, one vertical period of about 110 msec, and the control signals φ _G and
The period during which φ _A and φ _B change indicates a period during which charge transfer is performed from the pixel portion to the empty packet portion and empty packets are distributed to the VCCD, for example, a period of about 2.6 msec.

In each subsequent horizontal blank period, V
In the CCD, charge transfer is performed in units of four rows. One horizontal period is, for example, about 105 μsec.
The control signals V1 to V8 applied to the four rows and eight electrodes are shown enlarged in FIG. 9B.

The control signals V1 to V8 alternately take the low level L and the middle level M, and change with a shift of a half pulse width from the control signal V1 when performing charge transfer. By such a control signal, the accumulated charge moves down by one row and the empty packet moves up by four rows in four rows corresponding to V1 to V8. With such a driving method, FIG.
Can be realized.

FIG. 10 shows a charge transfer according to another embodiment of the present invention. In FIG. 10, one column of VCC in the vertical direction
D2 and HCCD5 are shown, and a temporal change is shown in the horizontal direction. In this embodiment, as in the embodiment shown in FIG.
An empty packet is sent into the CD, and, as in the embodiment shown in FIG.
2 is provided, and the charge overflowing from the pixel unit 11 is stored in the empty packet unit 12.

For this reason, it is not necessary to perform charge transfer in the HCCD until the charge overflows from the empty packet 12, and it is possible to transfer the empty packet to the VCCD upper end in a shorter time as compared with the embodiment shown in FIG. it can.

Further, the drive signal in the VCCD need only be given to a portion to which electric charges are to be transferred, and the distance between empty packets can be set arbitrarily. For this reason, even if the distance between empty packets is set as long as several tens of lines, charge transfer in the VCCD can be realized by, for example, four-phase driving.

When empty packets start to accumulate in the upper part of the VCCD, the drive signal of the VCCD is sequentially turned off from the upper side as in the above-described embodiment. Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0121]

As described above, according to the present invention,
When charge transfer in the VCCD advances and empty packets begin to accumulate on the opposite side of the HCCD, the supply of unnecessary drive signals is stopped to reduce power consumption.

Further, in a system in which all charges are taken into the VCCD at once from the photoelectric conversion element and are sequentially transferred to the HCCD and image signals are read out, the position of the charges in the upper portion of the VCCD can be quickly moved. Is suppressed, and the occurrence of fixed pattern noise is prevented.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a domino charge transfer according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of a CCD imaging device that performs the charge transfer of FIG.

FIG. 3 is a diagram illustrating a driving circuit for performing the driving of FIG. 1; FIG. 3A is a block diagram of a driving circuit, and FIG.
FIG. 3B is a signal waveform diagram, and FIG. 3C is a block diagram of another driving circuit.

FIG. 4 is a conceptual diagram of charge transfer according to another embodiment of the present invention.

FIG. 5 is a potential diagram for explaining charge transfer in the VCCD in the embodiment of FIG. 4;

FIG. 6 is a timing chart of a control signal for realizing charge transfer in the embodiment of FIG.

FIG. 7 is a conceptual diagram illustrating a solid-state imaging device according to another embodiment of the present invention.

8 is a circuit diagram showing the entire solid-state imaging device including the CCD shown in FIG. 7;

FIG. 9 is a timing chart of a control signal for realizing charge transfer in the embodiment of FIG. 7;

FIG. 10 is a conceptual diagram of a solid-state imaging device according to another embodiment of the present invention.

FIG. 11 is a conceptual diagram illustrating an accordion transfer method according to a conventional technique.

FIG. 12 is a conceptual diagram illustrating an FIT pseudo-frame electronic shutter according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 photodiode (photoelectric conversion element) 2 VCCD 3, 4 VCCD electrode 5 HCCD 6 empty packet 7 transfer gate 8 output amplifier 9 microcomputer 10 control circuit 11 pixel section 12 empty packet section 16 output amplifier 17, 18 control circuit 19 microcomputer

Claims (3)

(57) [Claims] 1. A photoelectric conversion device comprising: a plurality of photoelectric conversion elements arranged in a matrix; and a plurality of columns of vertical rows arranged adjacent to each row of the photoelectric conversion elements and capable of taking in charges accumulated in the photoelectric conversion elements. A vertical CCD connected to the plurality of columns of the vertical CCDs and capable of receiving charges transferred from the vertical CCDs in parallel and outputting the charges in series; each of the vertical CCDs having an m-stage configuration; A method for driving a solid-state imaging device in which each stage is constituted by k rows, wherein a step of capturing all charges accumulated in the plurality of photoelectric conversion elements into a vertical CCD, and applying a drive signal to the vertical CCD. Then, the charges taken from the photoelectric conversion elements are sequentially transferred to the horizontal CCD, and
A transfer step of sending empty packets in which no charge exists from the CD to each of the vertical CCDs. During a period in which charge transfer for one row is performed in the horizontal CCD, empty packets are stored in the vertical CCD for two or more rows. Move the vertical CC
In the area where empty packets of D are distributed, a drive signal that changes the voltage is supplied only to the stage that moves the empty packet, and the drive signals of the other stages do not change the voltage, and the end of the vertical CCD where the electric charge is emptied. , A driving method of the solid-state imaging device for stopping the driving signal. 2. A plurality of photoelectric conversion elements arranged in a matrix and a plurality of vertical columns arranged adjacent to each column of the photoelectric conversion elements and capable of taking in charges accumulated in the photoelectric conversion elements. A CCD which is connected to the plurality of columns of vertical CCDs, and which can receive in parallel electric charges transferred from the vertical CCDs and output them in series, wherein the vertical CCDs are rows of a matrix of photoelectric conversion elements. It has several pixel portions and an empty packet portion connected to the pixel portion and having a smaller number of rows than the number of rows of the pixel portion, and an end of the empty packet portion is connected to the horizontal CCD. A method of driving a solid-state imaging device, comprising: a step of taking in all the electric charges accumulated in the large number of photoelectric conversion elements into a pixel portion of a vertical CCD; and Is the vertical CCD pixel And accumulating the accumulated charge overflowing from the pixel portion in the empty packet portion. Applying a drive signal to the vertical CCD, sequentially transferring the charge taken from the photoelectric conversion element to the horizontal CCD, and emptying the vertical CCD. A transfer step of sequentially stopping the drive signal at an end of the CCD. 3. A plurality of photoelectric conversion elements arranged in a matrix, and a plurality of columns of vertical rows arranged adjacent to each column of the photoelectric conversion elements and capable of taking in electric charges accumulated in the photoelectric conversion elements. Each of the vertical CCDs includes a pixel portion corresponding to the number of rows of a matrix of photoelectric conversion elements, and an empty packet portion connected to the pixel portion and having a smaller number of rows than the number of rows of the pixel portion. A plurality of vertical CCDs having: a horizontal CCD that is connected to the plurality of columns of vertical CCDs at an end on the side of the empty packet section and that can receive charges transferred from the vertical CCDs in parallel and output them in series And take in the accumulated charge from all photoelectric conversion elements into the vertical CCD,
A control circuit for introducing one empty packet row for every three or more rows of the vertical CCD; applying a drive signal to the vertical CCD;
A drive circuit for stopping supply of a drive signal to a portion of the vertical CCD where empty packets are stored when empty packets start to be stored at an end of D;