JP3097620B2 - Scanning reduction projection exposure equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a scanning reduction projection exposure apparatus and an exposure method , and more particularly to a scanning reduction projection exposure apparatus and an exposure method using ultraviolet rays and far ultraviolet rays.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, an exposure apparatus is used to form a pattern on a semiconductor substrate (hereinafter, referred to as a wafer).

In recent years, in a semiconductor integrated circuit having a large area, a scanning reduction projection exposure apparatus has been used for forming a pattern on a wafer.

FIG. 1 schematically shows an example of a scanning reduction projection exposure apparatus. In the figure, an exposure light 101 is transmitted from a light source 102 to a reflecting mirror 103, a fly-eye lens 104, an aperture stop 105, a reticle blind 106, and a reflecting mirror 10.
7. The wafer 112 on the wafer stage 111 is irradiated with a desired exposure amount through the condenser lens 108, the reticle 109, and the projection lens 110 in this order. At this time, the exposure visual field has a slit shape of about 25 × 8 mm, and a maximum of 2 mm is obtained by synchronously scanning the reticle blind 106, the reticle stage 113 and the wafer stage 111.
The reticle 1 is placed on the wafer 111 in an area of about 5 × 30 mm.
09 is formed. This is the wafer stage 1
11 to move the wafer 20 as shown by the arrow in FIG.
By repeatedly scanning over the wafer 1, the pattern on the reticle 109 is repeatedly exposed on the entire surface of the wafer 112.

As described above, the accuracy of the synchronous control when performing the synchronous scanning exposure has a great influence on the imaging performance. Synchronous control detects the positions of the reticle stage 113 and the wafer stage 111 using laser interferometers 115 and 117 provided on the reticle stage 113 and the wafer stage 111, respectively, and the control unit 118 controls the reticle stage moving mechanism 114 and the wafer stage moving mechanism. 116 is controlled.

For example, when the scanning speed of the wafer stage is 80
mm / sec, the scanning speed of the reticle stage 113 is 3
In the case of 20 mm / sec, the 8 mm slit
The time for passing through one point on 12 is 0.1 sec. During this 0.1 second, the difference calculated from the positions of the reticle stage 113 and the wafer stage 111 measured by the laser interferometers 115 and 117 installed on each stage is the difference between the wafer stage 111 and the reticle stage 1.
13 is the synchronization control accuracy. The average value of the differences between 0.1 sec determines the imaging position of the pattern. Further, the amplitude of the difference leads to blurring of image formation of the pattern, that is, a reduction in resolution and a reduction in the depth of focus. This difference, that is, the synchronization control accuracy is almost proportional to the scanning speed. FIG. 4 shows the relationship between the wafer stage scanning speed and the maximum amplitude of the difference. The allowable value of the maximum amplitude differs depending on the exposure wavelength, the NA of the projection lens, the type of pattern, and the line width. For example, by KrF excimer exposure, using a projection lens with NA = 0.6, 0.20
The maximum allowable amplitude for forming μmL / S is 30n
m. The maximum scanning speed of the wafer stage 111 is determined so that the maximum amplitude does not exceed the maximum allowable amplitude. Although the maximum amplitude varies depending on the scanning position of the wafer stage 111 due to the mechanical characteristics of the exposure apparatus, the maximum amplitude is less than an allowable value because conventionally, only the function of exposing the entire wafer at the same scanning speed is provided. The maximum scanning speed is determined so as to satisfy the above. In the case where a chip as shown in FIG. 5 is formed on the wafer surface, the wafer stage scanning maximum speed at which the maximum amplitude can be reduced to 30 nm or less in the in-wafer regions A, B, C, D, and E is as follows: 60, 40, 100, 120, 80 respectively
nm / sec, the maximum scanning speed of the wafer stage is set to 40 mm / sec over the entire surface of the wafer.

[0007]

However, such a conventional scanning-type reduction projection exposure apparatus has a problem in that the processing capability is low.

The reason is that the maximum scanning speed is set to a value such that the maximum amplitude of the synchronization control accuracy does not exceed an allowable value over the entire surface of the wafer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scanning reduction projection exposure apparatus and an exposure method having a high processing capability in view of the above problems.

[0010]

In order to achieve the above object, a scanning type reduced projection exposure apparatus according to the present invention comprises a scanning type reduced projection exposure apparatus for exposing a semiconductor substrate by synchronously scanning a semiconductor substrate and a mask. in the exposure apparatus, a semiconductor
The semiconductor substrate and the mask run for each chip position in the substrate.
Means for determining the maximum inspection speed, and scanning for each chip position
Means for storing the maximum speed .

Further, according to the present invention, there is provided an exposure method comprising the steps of:
And the mask is scanned synchronously to the semiconductor substrate.
Exposure method using a scanning type reduction projection exposure apparatus that performs exposure
There are, the semiconductor chip by chip position in the semiconductor substrate before exposure
Determining the maximum scanning speed of the body substrate and the mask
And a step for storing the maximum scanning speed for each chip position.
And

The semiconductor substrate and the mask are scanned synchronously.
To expose each chip position on the semiconductor substrate
The scanning speed is set to the maximum scanning speed at each chip position.
The exposure is performed by setting .

The semiconductor substrate and the mask are synchronously scanned.
To expose each chip position on the semiconductor substrate
Automatically detects the synchronization control accuracy and confirms the synchronization control accuracy.
Set the scanning speed to the maximum scanning speed that can be maintained and
Is what you do .

Further, the semiconductor substrate and the mask are scanned synchronously.
To expose each chip position on the semiconductor substrate
In addition, synchronization control accuracy is allowed in the n-th chip (n = 1, 2,...)
If it deviates from the value, it will run during the next (n + 1) th chip exposure.
The exposure is performed with the inspection maximum speed lowered at a predetermined ratio .

In the present invention, the maximum scanning speed is determined by the synchronization control accuracy for each scanning exposure position in the wafer.
The wafer exposure process can be performed with the maximum throughput while the synchronization control accuracy is secured.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

In the scanning type reduction projection exposure apparatus shown in FIG. 1, exposure light 101 is transmitted from a light source 102 to a reflecting mirror 103, a fly-eye lens 104, an aperture stop 105, a reticle blind 106, a reflecting mirror 107, a condenser lens 108, and a reticle 109. The wafer 112 on the wafer stage 111 is irradiated with a desired exposure amount through the projection lens 110 in order. At this time, the exposure field of view is 25
The slit has a shape of about 8 mm, and a pattern on the reticle 109 is formed on the wafer 112 in a region of up to about 25 × 30 mm by synchronously scanning the reticle blind 106, the reticle stage 113, and the wafer stage 111. This is moved to the wafer stage 111,
By repeatedly scanning the wafer 1 as shown in FIG.
The point that the pattern on the reticle 109 is repeatedly exposed on the entire surface 12 is the same as the conventional case.

In the synchronous control, the positions of the reticle stage 113 and the wafer stage 111 are detected by the laser interferometers 115 and 117 provided on the reticle stage 113 and the wafer stage 111, respectively. Stage moving mechanism 11
4 and the wafer stage moving mechanism 116 are controlled.

In the present invention, the maximum scanning speed is determined from the synchronization control accuracy for each scanning position in the wafer. The synchronization control accuracy in the wafer plane is measured in advance by the procedure shown in FIG. 3, and the maximum scanning speed for each chip in the wafer plane is determined. That is, in the present invention, as shown in FIG. 3, (1) exposure condition setting input in the wafer is performed.
(2) Set the wafer on the wafer stage of the exposure apparatus. (3) The exposure operation is performed over the entire surface of the wafer, and simultaneously the synchronization control accuracy is measured. (4) For each step, the maximum scanning speed of each chip in the wafer is determined from the desired synchronization accuracy. (5) Store the maximum scanning speed of each chip in the exposure apparatus. (6) The wafer is exposed in the order of the wafer exposure steps.

FIG. 4 shows the relationship between the scanning speed of the wafer stage and the maximum amplitude of the difference between the position of the wafer stage and the position of the reticle stage. The maximum wafer stage scanning speed at which the maximum amplitude can be reduced to 30 nm or less in the chips of the in-wafer regions A, B, C, D, and E is 60, 40, 100, 120,
Since it is 80 nm / sec, scanning exposure is performed on each chip at the maximum scanning speed as shown in FIG.

According to the present invention, the scanning exposure time can be reduced by about 50% as compared with the prior art. Considering this, including the alignment and the wafer exchange time, it is possible to improve the processing capacity by about 30% with one wafer.

However, when the installation environment of the scanning reduction projection exposure apparatus, particularly the vibration environment, changes, the synchronization control accuracy may change. In preparation for such a case, the control unit 118 always recognizes a change in the synchronization control accuracy, and automatically adjusts the maximum scanning speed for each scanning exposure position (chip) so that the synchronization control accuracy falls within an allowable value. The operation is shown in FIG. At the time of each chip exposure at the position, the synchronization control accuracy is also monitored. In FIG. 7, the n-th chip (where n = 1, 2, 2)
..), The synchronization control accuracy deviates from the allowable value, the maximum scanning speed is set to, for example, 10 at the next (n + 1) th chip exposure.
Exposure is performed with the percentage lowered. As a result, it is possible to prevent the synchronization control accuracy from being reduced in the next chip. Therefore, in the case of the present embodiment, there is an advantage that it is possible to cope with a change in the installation environment of the apparatus.

[0023]

As described above, in the scanning type reduced projection exposure apparatus of the present invention, the throughput can be improved by changing the maximum scanning speed for each scanning exposure position.

[Brief description of the drawings]

FIG. 1 is a schematic view of a scanning type reduction projection exposure apparatus of the present invention and a conventional technique.

FIG. 2 is an example of scanning exposure of a wafer.

FIG. 3 is an operation diagram of one embodiment of the present invention.

FIG. 4 is a relationship diagram between a wafer stage scanning speed and a maximum amplitude according to the present invention.

FIG. 5 is a diagram showing an area in a wafer according to the present invention.

FIG. 6 is a diagram showing an in-wafer area and a maximum scanning speed according to the present invention.

FIG. 7 is an operation diagram of another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101 Exposure light 102 Light source 103, 107 Reflecting mirror 104 Fly array lens 105 Aperture stop 106 Reticle blind 108 Conductor lens 109 Reticle 110 Reduction projection lens 111 Wafer stage 112 Wafer 113 Reticle stage 114 Reticle stage moving mechanism 115 Laser interferometer 116 Wafer stage Moving mechanism 117 Laser interferometer 118 Control unit 201 Wafer

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 7/22

Claims (5)

(57) [Claims] 1. A scanning-type reduced projection exposure apparatus which performs exposure on a semiconductor substrate by scanning in synchronization with the semiconductor substrate and the mask, the semiconductor substrate and the mass for each chip position in the semiconductor substrate
Means for determining the maximum scanning speed of the chip , and means for storing the maximum scanning speed for each chip position.
Scanning reduction projection exposure apparatus, characterized in that was e. 2. A synchronous scanning of a semiconductor substrate and a mask.
Scanning projection exposure that exposes the semiconductor substrate by
In an exposure method using an optical device , the semiconductor substrate is provided for each chip position in the semiconductor substrate before exposure.
Determining the maximum scanning speed of the mask, and storing the maximum scanning speed for each chip position;
An exposure method comprising : 3. A synchronous scanning of a semiconductor substrate and a mask.
Exposure to each chip position on the semiconductor substrate
The scanning speed is set to the maximum scanning speed at each chip position.
The exposure method according to claim 2 , wherein the exposure is performed by setting . 4. A synchronous scanning of a semiconductor substrate and a mask.
Exposure to each chip position on the semiconductor substrate
Automatically detects the synchronization control accuracy and confirms the synchronization control accuracy.
Set the scanning speed to the maximum scanning speed that can be maintained and
The exposure method according to claim 3, characterized in that. 5. A synchronous scanning of a semiconductor substrate and a mask.
Exposure to each chip position on the semiconductor substrate
In addition, synchronization control accuracy is allowed in the n-th chip (n = 1, 2,...)
If it deviates from the value, it will run during the next (n + 1) th chip exposure.
5. The exposure method according to claim 3, wherein the exposure is performed with the inspection maximum speed lowered at a predetermined ratio .