JP3095769B2 - VSELP encoder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VSELP encoder for VSELP-encoding an audio signal by a processing device having a product-sum operation function.

[Prior Art] The VSELP speech coding method is a type of code-excited new predictive coding (CELP) that parameter-codes speech into a vocal tract and a vector-quantized excitation source. It is standardized as a speech coding method for cellular.

The following document A describes a conventional VSELP coding method.

Reference A: “Vector Sum Excited Linear Prediction (VS
ELP) Speech Coding at 8Kbps ", Ira A.Gerson & Mark
A.Jasiuk, Proc.IEEE Int.on.on Acoustics, Speech and
Signal Processing, pp. 461-464, April 1990 Hereinafter, a conventional technique of the VSELP encoding method will be described based on Document A.

The VSELP encoder in the conventional VSELP encoding method is LPC
The configuration includes an analyzer, a target signal generator, a long term lag selector, a code 1 selector, a code 2 selector, and a gain selector.

The LPC analysis unit converts the input audio signal V every 160 samples.
An LPC analysis is performed to obtain an LPC coefficient k and a voice average power R. Further, the LPC coefficient k and the voice average power R are quantized and interpolated for a subframe composed of 40 samples to obtain an LPC coefficient k _j And voice average power R ₀ are output.

Then, the target signal creation unit creates a residual signal of the input voice signal V by an analysis filter using the LPC coefficient k _j for each subframe, and generates the LPC coefficient k _j
Is applied to the residual signal, and the effect of the excitation signal ex synthesized in the previous sub-frame is removed to generate and output the target signal p.

The long-term lag selection unit updates the internal value long-term filter state with the excitation signal ex of the previous subframe, and squares the difference between the target signal p and the internal value long-term filter state using a weighting filter. seeking the optimum lag to calculate the error, and outputs the long-term code c ₀ by the lugs.

The code 1 selecting unit combines the fixed data internally stored as the basis vector v with the gray code θ to create a code vector u,
By applying a weighting filter using a P coefficient k _j to create a signal f ₀ ′ orthogonalized to the long-term code c ₀ , and evaluating the square error of the difference between the f ₀ ′ and the target signal p, select code 1 code c ₁ of the optimum output.

The code 2 selector stores a basis vector v 'different from the code 1 selector.

The code 2 selecting unit combines the basis vector v ′ with the gray code θ to create a code vector u ′, applies it to a weighting filter using the LPC coefficient k _j, and orthogonalizes the long term code c ₀ . And the optimal code obtained from the code 1 selector
'make, f _1' signal f ₁ orthogonal with respect to c ₁ to evaluate the squared error of the difference between the target signal p, and selects and outputs the optimum code 2 code c _2.

The gain selection unit receives the LPC coefficient k _j , the average sound power R ₀ , the target signal p, the long-term code c ₀ , the code 1 code c ₁ , and the code 2 code c ₂ , and based on these input signals, Select the optimal set from the parameters (GS, P0, P1) on the vector table in the gain selector,
Gains β, γ ₁ , γ ₂ calculated by the parameters
Is output.

These gains β, γ ₁ , γ ₂ correspond to the codes c ₀ , c ₁ ,
It is a gain for synthesizing an excitation signal ex by combining c _2.

The aforementioned codes c ₀ , c ₁ , and c ₂ are amplified by the aforementioned gains β, γ ₁ , and γ ₂ , respectively, and the amplified codes are added to form a combined excitation signal ex for the current subframe. Will be generated.

The generated synthesized excitation signal ex is used for synthesizing the target signal for the next subframe and updating the long-term filter state.

In the VSELP encoder as described above, L obtained from the input speech
The PC coefficient k _j , the average audio power R ₀ , the long term lag L, the code 1 index I, the code 2 index J, and the gain index are transmitted to the composite device.

In addition, the VSELP composite device in the conventional VSELP coding scheme forms a synthesis filter from the received LPC coefficient _kj, and decodes a long-term code c ₀ from the long-term filter state prepared by the encoder and the received lag L. And the basis vector v stored in the encoder and the received code 1
Decoding the codes one code c ₁ from the index I, decodes the code 2 code c ₂ from another basis vector v and code 2 index J, and the received vector quantization table (GS, P0, P1) gain The gains β, γ ₁ , γ ₂ for each code are decoded from the index.

Then, the decoded codes c ₀ , c ₁ , c ₂ and the gains β, γ ₁ ,
γ ₂ and the combined excitation signal ex for the current subframe
Are synthesized, and the input excitation signal V is decoded by applying the synthesized excitation signal ex to a synthesis filter constituted by the received LPC coefficients k _j . And the decoded audio signal is LPC
The noise is further compressed by a post filter configured using the coefficient k _j and output. Now, the long term lag selecting unit in the conventional VSELP coding method described above will be described in more detail.

The excitation signal (long-term filter state) stored in the long-term lag selection unit is defined as r (−1). Here, r is the excitation signal synthesized in the previous subframe.

For example, when the subframe is composed of N samples, N samples from r (−N) to r (−1) are excitation signals synthesized in the previous subframe, and r (−2N) to r (−N). N samples of (N-1) are synthesized in the previous and previous subframes.

The long-term lag selector selects various lugs
A long term code composed of N samples from (−1) to r (−1 + N) is extracted, and a process of selecting the most appropriate one from among the target signals of the current subframe is performed.

For this selection, first, a process of applying a weighting filter to the long term code is performed.

This processing is performed by approximating the impulse response h (n) of the weighting filter, which is the synthesis filter, by convolution.

Assuming that a signal obtained by convolving the long term codes r (−1) to r (−1 + N) corresponding to the lag l with h (n) is z (l, n), However, in this equation, n is 0 ≦ n <N, l is 1 ≦ l
It is.

 Then, the following recursive formula is obtained from the above formula.

z (l, n) = z (l−1, n−1) + r (−1) h (n) (2) where n is 1 ≦ n <N, l is 2 ≦
l.

Also, the impulse response h is truncated at the _NT order,
h (N _T ) to h (N−1) are all set to 0. as a result,
The above equation is divided as follows.

When n is 1 ≦ n < _NT and 1 is 2 ≦ l, z (l, n) = z (l−1, n−1) + r (−1) h (n) and n Is N _T ≦ n <N and 2 ≦ l, z (l, n) = z (l−1, n−1) where the search range of the lag l is L _min ≦ l ≦ L _max .

Accordingly, z is calculated from the above equation through the following procedure.

However, in the formula, n is 0 ≦ n <N.

z (l, 0) = r (−1) · h (0) where l is L _min <l ≦ L _max .

z (l, n) = z (l-1, n-1) + r (-1) h
(N) In the formula, n is 1 ≦ n <N _T , and 1 is
L _min <l ≦ L _max .

z (l, n) = z (l−1, n−1) where n is _NT ≦ n <N and l is
L _min <l ≦ L _max .

An optimal lag is selected by obtaining a signal b ′ _L that has been subjected to a weighting filter using z obtained by the above formula and evaluating the square error of the difference between b ′ _L and the target signal p.

[Problems to be Solved by the Invention] By the way, in order to realize the VSELP coding method, it is conceivable to use a high-speed signal processing device.

In many cases, a signal processing device has a plurality of m-bit registers and (2m + α) -bit accumulators, finds the product of the contents of one register and the contents of another register, and calculates the product of the product and the contents of the accumulator. After obtaining the sum, it has a product-sum operation function of storing the sum in the accumulator.

Using this function, for example, convolution operation
After repeating the multiply-accumulate operation as appropriate, m in the accumulator
The calculation is performed by extracting bits and storing the result in a memory or the like.

However, according to the calculation method of the prior art, when convolving the long-term filter state r with h to obtain z, once z (L _min , n) and z (l, 0) are once obtained, , L _min <l ≦ L _max , and a recursive formula for z (l, n) is obtained, which is obtained by performing a product-sum operation (2m +
α) bits of data z (L _min , n) are stored once in memory with m-bit precision, then transferred to the accumulator again, and the product-sum operation to obtain z (l, n) is resumed. Therefore, there are two problems that the calculation accuracy is reduced on the way and that the processing time is increased by the extra transfer on the way.

The present invention has been made in view of the above circumstances, and when the long-term lag selecting unit convolves the long-term filter state r with h to obtain z, the calculation accuracy does not decrease during the calculation, and An object of the present invention is to provide a VSELP encoder capable of obtaining the above z without performing extra transfer on the way.

[Means for Solving the Problems] A VSELP encoder according to the present invention includes a long-term lag selecting section having a processing device having a product-sum operation function, and a long-term lag selecting section selects an optimal long-term lag. The processing of convolving the filter state r (l) with the impulse response h (n) to obtain z (l, n) is executed by a processing device having a product-sum operation function, and the audio signal is VSELP-encoded. is there.

Specifically, when the arithmetic processing for obtaining z (l, n) is repeated while changing the combination of l and n, both the values of l and n in the series of arithmetic processing executed earlier are set to one. It is characterized in that the next operation is performed with the increased value.

[Operation] The VSELP encoder according to the present invention employs a long-term filter state r to select a long-term lag.
(L) is convolved with the impulse response h (n) to obtain z (l,
When the calculation process for obtaining n) is repeated, z
The values obtained by increasing the values of l and n with respect to by 1 each are the values of l and n of z to be calculated next.

In such an encoder, an m-bit register and (2m
+ Α) When the arithmetic operation of z is repeated by a processor that performs a product-sum operation using an accumulator of bits, the contents of the accumulator having a large bit length are transferred to a memory having a small bit length during a series of operations. The calculation for the next z can be performed in sequence without any delay, so that the calculation accuracy does not decrease during the calculation due to the data transfer to the memory, and the extra transfer does not need to be performed during the calculation. It can also be shortened.

[Embodiment] FIG. 1 shows a specific example of a process of a main part in an embodiment of a VSELP encoder according to the present invention.

The VSELP encoder according to this embodiment has a long term lag selecting unit having a z term that is longer than that of the conventional VSELP encoding method.
, That is, the calculation order when z is obtained by convolving the long-term filter state r with h.

In the VSELP encoder of this embodiment, the operation of z (l, n) in the long term lag selector is divided into the following three cases (I) to (III) according to the value of l, and in each case By repeating a series of processes as appropriate for each time,
Desired z (l, n) is obtained. In any case, when a series of processing is repeated, both l and n are both increased by one.

That is, when a series of processing is repeated, if z (l ₁ , n ₁ ) is obtained by setting l = l ₁ , n = n _{1 in} the previous series of processing, the subsequent series of processing is repeated. , L = l ₁
+ 1, as n = n ₁ +1, is to compute the _{z (l 1 + 1, n} 1 +1).

(I) When 1 is smaller than L _min , the following processes [A] and [B] are sequentially executed as a series of processes.

Processing [A] According to the given l and n, r (-l) on the memory is stored in the register A and h (n) on the memory is stored in the register B.

Process [b] This process is a so-called product-sum process in which the product of the value stored in the register A and the value stored in the register B is calculated, and the value of the accumulator is added to the calculated product value. , And returns the result to the accumulator.

(II) When 1 is equal to or more than L _min and n is smaller than _NT , the following processes [c], [d], and [e] are sequentially executed as a series of processes.

Process [c] This process corresponds to the process [a] described above. That is, according to given l and n, r on the memory
(−l) is stored in the register A, and h (n) on the memory is stored in the register B.

Processing [d] This processing is a so-called sum-of-products processing, and corresponds to the above-described processing [b]. That is, the product of the value stored in the register A and the value stored in the register B is calculated,
Further, the accumulator value is added to the calculated product value,
The result is returned to the accumulator.

Process [e] This process is a so-called transfer process, in which the value stored in the accumulator in the above process [d] is z (l, n).
Transfer as

(III) When 1 is equal to or greater than L _min and n is equal to or greater than _NT , only the following process (f) is executed.

Process [f] This process is a so-called transfer process in which the value stored in the accumulator is transferred as z (l, n).

Note that the above-described process [a] or [c] is an initial setting process depending on the value of l or n, and is replaced by any of the following processes [i] or [ii] depending on the value of l or n.

Process [i] This is a process in which l is not "1" but n is "0". According to given l and n, r (-
1) is stored in the register A, h (0) on the memory is stored in the register B, and the value "0" is stored in the accumulator.

Process [ii] This is a process in which n is not “0” but l is “1”. According to given l and n, r (−
1) is stored in the register A, h (n) in the memory is stored in the register B, and the value "0" is stored in the accumulator.

Next, FIG. 1 specifically showing the above-described processes (I) to (III) and processes [i] and [iii] will be described.

In FIG. 1, the horizontal axis represents the value of “l” for calculating z, and the vertical axis represents the value of “n”.
And the values of l and n when calculating.

In FIG. 1, the arrow "" indicates the calculation order of z (l, n) by the process (I), the arrow "⇒" indicates the calculation order of z (l, n) by the process (II), and the arrow "→" Indicates the calculation order of z (l, n) in the process (III).

Further, the "○" mark by symbol Q ₁ a corresponding part of the process described above [i], subjected was "○" mark code Q ₂ is relevant part of the process described above [ii].

FIG. 1 shows that, for example, when z (−2,0) is calculated, z (−3,1) is calculated, and then z (−3,1) is calculated.
(−4,2) is calculated. Also, for example, when z (−3,36) is calculated, next, z (−4,
37), and then z (−5,38).

As described above, in one embodiment, the values of l and n previously calculated are each increased by 1, and the values of l and n of z to be calculated next are the values of such calculations. Proceed with the process.

Therefore, when the above-mentioned operation of z is repeated in a processor which performs a product-sum operation using an m-bit register and an (2m + α) -bit accumulator, the contents of the accumulator having a large bit length are converted into a bit length during a series of operations. It is possible to sequentially shift to the operation for the next z without transferring to a memory having a small size, so that the data transfer to the memory does not reduce the calculation accuracy in the middle of the calculation, and extra transfer is performed in the middle of the calculation. Since it is not necessary, the calculation time can be shortened.

[Effect of the Invention] The VSELP encoder according to the present invention uses a long-term filter state r to select a long-term lag.
(L) is convolved with the impulse response h (n) to obtain z (l,
When the calculation process for obtaining n) is repeated, z
The values obtained by increasing the values of l and n with respect to by 1 each are the values of l and n of z to be calculated next.

In such an encoder, an m-bit register and (2m
+ Α) When the arithmetic operation of z is repeated by a processor that performs a product-sum operation using an accumulator of bits, the contents of the accumulator having a large bit length are transferred to a memory having a small bit length during a series of operations. The calculation for the next z can be performed in sequence without any delay, so that the calculation accuracy does not decrease during the calculation due to the data transfer to the memory, and the extra transfer does not need to be performed during the calculation. It can also be shortened.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a calculation procedure in one embodiment of the present invention.

Continuation of the front page (56) References JP-A-4-190399 (JP, A) Proceedings of IEEE 1990 International Conference on Acoustics, Speech and Signal Processing, Vol. 1, "S9.3 Vector or Sum Excited Line near Prediction (VSE LP) Speech Coding at 8 kbps" p. 461-464, April 3-6, 1990 (58) Fields investigated (Int. Cl. ⁷ , DB name) G10L 11/00-13/08 G10L 19/00-21/06 INSPEC (DIALOG) JICST file ( JOIS) WPI (DIALOG)

Claims (1)

(57) [Claims] An LPC analysis unit that analyzes an audio signal to calculate an LPC coefficient and an average audio power; a target signal generation unit that generates a target signal based on the LPC coefficient and the audio signal; Based on the LPC coefficient, the target signal, and the long-term filter status, select an optimal long-term lag, and output a long-term lag selecting unit that outputs an optimal long-term code corresponding to the optimal long-term lag; A code selector that outputs an optimal code based on the LPC coefficient, the target signal, and the optimal long-term code; and the LPC coefficient, the audio average power, the target signal, the optimal long-term code, and the optimal code. Based on the optimal long-term code and the gay code corresponding to the optimal code, respectively. A long term lag selector, comprising: a processing device having a product-sum operation function, for selecting the optimum long term lag. When the long-term filter state is convoluted with an impulse response to execute a series of arithmetic processing for obtaining z (l, n), and when the combination of l and n is changed and repeated, a series of previously executed L in arithmetic processing
A VSELP encoder characterized by increasing both values of n and n one by one and performing the next operation with the increased values.