JP3092219B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of forming a contact in a large capacity NAND type mask ROM having a submicron gate electrode.

[0002]

2. Description of the Related Art In recent years, MIS has been developed to increase the capacity of a mask ROM.
Transistors having a multi-gate structure in which the threshold voltage of the transistor is controlled by the type and concentration of impurities in the channel region, for example, are described in the IEICE Technical Report, SSD7
As described in the article "Characteristics of Multi-Gate Transistor ROM" in Vol. 9-21, pp. 17-24,
It is being used.

A method of manufacturing a conventional multi-gate mask ROM will be described below with reference to FIGS.

First, as shown in FIG. 2A, after forming a first gate oxide film 2 on a P-type silicon substrate 1, a first polycrystalline silicon film 3a, a first tungsten silicide film 3b and a first One silicon oxide film 5a is deposited and patterned to form a first gate electrode. Next, a second silicon oxide film is deposited, and anisotropic etching is performed to form a spacer 5a.

Next, as shown in FIG. 2B, after forming a second gate oxide film 6, a second polysilicon film 8a and a second tungsten silicide film 8b are successively deposited and selectively deposited. To form a second gate electrode. Next, phosphorus is implanted using the first and second gate electrodes as a mask to form an ion implantation region 4a.

Next, as shown in FIG.
Then, phosphorus is implanted into a channel region of a predetermined first gate electrode portion or a predetermined second gate portion (by forming an ion implantation region 10a) to write data "ON".

Next, as shown in FIG. 2D, the interlayer insulating film 12 is formed.
Is deposited and reflowed to flatten the surface. Then, a contact hole is formed in the contact portion 7 by etching using a resist. Thereafter, polycrystalline silicon or the like is deposited and etched back to form a buried contact 15. Next, when an aluminum film is deposited and etched to form the electrode wiring 14, a conventional multi-gate mask ROM is obtained.

[0008]

In this conventional method for forming a contact in a multi-gate mask ROM, the second gate electrode overlaps the first gate electrode, so that the step is large, and the interlayer insulating film 12 needs to be formed. Since the aspect ratio of the contact hole becomes 1 or more because it is necessary to increase the thickness and to provide a deep contact hole extending from the surface of the interlayer insulating film 12 to the surface of the P-type silicon substrate, the polycrystalline silicon For this reason, a buried contact in which a contact hole is buried must be used. Therefore, there is a problem that the process is complicated and it is difficult to shorten the TAT (process preparation period).

[0009]

According to a method of manufacturing a semiconductor memory device of the present invention, a first polysilicon film, a first metal silicide film and a first metal silicide film are formed on a semiconductor substrate via a first gate insulating film. Forming the first insulating film sequentially, and selectively etching the first insulating film, the first metal silicide film, and the first polycrystalline silicon film to cover the surface with the first insulating film. Forming a plurality of first gate electrodes, forming a source / drain region by implanting ions of the opposite conductivity type to the semiconductor substrate using the plurality of first gate electrodes as masks, Depositing an insulating film and then etching back to form spacers on the side surfaces of the first gate electrode, and etching the semiconductor substrate using the first insulating film and the spacer as masks, respectively. Forming a trench, and forming a second gate insulating film on the side and bottom surfaces of said grooves,
A step of removing the second gate insulating film in a region where a contact is to be formed, a step of depositing a second polycrystalline silicon film and then etching back to fill a groove between the first gate electrodes; Depositing and patterning a silicide film to form a second gate electrode; and implanting ions of a conductivity type opposite to that of the semiconductor substrate into a channel region immediately below a predetermined first gate electrode portion or directly below a second gate electrode portion. Writing information by performing the following steps: forming an interlayer insulating film over the entire surface after the step; forming contact holes in the interlayer insulating film on predetermined source / drain regions, and then forming an electrode wiring. That is.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views showing a sequence of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a first gate oxide film 1 having a thickness of 10 to 26 nm is formed on a P-type silicon substrate 101.
02, a first polycrystalline silicon film 103a having a thickness of 150 nm, a first tusten silicide film 103b having a thickness of 150 nm, and a first silicon oxide film 105a having a thickness of 150 nm are deposited and patterned.
A plurality of first gate electrodes whose surfaces are covered with the first silicon oxide film 105a are formed. Next, using these first gate electrodes as a mask, phosphorous is applied at 1 × 10 5 at 30 to 50 keV.
^The source / drain regions 104 are formed by implanting ^{14 to} 3 × 10 ¹⁴ / cm ² . After that, a second silicon oxide film having a thickness of 120 nm is deposited, anisotropically etched, and spacers 105b are formed on the first gate electrodes (103a, 103b) and the side surfaces of the first silicon oxide film 105a.

Next, as shown in FIG. 1B, the P-type silicon substrate 101 is etched deeper than the source / drain region 104 using the first silicon oxide film 105a and the spacer 105b as a mask to form a groove having a depth of 150 nm. I do. After forming a second gate oxide film 106 having a thickness of 10 to 26 nm on the side and bottom surfaces of the groove, the second gate oxide film 106 of the contact formation portion 107 is etched using a resist as a mask to expose the P-type silicon substrate 101. Next, a second polycrystalline silicon film 108a having a thickness of 400 nm is deposited on the entire surface, etched back, and buried only between the first gate electrodes. Subsequently, a second tungsten silicide film 108b is deposited and selectively etched to form a second gate electrode (1
08a, 108b). The thickness between the second tungsten silicides is set to about 100 nm so that the surface of the polycide film at the center of the groove is almost as high as the surface of the first gate electrode.

Next, as shown in FIG.
9, 400 to 500 phosphorus is added to the channel region of the predetermined first gate electrode portion or the second gate electrode portion.
The data “ON” is written by implanting keV at 2 × 10 ¹³ to 4 × 10 ¹³ / cm ² (forming the ion implantation region 110). At this time, an ion implantation region 111a is formed in the contact formation portion 107.

Next, as shown in FIG. 1D, when activation and diffusion are performed by heat treatment, the ion implanted regions 110a, 110a
Numeral 11a denotes an N-type diffusion layer 110b for complete thresholding of the transistor of the deflection type connected to the source / drain region and an N-type diffusion layer 111b for the digit line.
Becomes

Next, as the interlayer insulating film 112, for example, BP
An SG film is deposited and reflowed to planarize the surface. Then, only in the contact forming portion 107, a contact hole is formed using a resist film to expose the second tungsten silicide film, an aluminum film or the like is deposited, and an electrode wiring 114 (digit line) is formed.

Since only the second tungsten silicide film of the second gate electrode overlaps with the first gate electrode via the insulating film, the thickness of the interlayer insulating film 112 may be smaller than that of the prior art. Since the contact hole only needs to reach the second gate electrode, the contact hole needs to be shallow, and a second gate electrode having an area larger than the distance between the first gate electrodes (word lines) can be provided in the contact formation portion. For such reasons, the aspect ratio of the contact hole provided in the interlayer insulating film can be reduced. Accordingly, since it is not necessary to form a buried contact, a step of burying the contact hole becomes unnecessary, and the T of the multi-gate mask ROM becomes unnecessary.
AT can be shortened. The first and second tungsten silicide films are representative of the high melting point metal silicide film.

[0018]

As described above, according to the present invention, a groove is provided after the formation of a first gate electrode, a second gate insulating film is formed in the groove, and the second gate insulating film in a contact formation portion is removed. Then, the aspect ratio of the contact hole for the digit line is reduced by burying the second polycrystalline silicon film for forming the second gate electrode and the groove of the contact formation portion with the second metal silicide film. This makes it unnecessary to use a buried contact, which simplifies the process and contributes to shortening the TAT of the semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention;
FIG. 3D is a cross-sectional view of the semiconductor chip, which is illustrated in the order of steps, separately from FIG.

FIGS. 2A to 2D are cross-sectional views of a semiconductor chip shown in FIGS. 2A to 2D for explaining a conventional method of manufacturing a semiconductor memory device and shown in the order of steps; FIGS.

[Explanation of symbols]

 1,101 P-type silicon substrate 2,102 First gate oxide film 3a, 103a First polycrystalline silicon film 3b, 103b First tungsten silicide film 4,104 Source / drain region 5a, 105a First silicon oxide Film 5b, 105b Spacer 6, 106 Second tungsten silicide film 7, 107 Contact formation portion 8a, 108a Second polycrystalline silicon film 8b, 108b Second tungsten silicide film 9, 109 Resist film 10a, 10b, 110a Ion Implanted region 10b, 110b N-type diffusion layer 111a Ion-implanted region 111b N-type diffusion layer 12, 112 Interlayer insulating film 113 Contact hole 14, 114 Electrode wiring 15 Embedded contact

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 H01L 21/3205 H01L 21/8234 H01L 27/088 H01L 27/112

Claims (2)

(57) [Claims] A step of sequentially forming a first polycrystalline silicon film, a first metal silicide film, and a first insulating film on a semiconductor substrate via a first gate insulating film; Selectively etching the film, the first metal silicide film, and the first polycrystalline silicon film to form a plurality of first gate electrodes whose surfaces are covered with the first insulating film; Implanting ions of a conductivity type opposite to that of the semiconductor substrate using the first gate electrodes as masks to form source / drain regions; and depositing a second insulating film and then etching back the first gate. Forming a spacer on each of the side surfaces of the electrode, etching the semiconductor substrate using the first insulating film and the spacer as a mask to form grooves, and forming second grooves on the side and bottom surfaces of the groove. Forming a gate insulating film;
A step of removing the second gate insulating film in a region where a contact is to be formed, a step of depositing a second polycrystalline silicon film and then etching back to fill a groove between the first gate electrodes; Depositing and patterning a silicide film to form a second gate electrode; and implanting ions of a conductivity type opposite to that of the semiconductor substrate into a channel region immediately below a predetermined first gate electrode portion or directly below a second gate electrode portion. Writing information by performing the following steps: forming an interlayer insulating film over the entire surface after the step; forming contact holes in the interlayer insulating film on predetermined source / drain regions, and then forming an electrode wiring. A method for manufacturing a semiconductor memory device, comprising: 2. The method according to claim 1, wherein the metal silicide film is a tungsten silicide film.