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JP3089956B2 - Multilayer ceramic capacitors - Google Patents

Multilayer ceramic capacitors

Info

Publication number
JP3089956B2
JP3089956B2 JP06243800A JP24380094A JP3089956B2 JP 3089956 B2 JP3089956 B2 JP 3089956B2 JP 06243800 A JP06243800 A JP 06243800A JP 24380094 A JP24380094 A JP 24380094A JP 3089956 B2 JP3089956 B2 JP 3089956B2
Authority
JP
Japan
Prior art keywords
electrode
internal
capacitor
multilayer ceramic
internal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP06243800A
Other languages
Japanese (ja)
Other versions
JPH08111344A (en
Inventor
久直 中蔵
巌夫 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP06243800A priority Critical patent/JP3089956B2/en
Publication of JPH08111344A publication Critical patent/JPH08111344A/en
Application granted granted Critical
Publication of JP3089956B2 publication Critical patent/JP3089956B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、積層セラミックコンデ
ンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor.

【0002】[0002]

【従来の技術】一般に積層セラミックコンデンサは、セ
ラミックグリーンシートならびにセラミックグリーンシ
ート上に内部電極ペーストを印刷したシートを積み重ね
た後、加圧させて積層体とし、次に焼成し、焼結体の両
端部に内部電極と接続される外部電極を設けた構造であ
る。
2. Description of the Related Art In general, a multilayer ceramic capacitor is obtained by stacking ceramic green sheets and sheets on which an internal electrode paste is printed on ceramic green sheets, pressurizing to form a laminate, and then firing and sintering both ends of the sintered body. This is a structure in which an external electrode connected to the internal electrode is provided in the portion.

【0003】中高圧積層セラミックコンデンサ(1kV
級以上)では、直列式の電極構造を形成し、有効層1層
あたりにかかる電圧を半減させ絶縁破壊を発生しにくく
していた。
[0003] Medium to high voltage monolithic ceramic capacitors (1 kV
Or higher), a series electrode structure was formed, the voltage applied to each effective layer was reduced by half, and dielectric breakdown was less likely to occur.

【0004】[0004]

【発明が解決しようとする課題】上記従来の構成では、
高電圧で使用する場合、内部電極の端部に電界が集中し
やすいため、内部電極の端部で絶縁破壊が発生しやすい
という問題点を有していた。
In the above-mentioned conventional configuration,
When used at a high voltage, the electric field tends to concentrate on the ends of the internal electrodes, and therefore, there is a problem that dielectric breakdown easily occurs at the ends of the internal electrodes.

【0005】本発明は、内部電極の端部で発生する絶縁
破壊を防止し、絶縁破壊電圧を向上させた積層セラミッ
クコンデンサを提供することを目的とするものである。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer ceramic capacitor in which dielectric breakdown occurring at an end of an internal electrode is prevented and dielectric breakdown voltage is improved.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明の積層セラミックコンデンサは、相対向する端
部に至るように一対の第1の内部電極を形成した第1の
誘電体層と、端部に至らないように第2の内部電極を形
成した誘電体層とを交互に積層した積層体と、この積層
体の端部に外部電極を形成したものであり、第1の内部
電極は、それぞれ容量電極と、外部電極とこの容量電極
とを接続するとともにこの容量電極の幅よりも小さい幅
の少なくとも1個の導出電極と、この容量電極間に設け
た少なくとも1つの浮遊電極とからなり、第2の電極
は、一対の容量電極と、この容量電極同士を接続すると
ともにこの容量電極の幅よりも小さい幅の少なくとも1
個の導出電極と、外部電極と容量電極との間に設けた少
なくとも1つの浮遊電極とからなり、第1の内部電極の
浮遊電極は第2の内部電極の導出電極と誘電体層を介し
て対向するように形成され、第2の内部電極の浮遊電極
は、第1の内部電極の導出電極と誘電体層を介して対向
するように形成されたものである。
In order to achieve this object, a multilayer ceramic capacitor according to the present invention comprises a first dielectric layer having a pair of first internal electrodes formed so as to reach opposite ends. A laminate in which dielectric layers on which second internal electrodes are formed alternately so as not to reach an end, and an external electrode formed on an end of the laminate, and a first internal electrode Are connected to the capacitor electrode, the external electrode and the capacitor electrode, and at least one lead electrode having a width smaller than the width of the capacitor electrode, and at least one floating electrode provided between the capacitor electrodes. The second electrode has a pair of capacitance electrodes and at least one of a width smaller than the width of the capacitance electrode, connecting the capacitance electrodes to each other.
And at least one floating electrode provided between the external electrode and the capacitor electrode. The floating electrode of the first internal electrode is connected to the second internal electrode via the dielectric electrode and the dielectric layer. The floating electrode of the second internal electrode is formed so as to face the lead-out electrode of the first internal electrode via a dielectric layer.

【0007】[0007]

【作用】この構成によると、内部電極端部への電界集中
が緩和されるため、絶縁破壊電圧が向上する。
According to this structure, the electric field concentration on the end of the internal electrode is reduced, so that the dielectric breakdown voltage is improved.

【0008】[0008]

【実施例】【Example】

(実施例1)以下、本発明の第1の実施例について図面
を参照しながら説明する。
Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

【0009】図1,2,3,4には本発明の一実施例に
おける積層セラミックコンデンサの断面図が示されてい
る。この積層セラミックコンデンサの製造方法について
説明する。
FIGS. 1, 2, 3 and 4 are sectional views of a multilayer ceramic capacitor according to an embodiment of the present invention. A method for manufacturing the multilayer ceramic capacitor will be described.

【0010】まず、キャリアフィルム上に誘電体セラミ
ックススラリーをリバースロールコータにより成形し、
乾燥してセラミックグリーンシートを構成した。次に、
セラミックグリーンシートをキャリアフィルムから剥離
し、セラミックグリーンシート上に内部電極用ペースト
をスクリーン印刷により図5に示すパターンYで印刷乾
燥し、その上に、セラミックグリーンシートを積層し、
このグリーンシート上に、図5に示すパターンYを長さ
方向にずらして内部電極用ペーストを印刷乾燥した。こ
の工程を繰り返すことにより積層を行った。このように
積層したセラミックグリーンシートの上側および下側に
必要に応じて内部電極用ペーストが印刷されていないセ
ラミックグリーンシートを所定枚数積層した。次に、積
層したセラミックグリーンシートをプレスしてお互いに
圧着し、積層体を構成した。次に、この積層体を切断
し、バインダアウト、焼成を行い、その後、外部電極を
塗布、焼き付けし、Niメッキ、Sn−Pbメッキを行
い、積層セラミックコンデンサとした。得られた積層セ
ラミックコンデンサは、静電容量100pF,Q 12
00, IR 1*1013Ωであった。
First, a dielectric ceramic slurry is formed on a carrier film by a reverse roll coater.
After drying, a ceramic green sheet was formed. next,
The ceramic green sheet was peeled off from the carrier film, the internal electrode paste was printed and dried on the ceramic green sheet in a pattern Y shown in FIG. 5 by screen printing, and the ceramic green sheet was laminated thereon.
On this green sheet, the internal electrode paste was printed and dried while shifting the pattern Y shown in FIG. 5 in the length direction. By repeating this process, lamination was performed. On the upper and lower sides of the thus laminated ceramic green sheets, a predetermined number of ceramic green sheets on which the internal electrode paste was not printed were laminated as necessary. Next, the laminated ceramic green sheets were pressed and pressed together to form a laminate. Next, the laminated body was cut, binder-out and firing were performed, and then external electrodes were applied and baked, and Ni plating and Sn-Pb plating were performed to obtain a multilayer ceramic capacitor. The obtained multilayer ceramic capacitor has a capacitance of 100 pF, Q 12
00, IR 1 * 10 13 Ω.

【0011】この積層セラミックコンデンサの絶縁破壊
電圧を測定し、その結果を(表1)に示す。
The dielectric breakdown voltage of this multilayer ceramic capacitor was measured, and the results are shown in Table 1.

【0012】[0012]

【表1】 [Table 1]

【0013】(比較例1)まず、キャリアフィルム上に
誘電体セラミックススラリーをリバースロールコータに
より成形、乾燥しセラミックグリーンシートを構成し
た。次に、セラミックグリーンシートをキャリアフィル
ムから剥離し、セラミックグリーンシート上に、内部電
極ペーストをスクリーン印刷により図6に示すパターン
Wで印刷乾燥し、その上に、セラミックグリーンシート
を積層し、このグリーンシート上に図6に示すパターン
Wを長さ方向にずらし、内部電極ペーストを印刷乾燥し
た。この工程を繰り返すことにより積層を行った。積層
したセラミックグリーンシートはプレスしてお互いに圧
着し、積層体を構成した。以降は実施例1と同様にして
積層セラミックコンデンサを得たが、これが従来例タイ
プとなる。
Comparative Example 1 First, a dielectric ceramic slurry was formed on a carrier film by a reverse roll coater and dried to form a ceramic green sheet. Next, the ceramic green sheet is peeled off from the carrier film, the internal electrode paste is printed and dried on the ceramic green sheet in a pattern W shown in FIG. 6 by screen printing, and a ceramic green sheet is laminated thereon. The pattern W shown in FIG. 6 was shifted in the length direction on the sheet, and the internal electrode paste was printed and dried. By repeating this process, lamination was performed. The laminated ceramic green sheets were pressed and pressed together to form a laminate. Thereafter, a multilayer ceramic capacitor was obtained in the same manner as in Example 1, but this was the conventional type.

【0014】得られた積層セラミックコンデンサを用い
て実施例1と同様に絶縁破壊電圧を測定した結果を(表
1)に示す。
The results of measuring the dielectric breakdown voltage of the obtained multilayer ceramic capacitor in the same manner as in Example 1 are shown in Table 1 below.

【0015】この(表1)から明らかなように、本発明
の積層セラミックコンデンサは絶縁破壊電圧が向上する
ことができる。
As apparent from Table 1, the multilayer ceramic capacitor of the present invention can improve the dielectric breakdown voltage.

【0016】本実施例においては、図1、図2に示すよ
うに2種類の内部電極2a,2bを誘電体セラミック層
1を挟んで交互に積層して積層体を形成しており、この
積層セラミックコンデンサの図2におけるA−Aの断面
図が図3、B−Bの断面図が図4に示されている。図3
を見るとわかるように、浮遊電極3を設けることによ
り、従来よりも電界の集中を緩和することができる。
In this embodiment, as shown in FIGS. 1 and 2, two kinds of internal electrodes 2a and 2b are alternately laminated with a dielectric ceramic layer 1 interposed therebetween to form a laminate. FIG. 3 is a cross-sectional view of the ceramic capacitor taken along the line AA in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line BB of FIG. FIG.
As can be seen from the figure, the provision of the floating electrode 3 can reduce the concentration of the electric field as compared with the conventional case.

【0017】なお、本実施例においては、1個の容量電
極5に対し、導出電極6を2個設けたが、外部電極4と
容量電極との導通が取れ、電界集中が起こりにくければ
よい。また、浮遊電極3も、一つの誘電体セラミック層
1上に4つ設けたが、できるだけ大きくまた数は多いほ
うが電界集中をより緩和することができる。また、本実
施例においては、容量電極5のコーナーに丸みをもた
せ、浮遊電極3の形状も円形としたが、これも電界集中
を起こりにくくするためのものである。
In the present embodiment, two lead-out electrodes 6 are provided for one capacitor electrode 5, but it is sufficient that electrical connection between the external electrode 4 and the capacitor electrode is established and electric field concentration hardly occurs. Also, four floating electrodes 3 are provided on one dielectric ceramic layer 1, but the larger and the larger the number, the more the electric field concentration can be eased. Further, in the present embodiment, the corners of the capacitance electrode 5 are rounded and the shape of the floating electrode 3 is also circular, but this is also for preventing the electric field concentration from occurring.

【0018】[0018]

【発明の効果】以上、本発明は内部電極端部への電界集
中を緩和することにより、絶縁破壊電圧が向上するもの
である。
As described above, according to the present invention, the dielectric breakdown voltage is improved by alleviating the electric field concentration on the end of the internal electrode.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における積層セラミックコン
デンサの横断面図
FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.

【図2】本発明の一実施例における積層セラミックコン
デンサの横断面図
FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor according to one embodiment of the present invention.

【図3】本発明の一実施例における積層セラミックコン
デンサのA−A断面図
FIG. 3 is a sectional view taken along line AA of the multilayer ceramic capacitor in one embodiment of the present invention.

【図4】本発明の一実施例における積層セラミックコン
デンサのB−B断面図
FIG. 4 is a sectional view taken along line BB of the multilayer ceramic capacitor in one embodiment of the present invention.

【図5】本発明の一実施例における内部電極を印刷する
ためのスクリーンパターン図
FIG. 5 is a screen pattern diagram for printing internal electrodes according to an embodiment of the present invention.

【図6】従来の内部電極を印刷するためのスクリーンパ
ターン図
FIG. 6 is a screen pattern diagram for printing a conventional internal electrode.

【符号の説明】[Explanation of symbols]

1 誘電体セラミック層 2a 内部電極 2b 内部電極 3 浮遊電極 4 外部電極 5 容量電極 6 導出電極 Reference Signs List 1 dielectric ceramic layer 2a internal electrode 2b internal electrode 3 floating electrode 4 external electrode 5 capacitance electrode 6 lead-out electrode

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01G 4/00 - 4/40 H01G 13/00 - 13/06 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01G 4/00-4/40 H01G 13/00-13/06

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 2個の第1の内部電極をそれぞれ相対向
する端部に至るように設けた第1の誘電体層と、1個の
第2の内部電極を端部に非接触の状態で設けた第2の誘
電体層とを複数枚交互に積層した積層体と、この積層体
の前記第1の内部電極の露出した端面に設けた外部電極
とを備え、前記第1の内部電極は、それぞれ容量電極
と、前記外部電極とこの容量電極とを接続するとともに
この容量電極の幅よりも小さい幅の少なくとも1個の導
出電極と、この容量電極間に設けた少なくとも1つの浮
遊電極とからなり、前記第2の電極は、一対の容量電極
と、この容量電極同士を接続するとともにこの容量電極
の幅よりも小さい幅の少なくとも1つの導出電極と、前
記外部電極と前記容量電極との間に設けた少なくとも1
つの浮遊電極とからなり、前記第1の内部電極の浮遊電
極は前記第2の内部電極の導出電極と誘電体層を介して
対向するように形成され、前記第2の内部電極の浮遊電
極は、前記第1の内部電極の導出電極と誘電体層を介し
て対向するように形成されている積層セラミックコンデ
ンサ。
1. A first dielectric layer provided with two first internal electrodes extending to opposing ends, and a state in which one second internal electrode is not in contact with the ends. A laminate in which a plurality of the second dielectric layers provided in the above are alternately laminated, and an external electrode provided on an exposed end face of the first internal electrode of the laminate, wherein the first internal electrode Are respectively connected to the capacitor electrode, the external electrode and the capacitor electrode, and at least one lead electrode having a width smaller than the width of the capacitor electrode; and at least one floating electrode provided between the capacitor electrodes. The second electrode is formed of a pair of capacitance electrodes, at least one lead electrode connecting the capacitance electrodes and having a width smaller than the width of the capacitance electrodes, and the external electrode and the capacitance electrodes. At least one in between
And a floating electrode of the first internal electrode is formed so as to face a lead electrode of the second internal electrode via a dielectric layer, and the floating electrode of the second internal electrode is A multilayer ceramic capacitor formed so as to face the lead-out electrode of the first internal electrode via a dielectric layer.
JP06243800A 1994-10-07 1994-10-07 Multilayer ceramic capacitors Expired - Fee Related JP3089956B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06243800A JP3089956B2 (en) 1994-10-07 1994-10-07 Multilayer ceramic capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06243800A JP3089956B2 (en) 1994-10-07 1994-10-07 Multilayer ceramic capacitors

Publications (2)

Publication Number Publication Date
JPH08111344A JPH08111344A (en) 1996-04-30
JP3089956B2 true JP3089956B2 (en) 2000-09-18

Family

ID=17109137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06243800A Expired - Fee Related JP3089956B2 (en) 1994-10-07 1994-10-07 Multilayer ceramic capacitors

Country Status (1)

Country Link
JP (1) JP3089956B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101079464B1 (en) * 2009-12-22 2011-11-03 삼성전기주식회사 multilayer ceramic capacitor
CN105074853A (en) * 2013-02-14 2015-11-18 株式会社村田制作所 Ceramic electronic component and method for producing same
KR102122935B1 (en) * 2013-03-29 2020-06-26 삼성전기주식회사 Multi-layered ceramic capacitor and manufacturing method the same

Also Published As

Publication number Publication date
JPH08111344A (en) 1996-04-30

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