JP3088834B2 - Active matrix display device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic display device such as an active matrix type liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, active matrices for driving liquid crystal displays have been actively studied and put into practical use. In a conventional active matrix circuit, a capacitor having a liquid crystal interposed between a pixel electrode and a counter electrode is formed, and electric charges entering and exiting the capacitor are controlled by a thin film transistor (TFT). In order to display images stably, it was required that the voltage of both electrodes of the capacitor be kept constant, but there were difficulties for several reasons.

One problem is a phenomenon (ΔV) in which the gate signal is capacitively coupled to the pixel potential due to the parasitic capacitance between the gate electrode and the pixel electrode of the TFT, and the voltage fluctuates. That is, the gate pulse (signal voltage) is V _G , and the pixel capacitance is C
_LC, the parasitic capacitance of the gate electrode and the pixel electrode C 'when _{A, ΔV = C'V G / (C} LC + C' occurs when the variation of the voltage represented by) ... is removed the gate pulse did. The size of the ΔV is theoretically was the same regardless of the signal magnitude and polarity applied to the data line Y _m.

In order to solve this problem, _{CLC is changed} to C ′
Therefore, by forming the source / drain in a self-aligned manner, the parasitic capacitance can be reduced, or an auxiliary capacitance can be inserted in parallel with the pixel capacitance, so that the above denominator is apparently obtained. It has been made bigger.

Recently, a CMO as shown in FIG.
Attempts have been made to solve this problem by using an S transfer gate circuit (see, for example,
178632). That is, in such a transfer gate circuit, a negative pulse is applied to the gate electrode of the PMOS (P-channel TFT) and the negative pulse is applied to the NMOS (N-channel TFT).
When the gate electrode to the positive pulse of FT) (also both pulse wave height and V _G) is applied at the same time,
[Delta] V _{is, ΔV = (C 1 -C 2} ) V G / (C 1 + C 2 + C LC)
... (where C ₁ and C ₂ are the capacitance between each TFT and the pixel capacitance), so that if C ₁ and C ₂ are made equal, ΔV can be set to 0. it can.

In addition, since at least two TFTs exist for one pixel, even if one TFT does not operate due to a defect, it can be compensated by another TFT. Of course, in this case, depending on the degree of failure,
The equation does not apply, and the ordinary active matrix equation is applied. Therefore, when the parasitic capacitance is extremely large, ΔV becomes very large.

In FIG. 1, gate wirings are for PMOS and NM.
It is also used for the OS.
As shown in 32, a wiring dedicated to PMOS and a wiring dedicated to NMOS may be provided. However, in that case, the number of gate lines is doubled, so that the aperture ratio decreases.

Generally, in an active matrix circuit,
Electric charges are discharged from the pixel electrode via the TFT. Therefore, in a conventional TFT, an auxiliary capacitor is provided to suppress the release of the electric charge. However, even in the transfer gate type circuit of FIG. 1, the auxiliary capacitor is provided to suppress the release of the electric charge. . And in that case,
By taking advantage of the characteristic of the transfer gate circuit that ΔV is 0 if C ₁ and C ₂ are equal, as shown in FIG. 1B, the pixel electrodes overlap the gate lines (X _n , X _{n + 1} ) as shown in FIG. Attempts were made to use them as auxiliary capacitors (C ₁ , C ₂ ). That is, the gate line is at the same level as the ground level except during the application of the pulse. For this reason, for example, it was not necessary to provide a new ground line, and it was expected that high image quality could be obtained while maintaining the aperture ratio.

[0009]

However, FIG.
In forming the auxiliary capacitance as in (B), especially when the size of the auxiliary capacitance becomes large, it is difficult to make C ₁ and C ₂ exactly equal. For example, the parasitic capacitance per TFT when the source / drain is formed by the self-alignment method can be set within 10% of the pixel capacitance, and the variation in the parasitic capacitance of the two TFTs can be further reduced by 30%.
%. That is, (C ₁ -C ₂ ) in the equation can be set within 3% of the pixel capacity.

On the other hand, when a capacitance is artificially set as an auxiliary capacitance other than a parasitic capacitance formed naturally, the size of one auxiliary capacitance is required to be about the same as the pixel capacitance. Therefore, even if the difference between the _two storage capacitors C ₁ and C ₂ is within 10%, (C ₁ −C ₂ ) in the equation is 10 to 20% of the pixel capacitance. Actually, a larger fluctuation occurs due to a subtle difference in the width of the gate line, a shift of the overlap of the pixel electrodes, and the like, and a large auxiliary capacitance of 10 times or more of the pixel capacitance is required. As a result, ΔV sometimes became extremely large.

[0011]

In order to solve this problem, the present invention proposes a circuit arrangement as shown in FIG. That is, in the present invention, a transfer gate circuit is formed by connecting a TFT to the gate wiring in the n-th row and the gate wiring in the (n + 2) -th row, and the transfer wiring is formed in the gate wiring in the (n + 1) -th row. The storage capacitor C is formed by overlapping the pixel electrodes of the gate circuit. On the other hand, as is clear from the drawing, the gate wiring in the (n + 1) th row also functions as a gate electrode of another pixel, not a wiring dedicated to the storage capacitor. That is, since no extra wiring is provided, the aperture ratio does not decrease.

FIG. 2 shows a circuit diagram and a configuration for explaining the present invention. In such a configuration, when attention is paid to one data line (for example, Y _m ), it is efficient to maintain an aperture ratio by alternately configuring pixels such as left, right, left and right across the data line. is there.

In the present invention, C ₁ and C ₂ in the formulas are substantially parasitic capacitances of each TFT, and as is apparent from the figure, the pixel electrodes do not overlap the gate lines. Thus, in the formula, molecular is very small, and the C _LC of the denominator substantially is larger applied auxiliary capacitance C in addition to the pixel capacitance.

In the driving, the nth row and the (n
Pulses having polarities opposite to each other must be simultaneously applied to the gate lines of the (+2) -th row, but no pulse must be applied to the gate line of the intermediate (n + 1) -th row. Therefore, when a bipolar pulse in which a positive pulse and a negative pulse are continuously combined is applied to each gate line, as shown in FIG.
1) In the row, it is necessary that a pulse is applied to the n-th row and then applied in the middle before a pulse is applied again to the n-th row, and a positive pulse is applied to each gate line. When a pulse signal without a pulse is applied between the negative pulse and the negative pulse, as shown in FIG. 3B, a pulse is applied to the (n + 1) th row when there is no pulse. Is required.

It should be noted here that the auxiliary capacitance is formed using the gate line of the (n + 1) th row as one electrode, so that the potential of the pixel electrode is the potential of the gate line of the (n + 1) th row. Strongly influenced by This is shown in FIG. 3, but this is temporary and returns immediately to its original state with little visual effect. (N
+1) The time during which a pulse is applied to the gate line of the row is only a short time within one frame.

FIG. 4 shows an example of a manufacturing process for manufacturing the circuit of the present invention. Figures (A-1), (B-1), (C-
1) and (D-1) are cross-sectional views, and (A-2) and (B-
2), (C-2) and (D-2) are top views. Since the details of each process are described in Japanese Patent Application Nos. 4-30220, 4-38637, and 3-273377, no particular description is given here.

First, an underlying silicon oxide film 2 is formed on a substrate 1. This may be a multilayer film of silicon oxide and silicon nitride. Then, island-shaped semiconductor regions 3, 3 'are formed. Further, a gate insulating film (silicon oxide) 4 was formed, and gate wirings 6, 6 ', and 7 were formed of aluminum. (FIG. 4 (A
-1) and (A-2))

Thereafter, anodization was performed to form aluminum oxide films 8, 8 'and 9 around the gate wiring. The thickness was 350 nm. And a known CMOS
Impurity implantation was performed using a formation technique to form impurity regions (source / drain) 10, 10 '. (FIG. 4
(B-1) and (B-2))

Next, an interlayer insulator of silicon oxide is deposited to a thickness of 50
Only 0 nm was formed. Here, silicon oxide was left only at the intersection of the data line and the gate line, and the other portions were removed to form silicon oxide regions 11a, 11b, and 11c. Then, at this time, the silicon oxide film formed as the gate oxide film was removed to expose the impurity semiconductor region. (FIG. 4
(C-1) and (C-2))

A capacitance is generated at a portion where the data line and the gate line intersect, and this capacitance causes a delay of a gate signal and data. In order to reduce the capacitance, it is good to form the interlayer insulator thick as described above, but such interlayer insulator is not particularly required for other portions. In particular, when the silicon oxide layer is removed up to the one formed as the gate insulating film as in this example, the conventional contact hole is unnecessary, and therefore, the contact failure is significantly reduced. did it.

In such a process, a mask is required for the silicon oxide regions 11a, 11b, and 11c, but no mask is required for the other portions. This is because aluminum oxide formed as an anodic oxide film has extremely high corrosion resistance and, for example, etching with buffered hydrofluoric acid has a sufficiently slower etching rate than etching rate of silicon oxide.

Therefore, the silicon oxide film can be etched in a self-aligned manner with respect to the gate electrode. conventionally,
Although fine mask alignment was necessary for forming the contact hole of the TFT, this is not necessary in this example. Of course, a method of forming a contact hole may be adopted as in the conventional case.

Finally, a data line 12 and electrodes 13 and 13 'are formed of aluminum or chromium.
Thus, the pixel electrode 14 was formed. At this time, by arranging the pixel electrode so as to overlap the central gate wiring 7, an auxiliary capacitance could be formed therebetween. In particular, in this case,
Aluminum oxide (anodic oxide) having a thickness of 350 nm is formed between the gate wiring and the pixel electrode. The dielectric constant of the aluminum oxide is about twice as large as that of normal silicon oxide, which is effective. (FIG. 4 (D-1) and (D-2))

In the above example, the means of anodic oxidation is used, but it goes without saying that a normal TFT manufacturing method may be used.

[0025]

【Example】

Embodiment 1 FIG. 3A shows an example of a signal for driving an active matrix (shown in FIG. 2) of the present invention. In this example, signals are applied to the gate lines intermittently as in a so-called interlaced scanning method. That is, a signal is first applied to the gate line X _n of the n-th row, and then the (n + 1) -th gate line is applied.
It is applied to the (n + 2) _th gate line X _{n + 2} , skipping the gate line X _{n + 1} of the row.

In the circuit of FIG. 2, one gate line is a PMO
Since it is connected to both S and NMOS gates, a positive pulse and a negative pulse need to be applied. FIG.
As shown in (A), a negative pulse is first applied to X _n−1 , followed by a positive pulse. X _n-1 and m-th
Although column TFT connected to the data line Y _m of a two, a first negative pulse, pixel Z _n, NMOS of _m is not operated,
The PMOS of the pixel Zn _{-2, m} (not shown) operates.

On the other hand, a negative pulse is applied to X _{n + 1} at the same time that a positive pulse is applied to X _n-1 . At this time, the NMOS and PMOS of the pixel Zn _{, m} operate and turn on, and the pixel and the auxiliary capacitance are charged.

Next, a positive pulse is applied to X _{n + 1} , to which the PMOS of the pixel Zn _{, m} does not react, and the pixel Z _{n + 2, m below it} (not shown) ) NMOS operates.
In this way, scanning continues.

In this embodiment, the signal of the data line is set to 1
The polarity is inverted every half frame, that is, so-called alternating current is performed. Pulse X _n is applied from the pulse is applied to X _n-1 after approximately 1/4 frame. At that time, a negative pulse is applied first, and then a positive pulse is applied, in the same manner as the pulse was applied to X _n-1 and X _{n + 1} first.

And, similarly, in the first negative pulse,
Pixel Z _{n + 1,} NMOS of _m is not operated, the pixel Z _{n-1, m} of P
The MOS operates. At the same time a positive pulse is applied to the X _n, the X n _{+ 2} negative pulse is applied. At this time, the NMOS and PMOS of the pixel Zn _{+ 1, m} operate and turn on, and the pixel and the auxiliary capacitance are charged.

Next, a positive pulse is applied to X _{n + 2} , but the PMOS of the pixel Zn _{+ 1, m} does not respond to this, and the pixel Zn _{+ 3, m} below it does not react. NMOS (not shown) operates. In this way, scanning continues.

Here, the potential of the pixel Zn _{, m} is greatly affected by the pulse of the gate line _Xn functioning as an electrode of the storage capacitor. When a pulse is applied to the gate line _Xn , the pixel Zn _{, m} is in a static state (a state in which electric charges do not flow in and out).
Since the potential of the gate line _Xn changes positively and negatively as shown in the figure, the potential of the pixel electrode also changes accordingly.
This change in potential is determined by the ratio between the size of the auxiliary capacitance and the size of the pixel capacitance. However, the charge rarely enters or leaves the pixel electrode due to this change, and consequently returns to the original state. The pixel Z _{n + 1, m} also undergoes a similar variation due to the gate line X _{n + 1} . The duration of this fluctuation is so short that there is little visual effect.

The time during which the fluctuation continues is the time corresponding to two pulses of the gate line. For example, one frame is 30 ms
c, in the display device of 480 rows, the time per pulse is 62.5 μsec, so the time of this fluctuation is 125 μsec. This is 1/240 of one frame.

Although an ideal driving example has been described above, actually, when a pulse is applied to each gate line, an appropriate interval is set in order to avoid overlapping of pulses between different gate lines. A pulse may be applied.

Embodiment 2 FIG. 3B shows an example of a signal for driving the active matrix (shown in FIG. 2) of the present invention. In this example, signals are sequentially applied to the gate lines. That first signal to the gate line X _n in the n-th row is applied to the next gate line X _{n + 1} of the (n + 1) row, further the (n + 2) to the gate line X _{n + 2} rows , And so on.

As shown in FIG._n-1The most
First, a negative pulse is applied, followed by the first pulse
After a time equal to the time, a positive pulse is applied.
You. X _n-1And the m-th column data line Y_mTFT connected to
There are two, but in the first negative pulse, pixel Z_{n, m}NM
The OS does not operate and the pixel Z_{n-2, m}PMOS (not shown)
Works.

On the other hand, at the same time that a positive pulse is applied to X _n−1 , a negative pulse is applied to X _{n + 1} . At this time, the NMOS and PMOS of the pixel Zn _{, m} operate and turn on, and the pixel and the auxiliary capacitance are charged.

On the other hand, a negative pulse is applied to X _n between the negative pulse and the positive pulse of X _n-1 . Then, with this negative pulse, the NMOS of the pixel Zn _{+ 1, m} does not operate,
The PMOS of the pixel Zn _{-1, m} operates. Then, no pulse is applied while the pulse is applied to X _n-1 and X _{n + 1} . After the pulse of the X _n-1 is completed, the positive pulse is applied to the X _n, a negative pulse is applied to the X _{n + 2} at the same time. At this time, the NMOS and PMOS of the pixel Zn _{+ 1, m} operate and turn on, and the pixel and the auxiliary capacitance are charged.

[0039] After the pulse of the X _n has been completed, the positive pulse to X n _{+ 1} is applied, including, pixel Z _n, PM of _m
The OS does not respond, and the NMOS of the pixel Zn _{+ 2, m} (not shown) under the OS operates. In this way, scanning continues.

Here, as in the first embodiment, the potential of the pixel Zn _{, m} is greatly affected by the pulse of the gate line _Xn functioning as an auxiliary capacitance electrode. However, it is the same as in the first embodiment that the image quality finally falls within a level that does not affect the image quality.

[0041]

As described above, according to the present invention, a highly reliable auxiliary capacitor for stabilizing the potential of a pixel can be formed without lowering the aperture ratio. In this embodiment, the planar type TFT has been described. However, it is apparent that the same effect can be obtained even with an inverted stagger type TFT which is often used in the present amorphous silicon TFT.

[Brief description of the drawings]

FIG. 1 shows a circuit diagram and a configuration diagram of a conventional active matrix.

FIG. 2 shows a circuit diagram and a configuration diagram of an active matrix of the present invention.

FIG. 3 shows an operation example of the active matrix circuit of the present invention.

FIG. 4 shows an example of a manufacturing process of a circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Underlying silicon oxide layer 3, 3 'Island-shaped semiconductor region 4 Gate insulating film 6, 6', 7 Gate electrode / wiring 8, 8 ', 9 Anodized film 10, 10' Impurity region 11a, 11b, 11c Interlayer Insulator 12 Data line 13, 13 'Metal electrode 14 Pixel electrode

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1362 G02F 1/133 G09F 9/00-9/46 G09G 3/36 H01L 29/78

Claims (5)

(57) [Claims] 1. A gate electrode connected to an n-th gate line, a (n + 1) -th gate line and a (n + 2) -th gate line provided in parallel with each other, and a gate electrode connected to the n-th row gate line. A second TFT having a gate electrode connected to the (n + 2) th gate line, and one of a source and a drain of the first TFT.
And any of the source and drain of the second TFT
A pixel electrode connected to one of the gate lines , an insulator provided between the gate line in the (n + 1) th row and the pixel electrode, a gate line in the (n + 1) th row, the pixel electrode,
An active matrix display device comprising: an auxiliary capacitor formed of an insulator . 2. The semiconductor device according to claim 1, wherein the first TFT is N
An active matrix display device comprising a MOS, and wherein the second TFT is a PMOS. 3. The (n-1) th gate line, the nth row gate line, the (n + 1) th gate line and the (n + 2) th gate line provided in parallel with each other, A first TFT having a gate electrode connected to the (n-1) th row of gate lines, a second TFT having a gate electrode connected to the nth row of gate lines,
1) Third having a gate electrode connected to the gate line of the row
And a fourth TFT having a gate electrode connected to the gate line of the (n + 2) th row, and one of a source and a drain of the first TFT
And any of the source and drain of the third TFT
A first pixel electrode connected to one of them, and one of a source and a drain of the second TFT
And the source and the drain of the fourth TFT
A second pixel electrode connected to one of the gate electrodes, a first insulator provided between the gate line in the n-th row and the first pixel electrode, a gate electrode in the n-th row, One pixel electrode and the first
A first storage capacitor composed of an insulator, a second insulator provided between the gate line of the (n + 1) -th row and the second pixel electrode, and a first storage capacitor of the (n + 1) -th row. Gate line, the second pixel electrode and
An active matrix display device , comprising: a second storage capacitor formed of the second insulator . 4. The method of claim 3, wherein the first TFT and the second TFT are NMOS, and the third T
The active matrix display device, wherein the FT and the fourth TFT are PMOS. 5. A gate electrode connected to the n-th gate line, the (n + 1) -th gate line and the (n + 2) -th gate line provided in parallel with each other, and a gate electrode connected to the n-th row gate line. A second TFT having a gate electrode connected to the (n + 2) th gate line, and one of a source and a drain of the first TFT.
And any of the source and drain of the second TFT
A pixel electrode connected to one of the gate lines , an insulator provided between the gate line in the (n + 1) th row and the pixel electrode, a gate line in the (n + 1) th row, the pixel electrode,
A method of driving an active matrix display device having an auxiliary capacitor formed of an insulator , wherein gate pulses of opposite polarities are simultaneously applied to the gate line of the n-th row and the gate line of the (n + 2) -th row. And while the gate pulse is being applied, the (n)
+1) A method for driving an active matrix display device, wherein a gate pulse is not applied to a gate line in a row.