JP3084645B2 - Inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device for bridging an arm formed by connecting a plurality of self-extinguishing semiconductor switch elements in series.

[0002]

2. Description of the Related Art An inverter circuit is formed by connecting semiconductor switching elements in a bridge, and converts DC into AC. As this semiconductor switch element, a self-extinguishing type semiconductor switch element such as a power transistor, a metal oxide semiconductor field effect transistor,
Alternatively, a gate turn-off thyristor (hereinafter abbreviated as GTO thyristor) is frequently used. As for the main circuit configuration of the inverter, various types have been reported so far. Among them, as described in JP-A-3-159570, four semiconductor switch elements (e.g. Then, a GTO thyristor is taken as an example) in series. Advantages of connecting four semiconductor switch elements in series corresponding to one are as follows. The circuit voltage can be increased, and the conversion capacity of the inverter increases. 2. Withstand voltage characteristics per semiconductor element can be reduced. 3. Three potential levels can be derived at the output point of the inverter. Is mentioned. By the way, when the above-mentioned inverter is shifted from the operating state to the stopped state, it is only necessary to turn off the ones that are turned on in each GTO thyristor, but in reality, a plurality of GTO thyristors are turned on. It is almost impossible to turn off the GTO thyristor at the same time due to the variation in the operation time based on the characteristic difference between the semiconductor switching elements. Therefore, if the turn-off order is inappropriate, a biased voltage is applied to a specific element, which may cause a permanent breakdown beyond the breakdown voltage limit. As a technique for preventing this permanent destruction, Japanese Patent Application Laid-Open No. 1-152771 discloses a technique in which the off-time of each semiconductor switch element is grasped in advance, and then each element is arranged at an optimum position of each arm. It is described that combinations of semiconductor switching elements are excluded.

[0003]

However, this technique is
There is no freedom in the arrangement of the semiconductor switch elements, which causes the selection of the semiconductor switch elements to be complicated.In addition, the off time of each semiconductor switch element is grasped in advance, and each element is arranged at an optimal position of each arm. However, when the off-time changes due to aging during use of the semiconductor switch element, a problem that element destruction occurs, and particularly, for an element such as IGBT, which has a higher switching speed than GTO, There is a problem that it is extremely difficult to determine the difference between the off times. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and when the inverter shifts from an operation state to a stop state, a plurality of self-extinguishing type semiconductor switch elements are given an order of turning off, and a specific element is not overvoltage destroyed. Thus, it is to safely stop the operation of the inverter.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to bridge an arm formed by connecting a plurality of self-extinguishing semiconductor switch elements in series and connect the arm between the positive and negative electrodes of a DC voltage source. An inverter that converts a direct current into an alternating current by turning on and off the self-extinguishing type semiconductor switch element belonging to an arbitrary arm; when the inverter stops operating from an operation state, the semiconductor belonging to each arm This is achieved by providing means for turning off the turn-off operation of the switch element first from the element located closer to the positive electrode side or the negative electrode side.

[0005]

By defining the order in which the semiconductor switch elements are turned off, when stopping the inverter during operation, even if there are variations in the operating characteristics of the semiconductor switch elements, they also change over time during use of the semiconductor switch elements. Occurs, and even if the operation time varies, a specific element does not enter an overvoltage state with respect to each semiconductor switch element, and the cause of breakdown voltage can be prevented beforehand. Further, unlike the related art, it is not necessary to determine in advance the difference between the off times of the respective semiconductor switch elements, and the arm of the inverter can be formed easily and quickly.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an inverter circuit to which the present invention is applied. Here, one inverter circuit is shown.
In FIG. 1, two GTO thyristors 1 and 2 as self-extinguishing semiconductor switch elements are connected in series to an upper arm, and freewheel diodes 13 and 14 are connected in anti-parallel to the respective GTO thyristors 1 and 2. Connecting. Furthermore, in order to protect both GTO thyristors 1 and 2, snubber diodes 21, 22 and snubber capacitors 31, 3
2, a snubber circuit composed of snubber resistors 41 and 42 is connected to each GT.
O thyristors 1 and 2 are connected in parallel. Similarly, the lower arm has a GT as a self-extinguishing type semiconductor switch element.
O thyristors 3 and 4, freewheel diode 15,
16, snubber diodes 23 and 24, snubber capacitors 33 and 34, and snubber resistors 43 and 44. Further, filter capacitors 7 and 8 of the same capacity connected in series are connected to the upper end of the upper arm and the lower end of the lower arm, and the connection point between the filter capacitors 7 and 8 and the middle point of the upper arm and the lower arm are connected. The middle point is connected by clamp diodes 5 and 6. Reference numerals 10, 11, and 12 indicate wiring inductances. When the + side voltage of the power supply 9 is output to the output point R of the inverter in the operation state of the inverter circuit, both the GTO thyristors 1 and 2 are turned on. When outputting the intermediate voltage of the power supply 9, GT
Both O-thyristors 2 and 3 are turned on. In addition, power supply 9
Output the negative voltage of the GTO thyristor 3,
Turn 4 on.

Hereinafter, the operation of the inverter circuit for shifting from the operating state to the stopped state will be described. In the inverter circuit of FIG.
Is on, and the GTO thyristors 3 and 4 are off. At this time, the total voltage E of the power supply voltage source 9 is applied to the output point R.
Is output. When the inverter operation is stopped from this state, an off signal is sent to the gates G1 and G2 at the same time for the GTO thyristors 1 and 2. Thereby, the inverter operation can be stopped. However, at this time, it is assumed that the GTO thyristor 2 is turned off earlier than the GTO thyristor 1 because the characteristics of the switch elements vary.
FIG. 2 shows the changes in the voltage and current waveforms of each part in the inverter circuit at this time. When simultaneous off command is turned at time t _1, the inverter starts to stop the operation. When the GTO thyristor 2 enters the off state first, the GTO thyristor 2 becomes equivalently high in resistance, so that the anode current I ₂ flowing corresponding to the load current I _R is reduced to the snubber circuits 22, 32, 4
Divert to 2. The snubber current I _S2 is the snubber capacitor 32
, And the voltage across the snubber capacitor 32 rises almost linearly (ΔV indicates a voltage due to the amount of overcharge, the same applies hereinafter). At this time, it is assumed that the GTO thyristor 1 is still in the ON state. Across voltage increases of the snubber capacitor 32 from time t ₂ the voltage across V ₂ of the GTO thyristor 2 becomes equal to the voltage E of the DC voltage source 9, the upper arm current I ₁ and the snubber current I _S2 starts attenuation, completely it becomes zero at the time t _3. However, because the reactance of the load current I _R is the load at this time is sufficiently large, it is assumed to maintain a constant value from time t ₂ later,
And freewheel diodes 13 and 14 is on the lower arm, a current flows I _N. Thereafter, at time t4, the GTO thyristor 1 starts to turn off. At this time, the load current I _R has already been completely reduced to the freewheeling diode 1
3,14 has been completed the commutation, the anode current I ₁ is made zero. Here, even if the GTO thyristor 1 becomes equivalently high in resistance, no voltage is applied to the GTO 1 because the entire voltage of the power supply voltage 9 is borne by the GTO 2. Off operation of the GTO thyristor 1 and 2 of the upper arm is completely finished in the above, but only substantially GTO thyristor 2 are cut off the load current I _R, the off after the power supply voltage source 9
Is applied directly to the GTO thyristor 2.

On the other hand, FIG. 3 shows a change in the voltage / current waveform of each part in the inverter circuit when the GTO thyristor 1 is turned off first and then the GTO thyristor 2 is turned off. At time t _1, simultaneous OFF command is turned, first the GTO thyristor 1 enters the off state, since the GTO thyristor 1 becomes equivalent to a high resistance, the anode current I ₁ in the snubber circuit 21, 31, 41 Commutate. Due to the snubber current I _S1 , the voltage between both ends of the snubber capacitor 31 increases and becomes equal to the half voltage E / 2 of the power supply voltage source 9 at time t.
2, the clamp diode 5 is turned on, and the snubber current I
_S1 is commutated to the current I _C1 flowing through the clamp diode 5,
The snubber current I _S1 is attenuated, and the voltage V ₁ across the GTO thyristor 1 is clamped at this half voltage E / 2. Thereafter, at time t ₃ , the GTO thyristor 2 shifts to the off state, and when the resistance becomes equivalently high, the anode current I ₂ becomes the snubber circuit 2
It is commutated to 2, 32 and 42. Due to the snubber current I _S2 , the voltage across the snubber capacitor 32 increases and the power supply voltage source 9
From equal time t ₄ after the half voltage E / 2, freewheeling diodes 13 and 14 of the lower arm is turned on,
Snubber current I _S2 and the current I _C1 flowing through the clamp diode 5 starts to decay completely becomes zero at time t _5. At this time the load current I _R is terminated commutation completely freewheeling diodes 13, 14, GTO thyristor 2
Voltage across V ₂ of the clamp to the intermediate voltage E / 2 at both ends voltages V ₁ and similar power supply voltage source 9 of the GTO thyristor 1, OFF operation is completely finished above.

Here, when comparing the operation of FIGS. 2 and 3, in FIG. 2, when the GTO thyristor 2 is turned off, the total voltage E of the power supply voltage source 9 (actually, an overcharge amount of ΔV is added). ) Is applied, whereas in FIG.
The power supply voltage source 9 is equally applied to the GTO thyristors 1 and 2, respectively.
Is different in that a half voltage E / 2 is applied. In the inverter circuit shown in FIG. 1 in which four semiconductor switch elements equivalent to one are connected in series, the breakdown voltage per semiconductor switch is selected based on the half voltage of the power supply voltage source 9 in order to take advantage of the advantages 1 and 2 described above. Normally, a voltage twice as high as that in the case of FIG. 2 is applied, and there is a possibility that the semiconductor switch element may be damaged by overvoltage. In this case, as described with reference to FIG. 3, by turning off the GTO thyristor 1 first, it is possible to prevent overvoltage breakdown of the semiconductor switch element. Similarly, when the GTO thyristor 3 is turned off first when the lower arm is turned on from off, the entire voltage E of the power supply voltage source 9 is applied, and there is a possibility that overvoltage breakdown of the semiconductor switch element may occur. Also in this case, by turning off the GTO thyristor 4 first, overvoltage breakdown of the semiconductor switch element can be prevented.

FIG. 4 shows a first embodiment of the present invention. FIG. 4 shows an example in which the operation of an electric car (not shown) is controlled using the output of an inverter. Reference numeral 17 denotes an operation command control board for issuing an operation command by a notch operation, and reference numeral 18 detects an overvoltage of input and output of the inverter. An overvoltage detector (provided at the input / output terminal of the inverter in FIG. 1), 19 is a protection priority circuit for giving priority to an overvoltage detection signal over an operation command, 20 is a gate drive signal circuit, and 21 is a simultaneous off logic circuit. The simultaneous off logic circuit 21 includes AND gates 101 to 104 and an OR gate 40.
0,500, consists of a delay circuit 200,300, G ₁₀ ~
G ₄₀ is (on 1, off 0) gate drive signals indicating the output terminal of the. During normal operation, the operator operates the Notsuchi operation command control table 17, when a run command is entered to the gate drive signal circuit 20, the gate drive signal circuit 20 simultaneously turns off the gate drive signals G ₁₀ ~G ₄₀ from the logic circuit 21 Emit to In this case, the ON command 1 is input from the operation command control board 17 to the simultaneous OFF logic circuit 21 via the protection priority circuit 19. The AND gates 101 to 104 simultaneous off logic circuit 21, the gate drive signal G ₁₀ ~G ₄₀ and on command 1 is inputted, the gate drive signal G ₁₀ ~G ₄₀ is GTO thyristor 1-4 gate G ₁ ~G ₄ to control on / off of the GTO thyristors 1 to 4 to drive an electric vehicle (not shown). by the way,
Now, in order to turn off the inverters all at once, when the simultaneous off command 0 is input from the operation command control board 17 to the simultaneous off logic circuit 21 (1 → 0), the outputs of the AND gates 101 to 104 become the gate drive signals G _{10 to} G _10. 0, regardless of ₄₀ , G
TO thyristors 1 and 4 immediately shift to the off state. On the other hand, GTO thyristors 2 and 3 include delay circuits 200,
Despite the simultaneous OFF command 0 due to the delay action of 300,
The ON state can be forcibly continued for a certain time via the OR gates 400 and 500. As a result, the GTO thyristors 1 and 4 are turned off before the GTO thyristors 2 and 3, and then the GTO thyristors 2 and 3 are turned off. As a result,
GTO thyristors 2 and 4 before GTO thyristors 1 and 4
3 is never turned off. Further, when an overvoltage due to, for example, regenerative braking occurs on the input side of the inverter during normal operation, or when an overvoltage occurs on the output side of the inverter, the overvoltage detector 18 outputs a detection signal to turn off the inverter simultaneously. The signal is issued to the protection priority circuit 19. The protection priority circuit 19 sends a simultaneous OFF command 0 by a detection signal to the simultaneous OFF logic circuit 21 prior to the operation command from the operation command control board 17. The simultaneous off logic circuit 21
By the same operation as described above, the GTO thyristors 1, 4
Turns off before GTO thyristors 2 and 3,
GTO thyristors 2 and 4 before GTO thyristors 1 and 4
3 is never turned off.

FIG. 5 shows a second embodiment of the present invention. The configuration of the simultaneous off logic circuit is different from that of the first embodiment of FIG. 4, and the other components are the same. In FIG. 5, the simultaneous OFF logic circuit 22 is connected to the anodes of the GTO thyristors 1 and 4.
Voltage detectors 51 and 54 are added between the cathodes, and comparators 600 and 700 for comparing the outputs of the voltage detectors 51 and 54 with the voltage detection levels C ₁ and C ₂ are provided.
It is characterized in that the magnitude of the voltage level is determined at 00, and the determined value is incorporated in the logic. Hereinafter, only this feature will be described. Now, when the simultaneous OFF command 0 is input, when there is no voltage between the anode and the cathode of the GTO thyristors 1 and 4, that is, when the GTO thyristors 1 and 4 are on, the outputs of the voltage detectors 51 and 54 are It is smaller than the voltage detection levels C ₁ and C ₂ and the comparators 600 and 70
The output of 0 is 0, and the gates G ₂ , G ₃ are forcibly kept on by the gate drive signals G ₂₀ , G ₃₀ of the GTO thyristors ₂ , ₃ . The voltage detectors 51 and 54 detect that the GTO thyristors 1 and 4 are turned off and a voltage is generated between the anode and the cathode.
When the voltage detection levels C ₁ and C ₂ become higher than the above, the OR gates 800 and 900 permit the gate drive signals G ₂₀ and G ₃₀ of the gates G ₂ and G ₃ to be set to 0 for the first time.
As a result, the GTO thyristors 1 and 4 are turned off before the GTO thyristors 2 and 3, and as a result, the GTO thyristors 2 and 3 are not turned off before the GTO thyristors 1 and 4.

[0012]

As described above, according to the present invention,
When the inverter during operation is stopped, by specifying the order of turning off each semiconductor switch element, even if the semiconductor switch element has a variation in operating characteristics, aging occurs during use of the semiconductor switch element. Therefore, even if the operation time varies, a specific element does not become overvoltage state for each semiconductor switch element, and it is possible to prevent the cause of the breakdown voltage before it occurs. It can be done safely and reliably. Further, according to the present invention, there is no need to determine in advance the difference in the off-time of each semiconductor switch element as in the prior art, and an inverter including an arm can be formed easily and quickly.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an inverter circuit to which the present invention is applied.

FIG. 2 shows the voltage / current waveform of each part in the destruction mode

FIG. 3 shows a voltage / current waveform of each part in the destruction prevention mode.

FIG. 4 shows a first embodiment of the present invention.

FIG. 5 shows a second embodiment of the present invention.

[Explanation of symbols]

 1,2,3,4 GTO thyristor 21,22,23,24 Snubber diode 31,32,33,34 Snubber capacitor 41,42,43,44 Snubber resistor 5,6 Clamp diode 7,8 Filter capacitor 9 DC power supply 10, 11, 12 Wiring inductance 13, 14, 15, 16 Freewheel diode 17 Operation command control stand 18 Overvoltage detector 19 Protection priority circuit 20 Gate drive signal circuit 21, 22 Simultaneous off logic circuit 101, 102, 103, 104 AND Circuit 400, 500, 800, 900 OR circuit 200, 300 Delay circuit 600, 700 Comparator 51, 54 Voltage detector

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/48 H02M 1/00 H03K 17/10 H03K 17/725 H02M 7/515

Claims (3)

(57) [Claims] An arm formed by serially connecting a plurality of self-extinguishing semiconductor switch elements is connected in a bridge and connected between the positive and negative electrodes of a DC power supply, and the self-extinguishing means belonging to an arbitrary arm is connected. In an inverter that converts DC into AC by turning on and off a semiconductor switch element, when the inverter stops operating from an operating state,
An inverter device comprising: means for turning off the turn-off operation of the semiconductor switch element belonging to each of the arms first from an element located closer to the positive electrode side or the negative electrode side. 2. The device according to claim 1, wherein the means for turning off the semiconductor switch element belonging to each arm first from an element located closer to the positive electrode side or the negative electrode side comprises logic circuit means, Alternatively, after a predetermined time elapses after an element located near the negative electrode side is turned off, an element located in the middle is turned off. 3. The device according to claim 1, wherein the means for turning off the turn-off operation of the semiconductor switch element belonging to each arm first from an element located closer to the positive electrode side or the negative electrode side comprises logic circuit means. A voltage detector is provided on each output side of the element to be turned off, and after confirming that the voltage on the output side of the element to be turned off is equal to or higher than a predetermined value, the element located in the middle is turned off. Inverter device.