JP3079956B2 - Printer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a printer that receives image data and control data transmitted from an external device and forms an image.

[0002]

2. Description of the Related Art Conventionally, in order to receive image data supplied from an external device, for example, a host computer at high speed, such as a printer described in Japanese Patent Application Laid-Open No. 64-36326, the image data is directly transmitted. A printer that transfers data to a memory in the printer by a memory access (hereinafter, referred to as DMA) method is known.

A printer adopting the conventional DMA system is
The system includes a CPU for controlling the printer, a memory for storing image data, and a DMA controller for transferring image data directly to the memory without the intervention of the CPU. The CPU, the memory, and the DMA controller are connected to each other by a common bus.

In a printer adopting this DMA system,
After the CPU instructs the DMA controller to transfer the image data, the DMA controller transfers the image data, so that the CPU does not need to write the image data to the memory, and the image data reception can be speeded up. it can.

[0005]

However, in the conventional printer, since the CPU, the memory, and the DMA controller are common, that is, connected by one bus, the DMA controller transfers the image data to the memory. During this time, the bus is occupied by the DMA controller, so that the CPU cannot control the printer at all.

Therefore, if a large amount of image data is continuously transferred by the DMA controller, the CPU cannot control the printer until the transfer of the image data is completed.
There is a problem that the image forming speed of the printer is reduced.
In this case, even if the image data receiving speed increases, the image forming speed decreases, so that the effect of reducing the processing time including the image data receiving time and the image forming time is small.
Further, there is a problem that even if any abnormality occurs in the printer during transfer of image data by the DMA controller, the CPU cannot immediately cope with the abnormality.

On the other hand, the amount of image data transferred by the DMA controller at one time is reduced so that the CPU does not hinder the control of the printer. For example, each time the DMA controller transfers 1-byte data, If the bus is surrendered, there is a problem that the receiving speed of the image data is reduced.

An object of the present invention is to provide a printer capable of controlling the printer even while receiving image data.

Another object of the present invention is to provide a printer capable of receiving image data supplied from an external device at a high speed without lowering the image forming speed of the printer.

[0010]

In order to achieve this object, in the printer according to the first aspect, the receiving means receives image data and control data supplied from an external device. The control data received by the receiving unit is supplied to the control unit via the first bus, and the control unit controls the image forming unit according to the control data.

On the other hand, the image data received by the receiving means is supplied to the transfer means via the second bus, and is transferred to the storage means via the second bus and stored by the transfer means.

Further, in the printer according to the second aspect, in addition to the printer according to the first aspect, the number of image data successively transferred by the transfer unit to the storage unit is arbitrarily set by the data number setting unit. Is done. Each time the number of image data set by the data number setting means is transferred to the storage means by the transfer means by the mode switching means, Switching to an interrupt mode in which the control means can receive control data via the receiving means is performed.

Furthermore, in the printer according to the third aspect,
In addition to the printer according to claim 1, a first bus is connected to the storage means, and the first bus is connected to the control means by the arbitration means.
Access to the storage means via the second bus and access to the storage means via the second bus by the transfer means are arbitrated.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an electrical configuration of a laser printer according to an embodiment of the present invention.
The laser printer 1 is connected to a personal computer 4 (hereinafter, referred to as a PC) as a host computer, and forms an image on a medium such as plain paper in accordance with image data and control data supplied from the PC 4. The laser printer 1 has an engine 2 including various mechanisms such as an image forming mechanism for forming an image by a laser system and a paper feeding mechanism, and a controller 3 for controlling the engine 2. The engine 2 is the same as an existing laser printer, and a detailed description thereof will be omitted.

The PC 4 supplies image data and control data to the laser printer 1. The image data is data obtained by compressing bitmap data representing an image by a predetermined method, and the control data is data representing a resolution, data representing a page break, and the number of image data to be transmitted at one time (hereinafter, referred to as “data”). Data representing the total number of bytes of the block).

The controller 3 is connected to the PC 4 and
An interface 10 for receiving image data and control data from C4, an 8-bit CPU 11 for receiving control data via the interface 10 and controlling the entire printer, and a ROM 12 for storing a control program executed by the CPU 11. A RAM 13 provided with various work memories, etc., an engine controller 14 for outputting a control signal to the engine 2 based on a command from the CPU 11, and a DRAM 16 for storing image data.

The interface 10, CPU 11,
ROM 12, RAM 13, engine controller 14,
The DRAMs 16 are mutually connected by a CPU bus 21. The engine controller 14 and the engine 2
They are connected by a plurality of signal lines 23.

The controller 3 receives the image data via the interface 10 and a decoding circuit 18 for expanding the compressed image data, transfers the image data to the DRAM 16, and reads out the image data stored in the DRAM 16. A DMA controller 17 that transfers the image data to the decoding circuit 18 and a line buffer 19 that outputs the image data expanded by the decoding circuit 18 to the engine 2 as a video signal are provided.

The interface 10 and the decoding circuit 1
8, the DRAM 16, and the DMA controller 17 are interconnected by a local bus 22. Decoding circuit 1
8 and the line buffer 19 are connected by a dedicated bus 24, and the line buffer 19 and the engine 2 are connected to the signal line 2
5 is connected.

The DRAM 16 is connected to both the CPU bus 21 and the local bus 22 in order to enable access by the CPU 11 and access by the DMA controller 17. Therefore, they are connected to the CPU bus 21 and the local bus 22 via the arbitration circuit 15. The arbitration circuit 15 includes the CPU 1
1 and the DMA controller 17
Access to the RAM 16 is permitted.

Elements other than the DRAM 16 of the controller 3 are ASIC (Application Specified Integrate).
d Circuit; application-specific type IC) on a single chip.

The interface 10 switches between an interrupt mode for supplying control data supplied from the PC 4 to the CPU via the CPU bus 21 and a transfer mode for supplying image data supplied from the PC 4 to the DMA controller 17. . Hereinafter, a circuit configuration of a portion related to the mode switching function of the interface 10 will be described with reference to FIG.

The interface 10 is connected to the CPU 8
Bit data bus DI [07. . 00]. The register 50 includes the CPU 1
The number of block data is set by “1”, and each time the DMA controller 17 transfers a 1-byte control signal received from the interface 10 to the DRAM 16, a down count is performed.

The signals input to the interface 10 include a reset signal RESET supplied from a reset IC (not shown), a strobe signal STROBE supplied from the PC 4, a system clock signal SCLK supplied from an oscillator (not shown), and a CPU 11 A write signal IOWR supplied from the CPU 11, a chip select signal CCMDCS supplied from the CPU 11 for setting the register 50, a bus use permission signal CBG supplied from the arbitration circuit, supplied from the CPU 11, and sets the lower 8 bits of the register 50 Select signal BTL for performing
CS1, a chip select signal BTLC supplied from the CPU 11 for setting the middle 8 bits of the register 50
S2, supplied from the CPU 11, the upper 6
Chip select signal BTLCS for setting bits
3. The DRAM 16 which is supplied from the DMA controller 17 and has one byte of image data by the DMA controller 17
Transfer end signal CDMAE indicating that transfer to
ND and the like.

The signals output from the interface 10 include an interrupt signal STBINT for interrupting the CPU 11 according to a strobe signal STROBE supplied from the PC 4 in the interrupt mode, and transfer of image data to the DRAM 16 by the DMA controller 17 is started. At this time, the local bus 22
A bus request signal CBR for requesting access to the DRAM 16 through the CPU, and a transfer start signal CDMAE for instructing the DMA controller 17 to start transfer of image data.
NA and the like.

The signals generated inside the interface 10 include an inverted clock signal SCLKB obtained by inverting the system clock signal SCLK, and a mode switching signal GMOD for switching between an interrupt mode and a transfer mode.
E, a count value zero signal GMODECLR indicating that the count value of the register 50 has become zero, and the like.

Next, the operation of the laser printer 1 will be described. When the power of the laser printer 1 is turned on,
A reset signal RESET is supplied to the interface 10 by the reset IC. When the reset signal RESET is supplied to the interface 10, the D flip-flop 51 is cleared, the mode switching signal GMODE output from the D flip-flop 51 becomes low level, and the interrupt mode is set. While the interrupt mode is set, the data supplied from PC4 is
All are supplied from the interface 10 to the CPU 11 via the CPU bus 21. In the interrupt mode, since the DMA controller 17 does not access the DRAM 16, the CPU 11
Check.

Next, the image data receiving process will be described with reference to the timing chart of FIG. Note that the symbols P, C, D, and
Q, J, and K represent a preset terminal, a clear terminal, a D terminal, a Q terminal, a J terminal, and a K terminal, respectively.

In the interrupt mode, when a strobe signal STROBE is supplied from the PC 4 to the interface 10, an interrupt signal STBINT is output from the interface 10 and the CPU 11 is interrupted. Subsequently, control data representing the resolution and control data representing the total number of blocks, for example, 64 KB (kilobytes) are supplied to the CPU 11 from the PC 4 via the interface 10 and the CPU bus 21. The total number of bytes of the block can be set to any value that is most efficient according to the capacity of the PC 4, for example, the capacity of the RAM included in the PC 4.

The CPU 11 performs a resolution setting process according to the control data representing the resolution. The CPU 11
The write signal IOW is sent to the interface 10 in accordance with control data representing the total number of bytes of the block, 64 KB.
R, chip select signals BTLCS1, BTLCS2,
BTLCS3 is supplied, and 00FFFF representing 64 KB is stored in the register 50 via an 8-bit data bus.
Set H. Subsequently, the CPU 11 supplies the chip select signal CCMDCS and the write signal IOWR to the interface 10 and writes high-level data to the D flip-flop 51. Thus, the mode switching signal GMODE output from the D flip-flop 51
Becomes high level, and the transfer mode is set. While the transfer mode is set, all data supplied from the PC 4 is transmitted from the interface 10 to the local bus 2.
2 to the DMA controller 17.

In this state, when a strobe signal is supplied from the PC 4 to the interface 10, reception of the first byte of image data is started. The interface 10 outputs a bus request signal CBR to the arbitration circuit 15, and outputs the DRA via the local bus 22 by the DMA controller 17.
Request access to M16. Bus request signal CB
R from the arbitration circuit 15 in response to the
Is supplied to the interface 10, the interface 10 outputs the PC signal following the strobe signal STROBE.
4 supplies the one-byte image data received from the DMA controller 17 to the DMA controller 17 and outputs a transfer start signal CDMAENA to the DMA controller 17. The DMA controller 17 transfers the first byte of image data to the DRAM 16 via the local bus 22 and writes the image data at a predetermined address of the DRAM 16. DR of 1 byte image data
Upon transfer to the AM 16, the DMA controller 17 supplies a transfer end signal CDMAEND to the interface 10. When the transfer end signal CDMAEND is supplied, the interface 10 releases the bus request signal CBR.
The register 50 performs a down-counting operation of subtracting 1 from the set total number of data blocks in response to the transfer end signal CDMAEND.

In this state, the strobe signal S from the PC 4 is output.
When TROBE is supplied to the interface 10, 2
The reception of the byte image data is started, and the same processing as the reception of the first byte image data is performed. In this way, the reception of the image data is repeated one byte at a time, and when the 64 KB image data is transferred to the DRAM 16 by the DMA controller 17, the count value of the register 50 becomes zero and the register 50 becomes a flip-flop and a gate circuit. Count value signal GMODE via
Outputs CLR. Count value zero signal GMODECL
When R is output, the D flip-flop 51 of the interface 10 is cleared, the mode switching signal GMODE output from the D flip-flop 51 becomes low level, and the interrupt mode is set.

In this interrupt mode, when a strobe signal STROBE is supplied from the PC 4 to the interface 10, an interrupt signal STBINT is output from the interface 10 and the CPU 11 is interrupted. Then, from PC4, interface 10, CPU
Control data representing the resolution and control data representing the total number of bytes of the block, 64 KB, are transmitted to the CPU 21 via the bus 21.
11 and a second process of receiving 64 KB image data is performed. In this manner, 64 KB of image data is continuously transmitted to the DRAM by the DMA controller 17.
The transfer mode is switched to the interrupt mode every time the transfer is made to the transfer mode. Each time the CPU 11 switches to the interrupt mode, the CPU 11 checks whether 64 KB of image data is normally received without excess or deficiency. If the image data has not been received normally, the CPU 11 executes error processing such as requesting the PC 4 to stop transmitting the image data.

In this way, the controller 3
The reception of image data for each KB is repeated. PC4 is 1
The image data for a page is divided into 64 KB blocks, and transmission is performed for each block repeatedly. However, the number of image data may be less than 64 KB for a block immediately before a page break. In such a case,
The PC 4 supplies control data representing a value different from 64 KB to the interface 10 as control data representing the total number of blocks in the interrupt mode before transmitting the image data of the block immediately before the page break.

When the transfer of the image data of the block immediately before the page break by the DMA controller 17 is completed, the interface 10 switches the transfer mode to the interrupt mode. In this state, if there is image data of the next page, the control data indicating the page break, the control data indicating the resolution, and the control data indicating the total number of blocks, that is, the control data indicating 64 KB are transmitted from the PC 4 to the interface 1.
0, and the above-described image data receiving process is repeated. If there is no image data for the next page, PC4
Is supplied to the interface 10 from the control data representing the page break.

Next, the image forming process will be described. When control data indicating a page break is supplied from the interface 10 to the CPU 11 via the CPU bus 21, C
The PU 11 causes the engine 2 to start an image forming operation. That is, the CPU 11 instructs the engine controller 14 to drive the image forming mechanism, the sheet feeding mechanism, and the like. The engine controller 14 outputs a control signal to the engine 2 according to a command from the CPU 11, and starts driving the engine 2.

On the other hand, the CPU 11
0, a command is issued to the DMA controller 17 to read out the image data stored in the DRAM 16. CPU1
In accordance with the instruction 1, the DMA controller 17 accesses the DRAM 16 via the local bus 22 and
The reading of the image data stored in the memory 16 starts. D
The MA controller 17 reads the image data from the DRAM 16 one line at a time and transfers it to the decoding circuit 18 via the local bus 22. The decoding circuit 18 expands the compressed image data and supplies it to the line buffer 19 via the dedicated bus 24. Line buffer 19
Generates a video signal according to the supplied image data, and supplies the video signal to the engine 2 via the signal line 25.

As described above, the control signal from the engine controller 14 is supplied to the engine 2 by the line buffer 1.
9 supplies a video signal, and the engine 2 performs a laser-type image forming operation. The control of the engine 2 by the CPU 11 is executed via the CPU bus 21,
DRAM 1 for image data by DMA controller 17
6 is performed via the local bus 22, the image data receiving process and the image forming process can be performed simultaneously when image data for a plurality of pages is supplied from the PC 4. Time can be reduced.

In the above embodiment, the PC 4 serves as an external device, the engine 2 serves as an image forming means, the interface 10 serves as a receiving means, the CPU 11 serves as a controlling means, and the C
The PU bus 21 corresponds to a first bus, the DRAM 16 corresponds to a storage unit, the DMA controller 17 corresponds to a transfer unit, and the local bus 22 corresponds to a second bus. The register 5
0 corresponds to the data number setting unit, the D flip-flop 51 corresponds to the mode switching unit, and the arbitration circuit 15 corresponds to the arbitration unit.

[0041]

As is apparent from the above description, in the printer according to the first aspect, of the data supplied from the external device, the control data is transmitted from the receiving means to the control means via the first bus. The image data is supplied from the receiving unit to the transfer unit via the second bus, and is stored in the storage unit via the second bus by the transfer unit. Since the transfer of the image data by the transfer means is performed via the second bus, it is possible that the first bus to which the control means is connected is occupied by the transfer means during the transfer of the image data by the transfer means. Absent.

Therefore, even while receiving image data,
The control means can control the image forming means. As a result, even when a large amount of image data is continuously transferred by the transfer unit, the image forming speed of the image forming unit is not reduced, and the processing time including the image data receiving time and the image forming time is reduced. Is achieved. Further, if any abnormality occurs in the printer during the transfer of the image data by the transfer means, the control means can promptly deal with it. Further, since the amount of image data transferred by the transfer means at one time is reduced, and it is not necessary to surrender the bus to the control means, high-speed reception of image data becomes possible.

Further, in the printer according to the second aspect, every time the number of image data set arbitrarily by the data number setting means is transferred to the storage means by the transfer means,
Switching from the transfer mode to the interrupt mode is performed by the mode switching means.

Therefore, when a large amount of image data is supplied from the external device to the printer, the control means is given an opportunity to communicate with the external device before all the image data is supplied from the external device. Thus, when the image data is not normally received or when any abnormality occurs in the printer, the control unit can cope before all the image data is supplied from the external device.

The external device divides all image data to be supplied to the printer into a plurality of blocks based on the number of data set by the data number setting means, creates image data for each block, and sends the image data to the printer. You only need to supply them. That is, the external device does not start supplying image data to the printer after creating all image data,
When the image data for the block has been created, the supply of the image data to the printer is started, and the image data of the next block may be created while supplying the image data to the printer.
As a result, the image data creation by the external device and the reception of the image data and the image formation by the printer can be performed simultaneously in parallel, so that the processing time of the entire system including the external device and the printer can be reduced. become.

Further, since the data number setting means can set an arbitrary number of data, an optimum number of data can be set according to the capacity of the memory of the external device. Even when the memory of the external device is small, the printer can cope with the image data transmission of the external device so as not to hinder the transmission by reducing the number of data set by the data number setting unit.

Furthermore, in the printer according to the third aspect,
The arbitration unit arbitrates between the control unit accessing the storage unit via the first bus and the transfer unit accessing the storage unit via the second bus. Therefore, not only the transfer means but also the control means can access the storage means, and the control means can check the storage means.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a laser printer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a portion related to a mode switching function of an interface of the laser printer.

FIG. 3 is a timing chart showing image data reception processing of the laser printer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Laser printer 2 Engine 3 Controller 4 Personal computer 10 Interface 11 CPU 15 Arbitration circuit 16 DRAM 17 DMA controller 21 CPU bus 22 Local bus 50 Register 51 D flip-flop

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/00-1/00 108 H04N 1/21 B41J 5/00-5/52 B41J 29/00-29/70

Claims (3)

(57) [Claims] 1. A printer for forming an image in accordance with image data and control data supplied from an external device, an image forming means for forming an image, and an image connected to the external device and supplied from the external device. Receiving means for receiving data and control data; control means for controlling the image forming means according to control data supplied from the external device; and a second means for connecting the receiving means and the control means. 1 bus, storage means for storing image data supplied from the external device, and transfer of image data supplied from the external device to the storage means directly without passing through the control means. A printer comprising: a transfer unit; and a second bus for connecting the reception unit, the storage unit, and the transfer unit. 2. The printer according to claim 1, wherein the transfer unit sets an arbitrary number of image data to be continuously transferred to the storage unit, and the transfer unit performs the reception. A transfer mode for making image data receivable via the means, and a mode switching means for switching between an interrupt mode for making the control data receivable via the receiving means, Wherein the mode switching means switches the transfer mode to the interrupt mode each time the number of image data set by the data number setting means is transferred to the storage means by the transfer means. . 3. The printer according to claim 1, wherein said first bus is connected to said storage means, and said control means accesses said storage means via said first bus, and said transfer means. Arbitration means for arbitrating access to the storage means via the second bus according to (1).