JP3079534B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a highly integrated semiconductor memory device.
The present invention relates to a semiconductor memory device capable of shortening a channel length of a MOS transistor in a peripheral circuit section in a DRAM or the like.

[Summary of the Invention]

In the memory device of the present invention, in a memory device having a MOS transistor in each of a memory cell portion and a peripheral circuit portion, after forming a gate electrode of the MOS transistor in the memory cell portion, a gate electrode of the MOS transistor in the peripheral circuit portion is formed. By forming the source and drain regions of the MOS transistor in the peripheral circuit portion in a self-aligned manner with the gate electrode on the upper portion, diffusion of the source and drain region of the MOS transistor in the peripheral circuit portion due to heat treatment is prevented. Another object of the present invention is to reduce the channel length of a MOS transistor in a peripheral circuit section to achieve high integration and high speed of a memory device.

[Conventional technology]

In a semiconductor memory device having a MOS transistor in each of a memory cell portion and a peripheral circuit portion of a DRAM or the like, as the integration of the semiconductor memory device increases, the cell area decreases and the memory capacity in the memory cell portion increases. Have been. As a method of increasing the memory capacity, a so-called stack type in which the memory capacity is three-dimensionally stacked is known.

FIG. 4 shows a conventional DRAM having a stacked memory cell.
It is sectional drawing of an example. As shown in FIG. 4, the DRAM has MOS transistors in the memory cell section and the peripheral circuit section, respectively. The MOS transistors in the memory cell section are separated from each other by an element isolation region 51 on a silicon substrate 50, and are turned on and off by a gate electrode 53 formed on the silicon substrate 50 via a gate oxide film 52. This gate electrode 53 is made of a first polysilicon layer. One of the source / drain regions 54 of the MOS transistor is connected to a second polysilicon layer 56 functioning as a storage node via an opening in the interlayer insulating film 55. The second polysilicon layer 56, an insulating film 57 formed to cover the second polysilicon layer 56, and a third polysilicon layer serving as a cell plate on the insulating film 57. A capacitor is formed between the capacitor and the layer 58. Also, the source of the MOS transistor
The other of drain region 54 is connected to aluminum wiring layer 60 through an opening in interlayer insulating film 55. The aluminum wiring layer 60 is formed on an interlayer insulating film 59 that extends over the interlayer insulating film 55 so as to cover the third polysilicon layer 58.

On the other hand, in the peripheral circuit portion, source / drain regions 64 are formed in a region surrounded by the element isolation region 51 on the surface of the silicon substrate 50 so as to be separated from each other. This source / drain region 64
A gate electrode 63 is formed on the channel forming region between the gate electrodes via a gate oxide film 52. The gate electrode 63 is patterned at the same time as the gate electrode 53, and is made of the first polysilicon layer. An interlayer insulating film 55 extending over element isolation region 51 covering gate electrode 63 is formed. The interlayer insulating film 55 has an opening on the source / drain region 64, and a wiring layer 65 connected to the source / drain region 64 via the opening is formed on the interlayer insulating film 55. .

[Problems to be solved by the invention]

Has a conventional stack-type memory cell as described above
In DRAM, the gate electrode 6 of the MOS transistor in the peripheral circuit section
3 and the source / drain regions 64 are formed in the same process as the gate electrode 53 and the source / drain regions 54 of the MOS transistor in the memory cell portion. That is, after the gate electrodes 53 and 63 are formed by the first polysilicon layer, ion implantation is performed using the gate electrodes 53 and 63 as a mask to form the source / drain regions 54 and 64 in a self-aligned manner. .

However, in such a semiconductor memory device, a heat treatment is performed in a process after the formation of the source / drain regions 54 and 64, so that the impurities in the source / drain regions 64 of the MOS transistor in the peripheral circuit portion are subjected to the heat treatment. Spread. As a result, the channel length of the MOS transistor in the peripheral circuit section is shortened, and the short channel effect causes a problem such as an increase in the threshold value.

In order to prevent such a problem, in a conventional semiconductor memory device such as a DRAM, it is necessary to increase the channel length of a MOS transistor in a peripheral circuit portion in advance, and there is a limit in reducing the channel length. Therefore, it has been difficult to achieve high integration and high speed of the semiconductor memory device.

Therefore, the present invention has been proposed in view of such a conventional situation, and has as its object to reduce the channel length of a MOS transistor in a peripheral circuit portion and to achieve high integration and high speed of a memory device. And

[Means for solving the problem]

In order to solve the above-described problems, a semiconductor memory device according to the present invention includes, in a semiconductor memory device having a MOS transistor in each of a memory cell portion and a peripheral circuit portion, wherein a MOS transistor is formed in the memory cell portion,
A capacitor connected to the source or the drain is formed on the source or the drain of the MOS transistor, and the gate electrode of the MOS transistor in the peripheral circuit portion is formed on the substrate by an upper conductive layer and a lower layer constituting the capacity of the memory cell portion. An oxide film, a nitride film, and an oxide film formed between the conductive layers are formed through an insulating layer that is stacked in the order of the oxide film, and formed by an upper conductive layer that constitutes a capacity of the memory cell portion. The source / drain region of the MOS transistor in the peripheral circuit portion is formed in a self-aligned manner with the gate electrode of the MOS transistor in the peripheral circuit portion by ion implantation after the source / drain region of the MOS transistor in the memory cell portion is formed. It is.

[Action]

The semiconductor memory device according to the present invention has a
The gate electrode of the transistor is provided in the memory cell portion
Since the MOS transistor in the peripheral circuit portion is formed after forming the MOS transistor in the memory cell portion, the MOS transistor is formed over the source or drain of the MOS transistor by forming an upper conductive layer constituting a capacitor connected to the source or drain. You. The source / drain regions of the MOS transistor in the peripheral circuit are also formed in a self-aligned manner with the gate electrode of the MOS transistor in the peripheral circuit by ion implantation after the source / drain regions of the MOS transistor in the memory cell are formed. Further, the gate electrode of the peripheral circuit portion is formed on the substrate via an insulating film formed between an upper conductive layer and a lower conductive layer constituting the capacitance of the memory cell portion. The insulating film is formed on the substrate by stacking an oxide film, a nitride film, and an oxide film in this order, thereby preventing deterioration of device characteristics due to a hot carrier effect.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

In the present embodiment, in a DRAM having a stack type memory cell, the MO of the memory cell portion is controlled by the first polysilicon layer.
In this example, a gate electrode of an S transistor is formed, and a cell plate of a memory cell portion and a gate electrode of a MOS transistor of a peripheral circuit portion are simultaneously formed using a third polysilicon layer.

First, the structure of the semiconductor memory device of this embodiment will be described with reference to FIG.

In the memory cell section, an element isolation region 2 is formed on the surface of a p-type silicon substrate 1. A gate electrode 4 made of a first polysilicon layer is formed on the gate oxide film 3 formed on the silicon substrate 1 and on the device isolation region 2 in a pattern having a predetermined space therebetween. The gate electrode 4 controls ON / OFF of the MOS transistor in the memory cell section. The surface of the silicon substrate 1 is
An n ⁺ -type impurity region 5 which is a source / drain region of the MOS transistor is formed. One of the impurity regions 5 is connected to the second polysilicon layer 7 through the opening of the interlayer insulating film 6. The second polysilicon layer 7 extends on the interlayer insulating film 6 between the adjacent gate electrodes 4,
Functions as a storage node. An insulating film 8 having an ONO structure (a stacked structure of an oxide film / nitride film / oxide film) is formed to cover the second polysilicon layer 7, and a third layer of the same pattern is formed on the insulating film 8 in the same pattern. Polysilicon layer 9 is laminated. The third polysilicon layer 9 functions as a cell plate, and a capacitance is formed between the third polysilicon layer 9 and the second polysilicon layer 7. This capacitance is provided three-dimensionally by utilizing the step of the interlayer insulating film 6, and the capacitance is formed on the upper surface and the side wall of the second polysilicon layer 7, so that a large memory capacitance can be obtained. A sidewall film 11 made of a silicon oxide film or the like is formed on side walls of the third polysilicon layer 9 and the insulating film 8. An interlayer insulating film 12 having an opening 17 on the other impurity region 5 of the MOS transistor is formed on the entire surface including the third polysilicon layer 9. On this interlayer insulating film 12, a wiring layer 10 as a bit line is formed by an aluminum layer or the like. This wiring layer 10 is connected to the other of impurity regions 5 at opening 17 of interlayer insulating film 12. The charge accumulated in the second polysilicon layer 7 is read out to the wiring layer 10 via the impurity region 5 when the MOS transistor is turned on.

On the other hand, in the peripheral circuit portion, an insulating film 8 functioning as a gate oxide film is formed on a region surrounded by the element isolation region 2 on the surface of the silicon substrate 1. Since the insulating film 8 has an ONO structure, deterioration of device characteristics due to the hot carrier effect is prevented.

A gate electrode 14 of a MOS transistor in a peripheral circuit portion is formed on the insulating film 8, and a side wall film 11 made of a silicon oxide film or the like is provided on a side wall thereof. The gate electrode 14 is formed of a third polysilicon layer, similarly to the cell plate of the capacitor provided in the memory cell portion. That is, the gate electrode 14 is formed above the gate electrode 4 of the MOS transistor in the memory cell section, and is formed after the step of forming the MOS transistor in the memory cell section is completed.

N ⁻ formed in such a manner as to be self-aligned with the gate electrode 14.
A mold impurity region 15 is provided on the surface of silicon substrate 1. This impurity region 15 is formed by ion implantation using the gate electrode 14 as a mask. Since the gate electrode 14 is formed after the process of forming the MOS transistor in the memory cell portion is completed, the number of times the impurity region 15 undergoes heat treatment after the MOS transistor in the memory cell portion is formed,
The expansion of the impurity region 15 due to the heat treatment is suppressed. Therefore, the channel length of this MOS transistor is shortened,
High integration and high speed of the memory device can be achieved.

An n ⁺ -type impurity region 16 is formed on the surface of the silicon substrate 1 in a self-aligned manner with the sidewall film 11.
As described above, the MOS transistor in the peripheral circuit section has the LDD structure, so that the concentration of the electric field at the drain can be reduced.

An interlayer insulating film 12 extending over element isolation region 2 covering gate electrode 14 is formed. This interlayer insulating film 12 has an opening on impurity region 16. Wiring layer 20 connected to impurity region 16 through the opening of interlayer insulating film 12 is formed.

Here, a method for manufacturing the semiconductor memory device of the present embodiment will be described.

As shown in FIG. 2A, an element isolation region 22 is formed on a p-type silicon substrate 21 by a LOCOS method or the like, and a gate oxide film 23 is formed selectively with the element isolation region 22.

Then, in the memory cell portion, a gate electrode 24 having a predetermined pattern is formed on the gate oxide film 23 and the element isolation region 22 by using the first polysilicon layer. This gate electrode 24
Using n as a mask, n ⁺ -type impurity region 25 is formed on the surface of silicon substrate 21 by ion implantation. This impurity region 25 functions as the source / drain region of the MOS transistor in the memory cell section. In this step, the gate electrode 24, the impurity region 25, and the like are not formed in the peripheral circuit portion.

Then, after an interlayer insulating film 26 made of a silicon oxide film or the like is formed on the entire surface of the memory cell portion including the gate electrode 24 except for the peripheral circuit portion, etching is performed using a mask for opening the connection hole 26a. . As a result, a connection hole 26a is formed in the interlayer insulating film 26 and the gate oxide film 23 in one of the impurity regions 25 of the MOS transistor, and one of the impurity regions 25 is exposed. This connection hole 26a is opened to connect the MOS transistor in the memory cell portion to the capacitor.

As shown in FIG. 2 (b), in the memory cell portion, the second hole extending over the interlayer insulating film 26 by filling the connection hole 26a is formed.
A polysilicon layer 27 as a layer is formed. The second polysilicon layer 27 has a pattern in which an end portion is located above the adjacent gate electrode 24, and the impurity region 2 is formed by the connection hole 26a.
Connected to one of the five. Such a second polysilicon layer 27 functions as a storage node portion.

Subsequently, an insulating film 28 having an ONO structure is formed on the entire surface of the memory cell portion and the peripheral circuit portion. This insulating film 28 functions as a gate oxide film of the MOS transistor in the peripheral circuit portion.

Then, as shown in FIG. 2C, after a third polysilicon layer 29 is laminated on the entire surface of the insulating film 28, the third polysilicon layer 29 is patterned.
Due to this patterning, in the memory cell portion, the third polysilicon layer 29 remains in a pattern covering the upper surface and side walls of the second polysilicon layer 27, and at the same time, the gate is formed on the insulating film 28 in the peripheral circuit portion. An electrode 34 is formed. The third polysilicon layer 29 in the memory cell portion functions as a cell plate, and a capacitance is formed between the third polysilicon layer 29 and the second polysilicon layer 27 via the insulating film 28. By forming such a stack-type capacitor, a large memory capacity can be obtained. Thus, the cell plate of the capacity of the memory cell portion and the gate electrode 3 of the MOS transistor of the peripheral circuit portion are provided.
4 at the same time, the M
The gate electrode 34 of the OS transistor is formed above the gate electrode 24 of the MOS transistor in the memory cell portion, and is formed after the process of forming the MOS transistor in the memory cell portion is completed.

Subsequently, a resist layer 41 is applied to the upper part of the memory cell part. Then, ions of phosphorus or the like are implanted using the gate electrode 34 of the peripheral circuit portion as a mask, and an n ⁻ -type impurity region 35 is formed on the surface of the silicon substrate 21 only in the peripheral circuit portion in self-alignment with the gate electrode 34. This impurity region 35 is
Relieves the electric field concentration in the source / drain regions of MOS transistors. This impurity region 35 is formed after the step of forming the MOS transistor in the memory cell portion is completed. For this reason, for example, the MO of the memory cell portion is subjected to an annealing process performed after the impurity region 25 is formed by performing ion implantation.
The number of times of performing the heat treatment after the S transistor is formed is reduced. Therefore, since the expansion of the impurity region 35 due to the heat treatment is suppressed, the channel length of the MOS transistor in the peripheral circuit portion can be reduced, and high integration and high speed of the memory device can be achieved.

After ashing of the resist layer 41, a silicon oxide film or the like is formed on the entire surface of the memory cell portion and the peripheral circuit portion. Then, the entire surface is etched back to form the sidewall film 31 on the side wall of the gate electrode 34 in the peripheral circuit portion. At this time, the third polysilicon layer 29 in the memory cell portion is used.
Further, a sidewall film 31 is also formed on the side wall of the insulating film 28.

As shown in FIG. 2D, arsenic or the like is ion-implanted only into the surface of the silicon substrate 21 in the peripheral circuit portion using a resist layer 42 having the same pattern as the resist layer 41 used in the above-described ion implantation. As a result, an n ⁺ -type impurity region 36 is formed in a self-aligned manner with the sidewall film 31, and a MOS transistor having an LDD structure is formed.

As described above, in the present embodiment, the gate electrode 34 of the MOS transistor in the peripheral circuit portion is patterned simultaneously with the cell plate of the capacity of the memory cell portion by using the third polysilicon layer. Using the gate electrode 34 as a mask, ion implantation is performed to obtain the source
By forming the drain region, the number of times that the source / drain region undergoes heat treatment after the MOS transistor in the memory cell portion is formed is reduced. Therefore, diffusion due to the heat treatment occurs, so that the channel length of the MOS transistor in the peripheral circuit portion can be reduced, and high integration and high speed of the semiconductor memory device are realized.

In this embodiment, at the connection between the wiring layer 10 and the impurity region 5, a wiring is formed using an aluminum layer, but the opening 17 is previously buried using a SOG (spin-on-glass) film. Thereafter, the wiring layer 10 may be formed. That is, as shown in FIG. 3, first, a film functioning as a barrier metal having a thickness of 1000
A Ti film or a TION film 18 of about Å is formed. This Ti film or
An SOG (spin-on-glass) film 19 is formed on the TiON film 18 and the like, buried in the opening 17, flattened at the connection portion, and then sputtered to form an aluminum layer having a thickness of about 3000 mm. To form a wiring layer 10. Thus, SO
By embedding the inside of the opening 17 using the G film 19, good step coverage can be obtained even if the aspect ratio of the opening 17 increases. In addition, since the flatness of the connection portion is ensured, the thickness unevenness of the wiring layer 10 on the opening 17 is prevented.

〔The invention's effect〕

As described above, in the present invention, since the MOS transistor in the peripheral circuit portion is formed after the MOS transistor in the memory cell portion is formed, diffusion of impurities in the source / drain regions of the MOS transistor in the peripheral circuit portion due to heat treatment is suppressed. Therefore, even if the channel length of the MOS transistor in the peripheral circuit section is shortened, there is no possibility that a problem due to the short channel effect will occur. Therefore, high integration of the semiconductor memory device can be achieved. Further, since the channel length of the MOS transistor in the peripheral circuit section is short, high speed can be realized.

Further, in the present invention, the gate electrode of the MOS transistor in the peripheral circuit portion and the cell plate in the memory cell portion are formed using the same polysilicon layer. Higher speed is possible.

Further, in the present invention, by forming the gate insulating film of the MOS transistor in the peripheral circuit portion at the same time as the insulating film of the capacity in the memory cell portion having the ONO structure, characteristic deterioration due to hot carriers is suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an essential part of an example of a semiconductor memory device of the present invention, and FIGS. 2 (a) to 2 (d) are process cross-sectional views for explaining a manufacturing method thereof in the order of manufacturing steps.
FIG. 3 is an enlarged sectional view of a main part of a memory cell portion of an application example in an example of the semiconductor memory device of the present invention, and FIG. 4 is a sectional view of an example of a conventional semiconductor memory device. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Element isolation region 3 ... Gate oxide film 4, 14 ... Gate electrode 5, 15 ... Impurity region 6, 12 ... Interlayer insulating film 7 ... Second polysilicon layer 8 insulating film 9 third polysilicon layer 10, 16 wiring layer 11 sidewall film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (1)

(57) [Claims] A MOS transistor is provided in each of a memory cell section and a peripheral circuit section.
In a semiconductor memory device having a transistor, a MOS transistor is formed in the memory cell portion, and a capacitor connected to the source or drain is formed on a source or a drain of the MOS transistor. The gate electrode of the MOS transistor is stacked on the substrate in the order of an oxide film, a nitride film, and an oxide film formed between the upper conductive layer and the lower conductive layer constituting the capacitor of the memory cell portion. And a source / drain region of a MOS transistor in the peripheral circuit portion, the source / drain region of the MOS transistor in the peripheral circuit portion being formed by an upper conductive layer constituting a capacitance of the memory cell portion. After the source / drain regions are formed, ion implantation is performed to form a self-aligned gate electrode of the MOS transistor in the peripheral circuit section. The semiconductor memory device characterized in that it is.