JP3077439B2 - Matrix substrate and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix substrate and, more particularly, to a low-resistance scanning line and a high withstand voltage between a scanning line and a signal line which are effective in a large-area active matrix image display device. And a method of manufacturing the same.

[0002]

2. Description of the Related Art Due to recent advances in microfabrication technology, liquid crystal materials, packaging technology, and the like, television images and various image displays of a size of about 3 to 15 inches, which do not hinder practical use of liquid crystal panels, are commercially available. Have been obtained. By forming an RGB color layer on one of the two glass plates constituting the liquid crystal panel, color display can be easily realized,
In a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk and a high contrast ratio is guaranteed.

Such a liquid crystal panel has a standard matrix organization of about 120 to 960 scanning lines and about 240 to 2,000 signal lines. For example, the liquid crystal panel 1 is configured as shown in FIG. A COG (Chip-chip) for directly connecting a semiconductor integrated circuit chip 3 for supplying a drive signal to a scanning line electrode terminal group 6 formed on one glass substrate 2.
On-Glass) method, or a connection film 4 based on, for example, a polyimide-based resin thin film and having a gold-plated copper foil terminal group (not shown) is fixed to an electrode terminal group 5 of a signal line while being pressed with an adhesive. An electric signal is supplied to the image display unit by a mounting means such as a system that performs the operation. Here, two mounting methods are shown simultaneously for convenience, but it goes without saying that one of the mounting methods is actually selected. Note that 7,
Reference numeral 8 denotes a wiring path that connects the image display unit at the center of the liquid crystal panel 1 to the electrode terminals 5 and 6 for signal lines and scanning lines, and does not necessarily need to be formed of the same conductive material as the electrode terminals.

[0004] 9 is a transparent conductive counterpart common to all picture elements.
Another glass plate having electrodes , the two glass plates 2 and 9 are formed at a predetermined distance of about several μm by a spacer such as quartz fiber or plastic beads, and the gap is formed between the sealing material and the sealing member. It is a closed space sealed with a material, and the closed space is filled with liquid crystal.

In order to realize color display, an organic thin film containing either or both of a dye and a pigment called a colored layer is applied to the closed space side of the glass plate 9 to provide a color display function. The glass substrate 9 is also called a color filter. And depending on the properties of the liquid crystal material, the glass plate 9
A polarizing plate is stuck on one or both of the upper surface and the lower surface of the glass plate 2, and the liquid crystal panel 1 functions as an electro-optical element.

FIG. 8 is an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each pixel. The elements drawn by solid lines are formed on one glass substrate 2 and the elements drawn by broken lines are formed on the other glass substrate 9. Scan line 1
1 (8) and the signal line 12 (7) are formed on the glass substrate 2 simultaneously with the formation of the thin film transistor 10 using, for example, amorphous silicon as a semiconductor layer and a silicon nitride film (Si ₃ N ₄ ) as a gate insulating film. Is done.

The liquid crystal cell 13 is composed of a transparent conductive picture element electrode formed on the glass substrate 2, an opposite transparent conductive electrode 15 formed on the color filter 9, and two glass plates. It is composed of liquid crystal that fills a closed space, and is electrically treated the same as a capacitor. In order to align the liquid crystal molecules in a predetermined direction, it is necessary to form an alignment film on the counter electrode and the picture element electrode, but the details are omitted here.

Although the storage capacitor 16 in FIG. 8 is not always an essential component for an active type liquid crystal panel, it improves the efficiency of use of a driving signal source, suppresses stray parasitic capacitance, and operates at high temperatures. In order to prevent flickering of the image at the time, it is effective and appropriately adopted.
Reference numeral 17 denotes a conductive path common to all the storage capacitors 16, and generally, 15 and 17 are connected and used.

Although it is hard to say that the insulated gate transistor as a switching element has been almost industrially uniform from the viewpoint of both material and process, FIGS. 9 and 10 show two cases. FIGS. 11 and 1 show typical plane pattern layouts and cross-sectional views taken along lines AA 'and BB' of FIG.
2, the manufacturing process of the insulated gate transistor will be briefly described below.

First, an insulating gate is formed on one main surface of the glass substrate 2.
The metal layer 11 which also functions as the gate electrode and the scanning line of the transistor is formed on the metal layer 11 using a vacuum film forming apparatus such as sputtering.
It is deposited with chromium (Cr) having a thickness of 1 μm, and a selective pattern is formed. Next, in the case of the insulated gate type transistors shown in FIGS. 9 and 11, three layers of SiNx-a.Si-SiNx are formed by P-CVD (plasma film formation).
4-0.05-0.1 μm is continuously deposited, and the uppermost SiNx layer serving as an etching stopper is selectively left at 20 to form an amorphous silicon layer containing impurities on the entire surface. Similarly, it is deposited by P-CVD. Then, an amorphous silicon layer containing impurities (n + a.Si) and an amorphous silicon layer containing no impurities (a.Si) are formed as semiconductor layers in the form of islands to form 21 and 22, and the gate insulating layer 23 is selected. Exposure. Opening 2 for connection to scanning line 11
4 is formed on the gate insulating layer 23 to expose a part of the scanning line 11, and the gate wiring 25 including aluminum (Al) having a thickness of, for example, 1 μm and the island-like semiconductor layer including the opening 24 are formed. The source / drain wirings 26 and 27 are selectively formed on the substrate, and the amorphous silicon layer containing impurities on the etching stopper layer 20 is selectively removed by using the source / drain wirings 26 and 27 as a mask for insulation. The gate transistor is completed.

In the case of the insulated gate transistor shown in FIGS. 10 and 12, Si is formed by P-CVD (plasma film formation).
The three layers of Nx-a.Si-n + a.Si are, for example, 0.4
An amorphous silicon layer (n + a.Si) containing impurities and an amorphous silicon layer (a.Si) containing no impurities are continuously deposited with a film thickness of -0.1-0.1 μm as semiconductor layers. The gate insulating layer 23 is selectively exposed by forming islands 21 and 22 in an island shape. After an opening 24 for connection to the scanning line 11 is formed in the gate insulating layer 23 to expose a part of the scanning line 11, a gate wiring including the opening 24 and made of, for example, aluminum having a thickness of 1 μm is formed. Source / drain wirings 26 and 27 are selectively formed on the semiconductor layer 25 and the island-shaped semiconductor layer, and only the amorphous silicon layer 21 containing impurities in the semiconductor layer is formed using the source / drain wirings 26 and 27 as a mask. It is selectively removed to complete the insulated gate transistor.

For the purpose of enhancing the reliability of the active type liquid crystal panel, it is common to form an insulating film such as SiNx for securing the passivation function on the entire surface of any insulated gate type transistor, but the details are omitted here. I do.
In order to improve the heat resistance of the insulated gate transistor, Ti (titanium) or Cr is used as a barrier metal between the source / drain wirings 26 and 27 made of Al and the amorphous silicon layer 21 containing impurities. In the present invention, a technique for interposing a metal thin film layer or a silicide thin film layer, and a technique relating to the timing and method of forming a pixel electrode made of ITO are omitted.

[0013]

In P-CVD (plasma film formation), the substrate temperature during film formation is as low as about 300 ° C., and the walls in the reaction chamber, RF electrodes or metal trays for loading the substrate, etc. SiNx and a.Si adhered to the surface of the substrate are separated and float in the reaction chamber as dust or foreign matter of about 1 μm, and adhere to a film-formed substrate such as a glass substrate. As a result, a large number of pinholes are formed in the formed film. It is known that a short circuit occurs in the multilayer wiring via SiNx and the yield does not increase.

[0014] Such an approach for reducing minute dust and foreign matter is generally treated as know-how, and is rarely disclosed externally. However, with respect to the device structure and the manufacturing method that are less susceptible to dust and foreign matter, some examples of improvement have been demonstrated from a technical point of view. In FIG. 13, representative examples are selected and described.

In FIG. 13, the scanning line (gate) 11 is made of Ta (tantalum) so that the figure of merit of the insulated gate transistor does not decrease even if the gate insulating layer is thickly applied.
And the surface thereof is made into a Ta ₂ O ₅ layer 28 having a high dielectric constant by anodic oxidation, followed by SiNx-a.Si-Si.
After three layers of Nx, an insulated gate transistor is manufactured. That is, the gate insulating layer has a _two- layer structure of the Ta ₂ O ₅ layer 28 and the SiNx layer 23.

According to the above-described manufacturing method, it is apparent that the dielectric strength between the scanning line 11 and the source / drain wirings 26 and 27 is improved and the yield is increased for the following reasons.

[0017] Because the one where formation of the Ta ₂ O ₅ layer 28 is performed by chemical solution, hardly influenced by dust, Ta ₂
The O ₅ layer 28 has few pinholes. And in two, the formation of the gate insulating layer is divided into two times,
This is because if a cleaning step is introduced during that time, removal of dust and foreign matter is promoted, and pin holes are reduced at random. Third, the shoulder portion of the scanning line 11 is rounded by anodic oxidation, so that the coverage characteristics of the gate insulating layer 23 are improved and the gate insulating layer 23 is less susceptible to dust and foreign matter. Is improved.

However, with respect to lowering the resistance of the scanning line, the conventional improved example in which the constituent material of the scanning line is Ta or an alloy of Ta and Mo is insufficient. Lowering the resistance of the scanning lines becomes an essential design item as the screen size increases, but for that purpose, it is necessary to use a metal with lower resistance from the material side, and from the device side, it is necessary to increase the thickness of the wiring path. It is necessary. In particular, as the thickness of the wiring path increases,
The required increase in the thickness of the gate insulating layer becomes an unacceptable condition from the viewpoint of a decrease in the figure of merit of the insulated gate transistor and a decrease in the productivity.

Therefore, as one improvement example, it is easy for a person skilled in the art to easily form a scan line of low resistance Al (aluminum). This is because Al can be easily insulated by anodic oxidation like Ta. However, it has been found that there are some problems as described below when a scanning line is formed by using Al instead of the conventional Ta and the surface is to be insulated by anodic oxidation.

One reason is that, because of its porosity, Al in a thin film having a thickness of about 0.1 to 0.3 μm is easily recrystallized by a heat treatment, and irregularities are easily generated on the surface. For example, even when various heat treatments of at most about 150 ° C. are performed in a photosensitive resin patterning process for forming a scanning line, the photosensitive resin is kept at 0.1 mm.
Irregularities of about 05 μm are generated, and in the case where the developer is alkaline, the degree of the irregularities is further promoted in combination with weak etching and film reduction.

As a result, the dielectric breakdown voltage of the Al ₂ O ₃ film formed by anodizing is reduced by about 20 to 50%. In order to avoid a decrease in the dielectric strength, it is necessary to suppress the occurrence of irregularities caused by the heat treatment. For this purpose, for example, a means of mixing several percent or less of various additives such as Si or Ta into Al. There is. However, this countermeasure has the side effect that the resistance value increases and the dielectric strength decreases as the additive material increases, and the process for removing the additive remaining on the substrate at the time of etching Al and improving the chemical resistance. Industrially unfavorable increases in the number of manufacturing steps occur, such as the necessity of forming an insulating thin film on a glass substrate.

The second problem is that a new problem arises in a method of electrically connecting the scanning line itself made of Al. For example, as described above, a photosensitive resin is
A part of the scanning line is protected, and then an opening is formed in an insulating layer of SiNx or the like formed on Al to form an Al layer.
Is partially exposed, the reaction between SiNx and Al causes a considerable loss of Al in the opening (depending on the formation temperature of SiNx) (hillock formation of Al). In addition, restrictions such as the necessity of using an expensive dry etching apparatus for etching SiNx occur, which is industrially disadvantageous.

[0023]

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and does not cause a decrease in dielectric strength when anodic oxidizing the surface of a scanning line made of Al and facilitates connection to the scanning line. In order to make it smooth, a metal layer or a silicide layer for protecting the Al surface is introduced.

[0024]

In order to protect the scanning line surface made of Al with a heat-resistant metal layer or a silicide layer, it is possible to prevent the Al surface from being recrystallized by a heat treatment or a developing solution in a patterning process, thereby causing irregularities. .

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Detailed embodiments of the present invention will be described below. For convenience, members having the same functions are given the same numbers as in the conventional example.

First, as shown in FIG. 1, a 0.3 μm-thick Al film is formed on one main surface of an insulating substrate, for example, a glass plate 2.
As a metal layer, Cr having a thickness of 0.1 μm is deposited and formed by a vacuum film forming apparatus such as sputtering to obtain 30 or 31. The above film formation should preferably be performed continuously, but there is no problem even if a cleaning step is interposed between the Al film formation and the Cr film formation for the sake of particle generation and convenience in equipment operation.

Next, the photosensitivity corresponding to the scanning line pattern
A resin pattern 32 is formed, the Cr layer 31 and the Al layer 30 are etched, and a photosensitive resin pattern 32 is removed after forming a laminated pattern 33 of Cr and Al as shown in FIG. Prior to the anodic oxidation of Al, as shown in FIG. 5, a photosensitive resin pattern 34 is formed near the connection to the scanning line,
FIG. 2 is a cross-sectional view showing a state in which Cr on Al is selectively removed to form an exposed portion 35 of Al. Then, the Al layer 35 is selectively anodized using the photosensitive resin pattern 34 as a mask, and a 0.15 μm-thick Al ₂
FIG. 3 shows a state in which the O ₃ layer 36 is formed. After the anodization is completed, the photosensitive resin pattern 34 is removed,
Through a three-layer deposition of SiNx-a.Si-SiNx in the same manner as in the conventional example, a matrix substrate having an insulated gate transistor according to the present invention is completed as shown in FIGS.

In FIG. 6, reference numeral 37 denotes a Cr layer partially formed on the Al layer 35; and 38, a plurality of Al layers 35 extended to the periphery of the substrate for anodic oxidation.
FIG. 3 schematically shows a cutting line for separating the two.
Regarding the separation of the plurality of Al layers 35, the gate wiring 25
The opening 39 is formed simultaneously with the formation of the opening 24 for connection to the
After the formation of the source / drain wirings 26 and 27, a method of removing Cr and Al in the opening 39 can also be selected. Further, the large opening 2 can be formed without using the gate wiring 25.
The use of the Cr layer exposed in the opening 24 for forming the electrode layer 4 as the electrode terminal 6 of the scanning line is a design matter in device design.

Although Cr is used as the metal layers 31 and 37, it is important that the heat resistance is higher than that of Al and that the metal layers 31 and 37 are not affected by the chemical used in the patterning step of the photosensitive resin. Widely, Ti, Ta, M
Other metals such as o can be used. Mo, Ta,
It is clear that there is no problem even if silicide containing a metal such as W or Cr is used. When silicide is employed, an amorphous silicon layer containing impurities on the etching stopper layer 20 using the source / drain wirings 26 and 27 as a mask is used. The characteristic that the silicide layer is removed at the same time in the step of selectively removing is desirable industrially from the viewpoint of avoiding an increase in the number of manufacturing steps.

[0030]

As is clear from the above description , the present invention
According to this, a scan line made of low-resistance Al is protected by a metal layer or a silicide layer having high heat resistance until it is anodized. Therefore, it is possible to perform anodic oxidation while keeping the surface smoothness high, and it is possible to form an insulating film having a high withstand voltage of the Al ₂ O ₃ layer as the formed insulating film, in other words, to form an insulating film having excellent film quality. Can get
I can do it. Also, in the process of partially removing other insulating films on the scanning lines, processing using chemicals such as hydrofluoric acid is possible with an inexpensive wet processing equipment, which reduces the equipment cost industrially. Is done. Similarly, regarding the supply of electrical signals to the scanning lines, when used as connection terminals, the metal surface or the silicide layer covers the surface of Al, making it hard to be damaged and chemically stable compared to Al Excellent effects such as high degree of use and easy use are obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a process of forming an aluminum layer, a metal layer, and a photosensitive resin in a manufacturing process of one embodiment of a matrix substrate of the present invention.

FIG. 2 is an explanatory view of a step of selectively forming an aluminum layer and a metal layer and a step of selectively removing a metal layer in a manufacturing process of the substrate of the embodiment.

FIG. 3 is an explanatory view of a step of selectively oxidizing an aluminum layer in a manufacturing process of the substrate of the example.

FIG. 4 is an explanatory diagram of a process of forming an insulated gate transistor in a process of manufacturing the substrate of the example.

FIG. 5 is a plan view of the step shown in FIG. 2;

FIG. 6 is a plan view of an insulated gate transistor portion formed on the substrate of the example.

FIG. 7 is an external view showing a mounted state of a liquid crystal panel.

FIG. 8 is an equivalent circuit diagram of an active liquid crystal panel.

FIG. 9 is a plan view of an insulated gate transistor in a conventional liquid crystal panel.

FIG. 10 is a plan view of an insulated gate transistor in a conventional liquid crystal panel.

FIG. 11 is a sectional view of an insulated gate transistor in a conventional liquid crystal panel.

FIG. 12 is a sectional view of an insulated gate transistor in a conventional liquid crystal panel.

FIG. 13 is a cross-sectional view of another conventional insulated gate transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 liquid crystal panel 2 (active) matrix substrate 3 semiconductor chip 4 connection film 5, 6 (connection) electrode terminal of signal line and scanning line 9 color filter 10 insulating gate type transistor 11 scanning line 12 signal line 13 liquid crystal cell 20 (For etching stopper) SiNx layer 21 Amorphous silicon layer containing impurities 22 Amorphous silicon layer containing no impurities 23 Gate insulating layer (of SiNx) 25 Gate wiring 26, 27 Source / drain wiring 28 Ta ₂ O ₅ Layer 30, 35 Al layer 31, 37 Metal layer or silicide layer 32, 34 Photosensitive resin pattern 33 Laminated pattern, 36-Al ₂ O ₃ layer 38 Cutting line 39 Opening

Claims (2)

(57) [Claims] A signal line formed on one main surface of an insulating substrate and formed of an aluminum layer having an anodized surface, and intersecting with the scanning line through an insulating layer or an insulating layer and a semiconductor layer. Image table on the matrix substrate on which
A matrix having a metal layer or a silicide layer having the same width as the width of the aluminum layer formed on a part of the aluminum layer in a region outside the indicated portion as a connection point of an electric signal to the scanning line . substrate. 2. A step of continuously depositing and forming an aluminum layer and a metal layer or a silicide layer on one main surface of an insulating substrate, and using a first photosensitive resin pattern to form the aluminum layer and the metal layer. or selectively forming a <br/> stacked pattern of more becomes scan line the silicide layer, selectively a second photosensitive resin pattern comprising a portion of the stacked pattern
Forming, during the second photosensitive resin pattern
A step of selectively exposing the aluminum layer by selectively removing the metal layer or a silicide layer as a disk,
Selectively anodizing the aluminum layer using the second photosensitive resin pattern as a mask, and forming and selecting an insulating layer and a semiconductor layer after removing the second photosensitive resin pattern. manner by patterning and forming an insulated gate tiger <br/> Njisuta, forming an opening for external terminal connection for the scan lines in the insulating layer on the metal layer or a silicide layer, the scanning Insulation layer or insulation on wire
A signal line orthogonal to the scanning line via a layer and a semiconductor layer.
Forming a matrix substrate.