JP3070570B2 - Terminal load automatic setting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal load automatic circuit for setting a resistance value corresponding to a characteristic impedance of a terminal when connecting the terminal load to a circuit pattern for transmitting a high-frequency signal such as a clock signal on a circuit board. Related to setting device.

[0002]

2. Description of the Related Art Conventionally, when a high-frequency signal is supplied to a load, for example, when the input impedance at the feeding point of the antenna is different from the output impedance of the power output terminal of the transmitter and the characteristic impedance of the feeding cable, the progress of the supplied high-frequency power increases. A reflected wave is generated for the wave. That is, since a so-called standing wave (SWR) is generated, the characteristic impedance is matched. Also, at the end of a transmission path (coaxial cable) of a home bus type network such as CATV, a terminating load (mainly a resistor) is used in order to avoid attenuation of a video signal due to a standing wave at a connection position of the video receiving device. Is connected.

Similarly, a termination load is connected to a motherboard on which electronic components of various logic circuits are surface-mounted. This is because when a clock signal from a clock generator or the like is supplied to a logic circuit through a circuit pattern, the output impedance of the clock generator, the transmission line (circuit pattern), and the characteristic impedance of the clock signal input terminal of the logic circuit to which the clock signal is supplied are This is because the clock signal is reflected and a standing wave is easily generated. In particular, capacitive reflection due to the mounting capacitor and the stray capacitance at the clock signal input terminal is likely to occur. Note that a high-frequency signal different from the pulsed clock signal, for example, a transmission output terminal that transmits transmission power through a circuit pattern in a transmission system mounted on a circuit board of a mobile phone or the like also has a standing wave due to reflection similar to the clock signal. Is easy to occur.

When such reflection occurs, a reflected wave with respect to the traveling wave is generated on the same transmission line (circuit pattern), and the level of the clock signal is attenuated. Therefore, it is necessary to provide a waveform shaping circuit for the clock signal and an amplifying buffer. Also, when the reflected wave with respect to the traveling wave flows through the same transmission line (circuit pattern), waveform distortion occurs, and the noise becomes a noise source that radiates the higher-order frequency signal.
It may be mixed into other data processing circuits and cause data errors. Furthermore, radiation noise may be mixed into an external device. In other words, data processing using a higher-speed clock signal and processing of a higher-frequency signal are difficult to perform.

For this improvement, a Thevenin terminating load based on the so-called Thevenin theorem (reciprocity theorem) for connecting a terminating load between a clock signal input terminal of a buffer or a logic circuit and ground is often used. . The Thevenin termination load solves the above-mentioned problem caused by the difference between the output impedance (Za) of the clock generator (active circuit) and the input impedance (Zb) of the clock signal supply terminal (passive circuit) of the logic circuit to which the clock signal is supplied. I am trying to do it. In this case, the output impedance (Za) of the active circuit serving as an open end and the input impedance (Zb) of the passive circuit are determined by the length of the circuit pattern for transmitting the clock signal, the rise and fall of the clock signal, and the rise and fall of the circuit board. It depends on the material.

For this reason, in a three-dimensional motherboard,
The arrangement for connecting the terminating resistor (terminating load) is complicated.
In other words, in the three-dimensional configuration, a small individual circuit board that performs individual operations is placed on the layout board in order to increase the mounting efficiency of electronic components compared to planar mounting on a single circuit board, and to upgrade the version at a later date. It is mounted (removed) vertically on the provided connector. In this configuration, it is necessary to supply a clock signal from a clock generator mounted on one individual circuit board or an arrangement board to many other individual circuit boards. Therefore, a Thevenin-terminated load is arranged for each of a large number of individual circuit boards.

In this case, a Thevenin termination load for each length (corresponding to the characteristic impedance of the termination) of a circuit pattern (transmission line) disposed between a number of individual circuit boards for supplying a clock signal from the clock generator. Need to be set. As the Thevenin termination load, for example, a resistor is connected between a power supply line and an input terminal of a clock signal amplification buffer or a logic circuit, and a DC cut capacitor is connected between the input terminal and ground. A configuration in which a resistor and a resistor are connected in series is well known. In the Thevenin terminal load, the characteristic impedance is determined by calculating from the stray inductance L, the stray capacitance C ', the path resistance R', etc. together with the capacitance C and the resistance value R of the capacitor.

The Thevenin terminating load set in this way has many floating elements with indeterminate circuit constants at the input terminals of buffers and logic circuits, as well as stray inductance L, stray capacitance C 'and path resistance R. ’
Since the value is extremely small, it is substantially determined by the resistance value of the resistor provided between the input terminal of the buffer or the logic circuit and the ground. Also, there is no need to make the actual characteristic impedance at the input terminal of the buffer or logic circuit exactly the same as the characteristic impedance at the end of the circuit pattern for clock signal transmission, making it easy to set the Thevenin terminating load. For this reason, in many cases, a Thevenin-terminating load is set by connecting resistors having approximately the same resistance to the terminating ends of the circuit patterns for transmitting clock signals having somewhat different lengths.

[0009]

As described above, in the above conventional example, when a circuit for supplying a large number of clock signals is arranged on an arrangement board or in a three-dimensional configuration in which an individual circuit board is mounted on a connector, the length is small. There is a disadvantage that the setting operation for connecting a resistor forming a Thevenin terminal load having a value corresponding to the characteristic impedance of the terminal for each different wiring pattern is troublesome.

The present invention is to solve such a problem in the conventional technology, and divides a large number of circuits for supplying a high frequency signal such as a clock signal into a plurality of groups each having the same characteristic impedance. It is an object of the present invention to provide a terminal load automatic setting device which can automatically set a resistance value for forming a Thevenin terminal load for each group, and can easily and surely set the resistance value.

[0011]

In order to achieve the above object, an automatic terminal load setting device according to the present invention is adapted to correspond to a load value at each terminal position of two circuit patterns for supplying a high frequency signal to two circuits. Different first identification code and second
Identification code sending means for sending an identification code, first arrangement position identification means for sending an ON signal when the first identification code sent by the identification code sending means is identified, and second identification sent by the identification code sending means. The second arrangement position identification means for transmitting an off signal when the code is identified, and the respective termination loads of the two circuit patterns are formed based on the on signal or the off signal from the first or second arrangement position identification means. Terminating load setting means for setting the terminating load value corresponding to each of the two circuit patterns by switching the value of the resistor to be set.

[0012] The automatic terminal load setting device of the present invention comprises:
A circuit in which the high-frequency signal is a clock signal and a circuit that supplies the high-frequency signal through a circuit pattern is a buffer or a logic circuit, and a load at an end of the circuit pattern connected to the input terminal of the buffer or the logic circuit is connected to a power supply. And a resistor is connected between the input terminal and
The configuration is such that a capacitor and a resistor are connected in series between the input terminal and the ground to form a Thevenin-terminated load. Alternatively, the first identification code is parallel data consisting of high level, low level and high level, and the second identification code is parallel data consisting of high level, high level and low level.

Further, the automatic terminal load setting device according to the present invention comprises:
The first arrangement position identification means (second arrangement position identification means) performs parallel data comprising high level, low level and high level (high level, high level and low level) as the first identification code (second identification code) A pull-up resistor connected between each of the three transmission lines and the power supply, and high-level, low-level, and high-level (high-level, high-level, and low-level) parallel data through the pull-up resistor The configuration includes a buffer, an inverter, and a buffer to be supplied, and an AND gate that transmits a high-level (low-level) on signal (off signal) obtained by performing an AND process on the parallel data from the buffer, the inverter, and the buffer.

Further, the terminal load automatic setting device of the present invention comprises:
A terminal load in the terminal load setting means is such that a first resistor is connected between a power supply and an input terminal of a buffer or a logic circuit, and a capacitor and a second resistor are connected in series between the input terminal and ground. And a second resistor for setting a terminal load value corresponding to each of the two circuit patterns by an ON signal from the first position identification means or an OFF signal from the second position identification means. And a switching means for switching the value of the container.

Further, the automatic terminal load setting device of the present invention comprises:
The second resistor is a plurality of resistors connected in series, or
A plurality of resistors each having one end grounded, and the switching means is configured to short-circuit or open a part of the plurality of resistors connected in series based on an ON signal or an OFF signal; The switch is configured to switch one end to select one resistor. The second resistor is an electronic variable resistor, and the switching means switches the resistance value by varying the electronic variable resistor based on an ON signal or an OFF signal.

Further, the terminal load automatic setting device of the present invention comprises:
The identification code sending means is surface-mounted on the circuit board, or
Mounted on a first individual circuit board mounted on a first connector arranged on the circuit board, the first or second arrangement position identifying means and the terminating load setting means are mounted on the circuit board together with a circuit for supplying a high-frequency signal. It is configured to be mounted on a second individual circuit board mounted on the arranged second connector. Further, the identification code sending means, the first and second arrangement position identification means, and the termination load setting means are configured to be mounted on one circuit board.

The terminal load automatic setting apparatus of the present invention having such a configuration generates an off signal or an off signal corresponding to the length (characteristic impedance of the terminal) of each of two circuit patterns for supplying a high-frequency signal. . The value of the resistor forming the terminating load at the input terminal of the circuit is switched based on the off signal or the off signal to set the Thevenin terminating load. As a result, a large number of circuits that supply a high-frequency signal such as a clock signal can be divided into a plurality of groups for the same characteristic impedance, and the value of a resistor forming a Thevenin-terminated load for each group can be automatically set. Become like

Further, the terminal load automatic setting device of the present invention comprises:
Based on the off signal or the off signal, the resistance value of the electronic variable resistor forming the terminating load at the input terminal of the circuit is varied, and the Thevenin terminating load is set. As a result, a large number of circuits that supply high-frequency signals such as clock signals are divided into a plurality of groups for the same characteristic impedance, and the values of the electronic variable resistors forming the Thevenin-terminated loads for each of these groups are automatically and automatically determined. It can be freely changed and set.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the terminal load automatic setting device of the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view showing an overall external configuration of a terminal load automatic setting device according to a first embodiment of the present invention. In this example, the individual circuit boards 2, 3A, 3B, 4A, 4B for performing various data processing on a relatively large layout board 1 are connected to connectors 12a,
They are arranged perpendicular to and detachable from 12b, 13a, 13b, 14a, and 14b, and have a so-called three-dimensional arrangement for surface mounting in which electronic components are arranged only on the surface of the arrangement substrate 1. In practice, many individual circuit boards are arranged in addition to the individual circuit boards 2 to 4B.

The individual circuit boards 2 include individual circuit boards 3A to 3A.
A clock generator 2a for supplying a clock signal to 4B is arranged. A clock signal is supplied to the individual circuit board 3A from the clock generator 2a of the individual circuit board 2, and a termination load setting unit 3a for automatically setting a Thevenin termination load with respect to the characteristic impedance at the clock signal input terminal thereof is arranged. An arrangement position identification unit 3b is provided for identifying the self arrangement position on the substrate 1 (corresponding to the length of the circuit pattern from the clock generator 2a (corresponding to the terminal characteristic impedance)).

The clock signal is also supplied to the individual circuit board 4A from the clock generator 2a of the individual circuit board 2,
A terminating load setting unit 4a for automatically setting a resistance value forming a Thevenin terminating load corresponding to the characteristic impedance at the clock signal input terminal, and an arrangement position identifying unit 4b for identifying a self-arranged position on the arrangement substrate 1. Is provided. In addition, on the placement board 1, the individual circuit boards 3A to 4B are used to identify the self-placed positions on the placement board 1 (corresponding to the length of the circuit pattern from the clock generator 2a (the characteristic impedance of the termination)). The identification code (I
D) to each of the individual circuit boards 3A to 4B. Although the individual circuit boards 3B and 4B are not shown in detail, they have the same configuration as the individual circuit boards 3A and 4A, respectively.

The clock generator 2a of the individual circuit board 2
From the circuit patterns 23a and 23b connected to the connector 12a and the connectors 13a and 13b.
To the individual circuit boards 3A and 3B. In this case, the circuit patterns 23a and 23b have substantially the same length. Similarly, the clock signal from the clock generator 2a of the individual circuit board 2 is connected to the circuit patterns 21a and 21b (partially common) connected to the connector 12a and the connector 14
a and 14b to the individual circuit boards 4A and 4B.

In this case, the circuit patterns 21a and 21b have substantially the same length, and the circuit patterns 23a and 23b
The length is different from b. Therefore, the individual circuit board 3
A Thevenin termination load having the same value is set for A and 3B.
In addition, the Thevenin termination loads having the same value are set for the individual circuit boards 4A and 4B, and the Thevenin termination loads having different values from the individual circuit boards 3A and 3B are set.

FIG. 2 is a circuit diagram showing a detailed configuration of the identification code sending section 1a in the placement board 1 in the first embodiment. FIG. 3 is a circuit diagram showing the individual circuit boards 3A, 3B, 3B in the first embodiment.
FIG. 4 is a circuit diagram showing a detailed configuration of arrangement position identification sections 3b and 4b in 4A and 4B. In FIG. 2, an identification code sending unit 1a on the arrangement substrate 1 has an identification code ID0 for identifying an arrangement position on the arrangement substrate 1 (corresponding to the characteristic impedance at the end of the length of the circuit patterns 23a and 23b).
(High level: H), ID1 (Low level: L), ID
The 2 (H) parallel data is sent to the individual circuit boards 3A and 3B. At the same time, the identification code sending section 1a is arranged on the arrangement substrate 1 (corresponding to the length of the circuit patterns 21a and 21b).
ID0 (H), ID1 for identifying
(H), parallel data of ID2 (L) are transferred to the individual circuit board 4
A, 4B.

In FIG. 3, the arrangement position identification sections 3b of the individual circuit boards 3A and 3B are connected to respective data lines (circuit patterns 24) of the parallel data (H, L, H) of the identification codes ID0 to ID2. In order to set initial operation and generate low / high level voltages, for example, pull-up resistors R1, R connected to a plus 5V power supply line
2, R3 and a buffer 3 to which parallel data of parallel data (H, L, H) with identification codes ID0 to ID2 are supplied.
1, an inverter 32 and a buffer 33, and identification codes ID0 from the buffers 31, 33 and the inverter 32.
The parallel data (H, H, H) of ID2 is input, and this A
And an AND gate 34 for transmitting a high-level (H) ON signal to be described later by the ND processing.

The arrangement position identification section 4b on each of the individual circuit boards 4A and 4B is connected to a line (circuit pattern 25) of identification codes ID0 to ID2 to set initial operation and generate low / high level voltages. For example, a pull-up resistor R1 connected to a positive 5V power line
, R12, R13 and the buffer 41, the inverter 42, and the buffer 43 to which the parallel data (H, H, L) of the identification codes ID0 to ID2 are supplied, and the identification codes ID0 to ID2 from the buffers 41, 43, and the inverter 42. And the parallel data (H, L, L) are input and a low-level (L) off signal (OFF) is transmitted by AND processing.
And a gate 44.

FIG. 4 shows an individual circuit board 3 according to the first embodiment.
A, 3B, 4A, 4B terminal load setting units 3a, 4B
FIG. 2 is a circuit diagram showing a detailed configuration of FIG. The terminal load setting units 3a and 4a have the same configuration,
a, a buffer 52 and a logic circuit 53 to which a clock signal is supplied from the clock generator 2a of the individual circuit board 2 through the a, 21b, 23a, 23b;
And a resistor R20 having one end connected to a power supply line for setting a predetermined characteristic impedance with respect to a connection point of a Thevenin-terminated load which is an input terminal of the power supply line.

Further, in the termination load setting sections 3a and 4a, a DC cut capacitor C1 is provided between the input terminal of the buffer 52 and the ground, and a Thevenin termination load is formed between the capacitor C1 and the ground. Series connected resistor R
21, R22, a switch SW for short-circuiting or opening the resistor R22, and a high-level (H) or low-level of an ON signal or an OFF signal from the arrangement position identification sections 3b, 4b shown in FIG. (L) and a drive circuit 51 that outputs a drive signal for setting the switch SW to ON when a high level (H) is supplied from the determination circuit 50. doing.

Next, the operation of the first embodiment will be described. In the first embodiment, the value of the Thevenin terminating load set at the input terminal of the buffer 52 includes many floating elements with uncertain circuit network constants at the input terminal of the buffer 52 and the logic circuit 53, as well as stray inductance and stray electrostatic. Since the capacitance and the path resistance are extremely small, they are substantially determined by the resistances of the resistors R21 and R22 provided between the input terminals of the buffer 52 and the logic circuit 53 and the ground.

Further, in the first embodiment, the buffer 5
2 and the actual characteristic impedance at the input terminal of the logic circuit 53 and the circuit patterns 21a, 21b, 23a, 23
It is not necessary to make the characteristic impedance of the terminal of b extremely strictly the same, which facilitates the setting work of the Thevenin terminal load. That is, a large number of individual circuit boards are divided into a plurality of groups for each identical characteristic impedance, and the Thevenin-terminated load is set for each group by a resistor having the same resistance value. In the example of FIG. 1, the individual circuit boards 3 having substantially the same values of the Thevenin termination loads are provided.
A, 3B and the individual circuit boards 4A, 4B.

FIG. 5 is a flowchart of the operation of the first embodiment. A clock signal from the clock generator 2a of the individual circuit board 2 is supplied to the individual circuit boards 3A and 3B through the circuit patterns 23a and 23b connected to the connector 12a and the connectors 13a and 13b. In this case, the circuit patterns 23a and 23b have substantially the same length. Therefore, the characteristic impedances at the ends depending on the lengths of the circuit patterns 23a and 23b are substantially equal. Here, the resistance value forming the Thevenin termination load is assumed to be 80Ω.

Similarly, a clock signal from the clock generator 2a of the individual circuit board 2 is supplied from the connectors 14a and 14b to the individual circuit boards 4A and 4B through circuit patterns 21a and 21b (partially common) connected to the connector 12a. In this case, the circuit patterns 21a and 21b have substantially the same length. Therefore, the circuit patterns 21a, 21
The characteristic impedances at the ends due to the length of 1b are substantially equal. The resistance value forming the Thevenin termination load here is 10
It is assumed to be 0Ω.

The individual circuit boards 3A and 3B shown in FIG. 1 are mounted on the connectors 13a and 13b (step S1).
The parallel data of the identification codes ID0 (H), ID1 (L) and ID2 (H) are supplied from the identification code sending unit 1a of the arrangement board 1 through the connectors 13a and 13b and the circuit pattern 24 to the arrangement position identification unit 3b. . In the arrangement position identification unit 3b, identification codes ID0 (H), ID1
The parallel data of (L) and ID2 (H) are supplied to the buffer 31 and the inverter 3 through the pull-up resistors R1, R2 and R3.
2 and the buffer 33, from which AND
Input to the gate 34. The AND gate 34 sends a high level (H) ON signal (ON) obtained by AND processing the parallel data (H, H, H) to the termination load setting unit 3a of the individual circuit boards 3A, 3B.

In the termination load setting section 3a, the individual circuit board 2
The clock signal from the clock generator 2a is supplied to the logic circuit 53 through the buffer 52. A resistor R21 (80Ω) forming a Thevenin-terminated load is connected between an input terminal (terminal of the circuit patterns 23a and 23b), which is a clock signal supply terminal of the buffer 52, and ground via a DC cut capacitor C1. Resistor R
22 (20Ω) are connected in series.

An ON signal from the arrangement position identification section 3b of each of the individual circuit boards 3A and 3B is input to the determination circuit 50 of the termination load setting section 3a, where a high level (H) is determined (steps S2 and S3). : Yes), and supplies the high level (H) signal to the drive circuit 51. This drive circuit 5
The switch SW is set to ON by the drive signal from 1 (step S4). As a result, the resistor R22 (20Ω)
Is short-circuited, and the resistance value of the resistor R21 is set to 80Ω at the input terminal of the buffer 52 (the terminal of the circuit patterns 23a and 23b) (step S5). That is, a Thevenin termination load corresponding to the length (characteristic impedance of the termination) of the circuit patterns 23a and 23b is set.

Similarly, the individual circuit boards 4A and 4B shown in FIG.
Are attached to the connectors 14a and 14b. The identification code ID is transmitted from the identification code transmission unit 1a of the arrangement board 1 through the circuit pattern 25 through the connectors 14a and 14b.
The parallel data of 0 (H), ID1 (H), and ID2 (L) is supplied to the arrangement position identification unit 4b. In the arrangement position identification unit 4b, identification codes ID0 (H), ID1 (L), ID2
The parallel data of (H) is a pull-up resistor R11, R1
2, R13, the buffer 41, the inverter 42, and the buffer 43, and are input to the AND gate 44. A
The ND gate 44 receives the identification codes ID0 (H), ID1
(L), parallel data (H, L, L) of ID2 (H)
The ND-processed low-level (L) off signal is sent to the termination load setting unit 4a of each of the individual circuit boards 4A and 4B.

In the termination load setting section 4a, the individual circuit board 2
The clock signal from the clock generator 2a is supplied to the logic circuit 53 through the buffer 52. A resistor R21 (80Ω) and a resistor R22 (20) are connected between the input terminal (the end of the circuit patterns 21a and 21b) of the buffer 52 and the ground through a DC cut capacitor C1.
Ω) are connected in series. Individual circuit boards 3A, 3B
Is input to the determination circuit 50 of the termination load setting unit 4a, and when the low level (L) is determined here, the low level (L) signal is sent to the drive circuit 51. Send out. The switch SW is turned off by the drive signal from the drive circuit 51 (step S6).

As a result, the resistor R22 having a resistance value of 20Ω is not short-circuited, and the resistance value of 100Ω combined with the resistance value of 80Ω of the resistor R21 is set to the input terminal of the buffer 52 (end of the circuit patterns 21a and 21b). (Step S
7). That is, the Thevenin termination load corresponding to the length (characteristic impedance of the termination) of the circuit patterns 21a and 21b is set.

Next, a second embodiment will be described. FIG. 6 shows the individual circuit boards 3A, 3B, 4A,
FIG. 4 is a circuit diagram showing a detailed configuration of terminal load setting units 3a1 and 4a1 in 4B. The terminal load setting units 3a1, 4
a1 has the same configuration, and an electronic variable resistor (electronic volume) that forms a Thevenin termination load in place of the resistor R22 (20Ω) and the resistor R21 (80Ω) of the termination load setting units 3a and 4a in the first embodiment. ) AVR is provided.

The termination load setting section 3a of the second embodiment
In 1 and 4a1, the determination circuit 50 determines the high level (H) or the low level (L) of the ON signal or the OFF signal from the arrangement position identification units 3b and 4b shown in FIG. judge. High level (H) from the judgment circuit 50
Alternatively, a low-level (L) drive signal is sent to the drive circuit 51a.

When a high level (H) drive signal is sent from the drive circuit 51a to the electronic variable resistor AVR, the variable resistance here is set to a resistance value of 80Ω, and the resistance value is set to 8Ω.
0Ω is set to the input terminal of the buffer 52. That is, a Thevenin termination load corresponding to the length (characteristic impedance of the termination) of the circuit patterns 23a and 23b is set. When a low-level (L) drive signal is sent from the drive circuit 51a to the electronic variable resistor AVR, the variable resistance here is set to a resistance of 100Ω, and this resistance is set to 10Ω.
0Ω is set to the input terminal of the buffer 52. That is, the Thevenin termination load corresponding to the length (characteristic impedance of the termination) of the circuit patterns 21a and 21b is set.

In this configuration, an electronic variable resistor AVR is used, and a predetermined desired resistance value, that is, the above-mentioned 80 Ω / A is determined by an ON signal or an OFF signal from the arrangement position identification sections 3b and 4b shown in FIG. It becomes possible to set a resistance value other than 100Ω. Therefore, it is possible to easily cope with a case where the circuit pattern has a length other than the circuit patterns 21a, 21b / 23a, and 23b, and the value of the Thevenin terminal load can be automatically and freely set.

In the first and second embodiments, in the end load setting units 3a and 4a shown in FIG. 4, one of the resistors R22 (80Ω) and R22 (20Ω) connected in series is connected to one of the resistors R22. Although a short circuit is established by the switch SW to set a Thevenin-terminated load with the resistance values of 80Ω and 100Ω, other configurations may be used. For example, two resistors (8
One end of the resistor (0Ω, 100Ω) is grounded, and one end of the other end is selected by a switch to set one of the resistors (80Ω or 100Ω) forming the Thevenin-terminated load at the input terminal of the buffer 52. good.

In the first and second embodiments, the individual circuit boards 3A, 3B, 4A, and 4B are grouped into two groups on the placement board 1, and the circuit patterns 21a, 21b / 2 are formed.
3a, 23b, two different Thevenin termination loads (8
(0 Ω / 100 Ω) has been described above. However, when the individual circuit board of the placement board 1 is divided into three or more groups having different values of the Thevenin termination load, the individual configuration of the three or more groups is similarly configured as described above. The Thevenin termination load on the circuit board can be set.

In this case, as described above, a resistor having a value that forms a Thevenin termination load corresponding to the length (characteristic impedance of the termination) of each circuit pattern for three or more groups of individual circuit boards is provided as follows. What is necessary is just to select and set by the switch with the same configuration and operation as in the first and second embodiments. In other words, generalization of the Devnan termination load setting becomes possible.

Furthermore, in the first and second embodiments, the description has been made with respect to the three-dimensional arrangement.
The clock generator 2a and the termination load setting unit 3
Also, when the a and 4a and the arrangement position identification sections 3b and 4b are surface-mounted, they operate in the same manner as in the first and second embodiments. Further, even in the configuration in which the three-dimensional arrangement and the surface mounting are mixed on the arrangement substrate 1, the same operation as in the first and second embodiments is performed.

[0047]

As is clear from the above description, according to the automatic terminal load setting device of the present invention, the off-state corresponding to the respective lengths (characteristics of the terminal) of the two circuit patterns for supplying the high-frequency signal. The value of the resistor of the terminal load at the input terminal of the circuit is selected based on the signal or the OFF signal, and the setting of the Thevenin terminal load is performed.

As a result, a large number of circuits for supplying high-frequency signals such as clock signals are divided into a plurality of groups for the same characteristic impedance, and the value of the resistor forming the Thevenin-terminated load for each group is automatically adjusted. Can be set to

Further, according to the terminal load automatic setting device of the present invention, the resistance value of the electronic variable resistor forming the terminal load at the input terminal of the circuit is varied based on the off signal or the off signal. , The Thevenin termination load is set.

As a result, a large number of circuits for supplying high-frequency signals such as clock signals are divided into a plurality of groups each having the same characteristic impedance, and the value of the electronic variable resistor forming the Thevenin-terminated load for each group is determined. It can be automatically and freely changed and set.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an overall external configuration of a terminal load automatic setting device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of an identification code transmitting unit shown in FIG.

FIG. 3 is a circuit diagram showing a detailed configuration of an arrangement position identification unit shown in FIG. 1;

FIG. 4 is a circuit diagram showing a detailed configuration of a termination load setting unit shown in FIG.

FIG. 5 is a flowchart of the operation of the first embodiment.

FIG. 6 is a circuit diagram illustrating a detailed configuration of a termination load setting unit according to the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Arrangement board 1a Identification code sending part 2, 3A-4B Individual circuit board 2a Clock generator 3a, 3a1, 4a, 4a1 Termination load setting part 3b, 4b Arrangement position identification part 12a-14b Connectors 21a, 21b, 23a, 23b, 24 , 25 Circuit pattern 31, 33, 41, 43, 52 Buffer 32, 42 Inverter 34, 44 AND gate 53 Logic circuit 50 Judgment circuit 51, 51a Drive circuit AVR Electronic variable resistor C1 Capacitors R1 to R3, R11 to R13, R20 ~ R22 Resistor SW switch

Claims (10)

(57) [Claims] 1. An identification code transmitting means for transmitting different first identification codes and second identification codes corresponding to load values at respective terminal positions of two circuit patterns for supplying a high-frequency signal to two circuits; A first arrangement position identification unit that sends an ON signal when the first identification code sent by the code sending unit is identified, and sends an OFF signal when the second identification code sent by the identification code sending unit is identified. A second arrangement position identification unit, based on an on signal or an off signal from the first or second arrangement position identification unit, switching a value of a resistor forming a terminal load of each of the two circuit patterns, Terminal load setting means for setting a terminal load value corresponding to each of the two circuit patterns. 2. The circuit for supplying the high-frequency signal through a circuit pattern is a buffer or a logic circuit, wherein the high-frequency signal is a clock signal, and a circuit pattern connected to an input terminal of the buffer or the logic circuit. Wherein the load is a Thevenin-terminated load in which a resistor is connected between a power supply and the input terminal, and a capacitor and a resistor are connected in series between the input terminal and ground. 2. The terminal load automatic setting device according to 1. 3. The method according to claim 1, wherein the first identification code is parallel data including high level, low level, and high level, and the second identification code is parallel data including high level, high level, and low level. The automatic terminal load setting device according to claim 1. 4. A pull-up resistor connected between a power supply and three transmission lines for high-level, low-level, and high-level parallel data as the first identification code. A buffer, an inverter, and a buffer to which the high-level, low-level, and high-level parallel data are supplied through the pull-up resistor; and a high-level AND-processed parallel data from the buffer, the inverter, and the buffer. A that sends the ON signal of
The terminal load automatic setting device according to claim 1, further comprising: an ND gate. 5. A pull-up resistor connected between a power supply and three transmission lines for high-level, high-level and low-level parallel data as the second identification code, respectively, and A buffer, an inverter, and a buffer to which the high-level, high-level, and low-level parallel data are supplied through the pull-up resistor; and a low-level AND-processed parallel data from the buffer, the inverter, and the buffer. A that sends off signal of
The terminal load automatic setting device according to claim 1, further comprising: an ND gate. 6. A terminal load in the terminal load setting means, wherein a first resistor is connected between a power supply and an input terminal of a buffer or a logic circuit, and a capacitor and a capacitor are connected between the input terminal and ground. And a termination signal corresponding to each of the two circuit patterns by an on signal from the first location identification means or an off signal from the second location identification means. 2. The terminal load automatic setting device according to claim 1, further comprising a switching unit that switches a value of the second resistor for setting a value. 7. The method according to claim 7, wherein the second resistor is a plurality of resistors connected in series or a plurality of resistors having one end grounded, and the switching unit switches the plurality of resistors connected in series based on an ON signal or an OFF signal. Short-circuit or open some of the resistors of
7. The terminal load automatic setting device according to claim 6, wherein the switch is a switch for selecting one resistor by switching the other ends of the plurality of resistors. 8. The method according to claim 1, wherein the second resistor is an electronic variable resistor, and the switching means changes the electronic variable resistor to switch a resistance value based on an ON signal or an OFF signal. The automatic terminal load setting device according to claim 6. 9. The method according to claim 1, wherein the identification code sending means is surface-mounted on a circuit board, or mounted on a first individual circuit board mounted on a first connector disposed on the circuit board, and 2. The device according to claim 1, wherein the arrangement position identifying means and the terminal load setting means are mounted on a second individual circuit board mounted on a second connector arranged on the circuit board together with a circuit for supplying a high-frequency signal. The terminal load automatic setting device according to the above. 10. The identification code sending means, first and second identification code sending means.
The arrangement position identification means and the termination load setting means are mounted on one circuit board.
The terminal load automatic setting device according to the above.