JP3067276B2 - CCD solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD solid-state imaging device,
In particular the electric signal charge from the charge transfer unit composed of a CCD
Charge-to-electrical signal converter for converting into a gas signal, for example , a CCD having a so-called floating decision amplifier
The present invention relates to a solid-state imaging device.

[0002]

2. Description of the Related Art Conventional CCD solid-state imaging devices, particularly
The force part is, as shown in FIG.
In the next stage of the transfer unit 21, a floating gate is provided via an output gate OG.
Diffusion FD, reset gate PG and
And a discharge element 22 comprising a drain region D,
The output element Q is provided after the discharge element 22.₁And load resistance element Q
_TwoAnd a source follower circuit 23 comprising
ing.

In the charge transfer section 21, signal charges transferred from below the transfer electrode TG in the last stage are temporarily stored in the floating diffusion FD, and a voltage change ΔV based on the stored charge is transferred to a source follower circuit in a subsequent stage. 23, an output voltage (image signal) S is taken out from the output terminal φout of the source follower circuit 23.

The output terminal φou of the source follower circuit 23
After the imaging signal S is extracted from the reset gate P,
The floating diffusion FD is reset to the initial voltage Vdd is supplied to the reset pulse phi _PG in G, sweep out charges accumulated in the floating diffusion FD to the drain region D side.

[0005]

In the CCD solid-state image pickup device, the fixed potential Vog applied to the output gate OG is expanded in the degree of freedom in setting the fixed potential Vog. There is a demand for facilitating distribution to Vog.

When the fixed potential Vog has to be set irrespective of the potential under the output gate OG due to the circuit design, the impurity concentration under the output gate OG is changed at the stage of the manufacturing process. The potential under the output gate OG must be optimized. However, as described above, if there is a degree of freedom in setting the fixed potential Vog applied to the output gate OG, the impurity concentration under the output gate OG can be adjusted. Need not be changed, the impurity concentration can be set to be equal to the impurity concentration in the charge transfer section 21, and the manufacturing process can be simplified.

However, in the conventional CCD solid-state imaging device, as shown in FIG. 13A, there is a disadvantage that the set width m of the fixed potential Vog applied to the output gate OG is narrow. That is, when the set width m is viewed at the position of the potential OGp below the output gate, one of the driving pulses φ2 is at a high level, and the signal charge e is stored under the storage electrode TG. There is only a width from the potential position corresponding to the maximum handled charge amount of the TG to the potential position under the storage electrode TG when the drive pulse φ2 is at a low level and the potential under the storage electrode TG is low. , The degree of freedom in setting the fixed potential Vog is small.

That is, if the fixed potential Vog applied to the output gate OG is set too high, as shown in FIG. 13B, the driving pulse φ2 becomes high level, and the signal charge falls below the storage electrode TG of the last stage. When e is accumulated, since the potential barrier OGp below the output gate OG is low, a part ex of the signal charge e to be accumulated flows toward the floating diffusion FD in the reset state. Inconvenience that it occurs.

On the other hand, if the fixed potential Vog is set too low, then, as shown in FIG.
When transferring the signal charge e accumulated under the storage electrode TG in the final stage to the floating diffusion FD side, there is a disadvantage that the potential OGp under the output gate OG acts as a barrier and causes the transfer of the signal charge e to remain. Occurs.

Therefore, in the conventional CCD solid-state imaging device, when viewed from the height of the potential, the fixed potential Vog or the potential below the output gate OG is set so that the potential OGp below the output gate OG exists within a narrow range represented by the width m. Must be set. For this reason, in the conventional CCD solid-state imaging device, there is a disadvantage that the circuit design cannot be rationalized, the reference power source can be easily distributed to the fixed potential Vog, and the manufacturing process cannot be simplified.

In general, the charge-voltage conversion efficiency η in the floating diffusion FD is expressed by the following equation (1).

Η = ΔV / ΔQ = 1 / C _FD

Here, ΔV indicates a voltage change based on the signal charge amount ΔQ stored in the floating diffusion FD. Further, C _FD is the total capacity of the floating diffusion, and this total capacity C _FD is represented by the following equation. C _FD = C _B + C _OG + C _PG + C _L + C _M

Here, each capacitance is, as shown in FIG.
C _B is the capacitance between the floating diffusion FD and the substrate or adjacent channel, C _OG is the capacitance between the floating diffusion FD and the output gate OG, C _PG is the capacitance between the floating diffusion FD and the reset gate PG, and C _L is the wiring. capacitance, C _M is capacitance in the source follower circuit 23.

As can be seen from the above equation (1), the charge-voltage conversion efficiency η in the floating diffusion FD can be increased by reducing the total capacitance C _FD relating to the floating diffusion FD.

In order to realize this, conventionally, a method of reducing the area of the floating diffusion FD has been adopted. However, in the conventional CCD solid-state imaging device, the potential Vog applied to the output gate OG is fixed. , The floating diffusion F
Can not be lowered parasitic capacitance C _OG between D and the output gate OG, the charge - has become an obstacle to improvement of the voltage conversion efficiency eta.

The same applies to a CCD solid-state imaging device of a floating gate output type capable of nondestructively detecting signal charges.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to increase the degree of freedom in setting a fixed potential applied to an output gate. An object of the present invention is to provide a CCD solid-state imaging device capable of rationalizing circuit design of an element, facilitating distribution from a reference power supply to the fixed potential, and simplifying a manufacturing process.

Further, the present invention is the charge - the electrical signal converter can reduce the parasitic capacitance between the output gate, the charge - electric signal
It is possible to achieve an improvement in the charge-to-electric signal conversion efficiency in the conversion unit, an improvement in the sensitivity of the CCD solid-state imaging device, and an improvement in the S / S ratio.
The N ratio can be improved, and the degree of freedom in setting the fixed potential applied to the output gate can be increased, so that the circuit design of the CCD solid-state imaging device can be rationalized and the manufacturing process can be simplified. It is an object of the present invention to provide a CCD solid-state imaging device capable of performing the above-mentioned.

[0019]

According to the present invention, a signal charge from the last stage of a charge transfer section 2 constituted by a CCD is temporarily stored in a charge-to-electric signal conversion section FD via an output gate OG, and the storage is performed. A CCD solid-state imaging device having an output unit 1 configured to supply a change in an electric signal based on charges to an output amplifier 5 so as to extract the image signal S from an output terminal φout of the output amplifier 5 includes at least the charge transfer unit The charge storage capacity of the last stage is larger than the charge storage capacity of the other transfer stages.

Further, according to the present invention, in the CCD solid-state imaging device, the output from the output amplifier 5 is fed back to the output gate OG .

[0021]

According to the configuration of the present invention described above , at least the charge storage capacity of the last stage of the charge transfer section 2 is made larger than the charge storage capacity of the other transfer stages, so that the fixed potential Vog applied to the output gate OG is reduced. Even if it is set higher than in the conventional case, it is possible to maintain the maximum handled charge amount in the final stage. That is, when the signal charges are transferred to the final stage of the charge transfer unit 2, a phenomenon that a part of the signal charges overflows to the charge-electric signal conversion unit FD side is avoided. Therefore, the fixed potential Vog applied to the output gate OG can be set more flexibly, rationalizing the circuit design in the CCD solid-state imaging device, facilitating distribution from the reference power supply to the fixed potential, and simplifying the manufacturing process. be able to.

Further, according to the configuration of the present invention, the output (imaging signal S) from the output amplifier 5 is fed back to the output gate OG. The imaging signal S in the same phase as the signal change is supplied, and the charge-electric signal conversion unit F
D and the parasitic capacitance C _OG between the output gate OG is reduced.
Actually, assuming that the gain of the output amplifier 5 is G, (1-
G) It can be reduced about times.

As a result, the total capacitance C _FD of the charge-to-electrical signal converter FD can be reduced, and the charge
-Electric signal-electric signal conversion efficiency in the electric signal converter FD can be improved. This leads to an improvement in the sensitivity of the CCD solid-state imaging device and an improvement in the S / N ratio.

[0024]

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
Reference Examples and Examples will be described. FIG. 1 shows C according to the reference example .
FIG. 2 is an equivalent circuit diagram schematically showing a configuration of a CD solid-state imaging device, particularly, an output unit 1 thereof.

The output unit 1 of this CCD solid-state image pickup device
It has a so-called FDA (floating diffusion amplifier) 3 for converting a signal charge from the charge transfer section 2 constituted by a CD into an output voltage. That is, a discharge element 4 including a floating diffusion FD, a reset gate PG, and a drain region D is provided at the next stage of the charge transfer section 2 with an output gate OG interposed therebetween.
Next to the output element Q ₁ and the load resistance element Q ₂
And a source follower circuit 5 comprising: The output device Q ₁ and the load resistance element Q ₂ is constituted by, for example, N-channel type MOSFET (MOS field effect transistor).

The charge transfer section 2 is formed, for example, by a horizontal register 7 formed of an N-type impurity diffusion region band on the surface of a P-type silicon substrate 6 and an insulating film 8 on the horizontal register 7. It has a storage electrode 9 and a transfer electrode 10 of the first and second polycrystalline silicon layers, and these storage electrodes 9 and the transfer electrode 10 are arranged and formed in a set in a horizontal direction sequentially. It is configured. Then, the signal charges are sequentially transferred to the output unit 1 by alternately applying two-phase drive pulses φ1 and φ2 having opposite phases to each other.

In the charge transfer section 2, the signal charge transferred from the storage electrode 9e at the last stage is temporarily stored in the floating diffusion FD, and a voltage change ΔV based on the stored charge is transferred to the source follower circuit 5 at the subsequent stage. , Is taken out from the output terminal φout of the source follower circuit 5 as an output signal (imaging signal) S.

[0029] After removal of the output signal S from the output terminal φout, by supplying a reset pulse phi _PG to the reset gate PG, the floating diffusion FD is reset to the initial voltage Vdd, accumulated in the floating diffusion FD The discharged signal charges are swept out to the drain region D side. The two-phase drive pulse φ1
And φ2 as well as the output timing of the reset pulse phi _PG in FIG.

Therefore, the voltage change ΔV from the floating diffusion FD becomes a signal including a signal component based on the precharge drain voltage Vdd and the accumulated charge amount as shown in the waveform of FIG. The output signal S from the source follower circuit 5 is
Is a signal obtained by multiplying the voltage change ΔV from the floating diffusion FD by G, as shown in the waveform, and each signal (voltage change ΔV and output signal S) Is in phase.

At this time, in the output signal S from the source follower circuit 5, the potential corresponding to the precharge drain voltage Vdd in the voltage change ΔV from the floating diffusion FD is Vo, and the magnitude relation is Vo. Vdd from the relationship of the gain G of
<Vo.

In this embodiment , however, the charge storage capacity of the last storage electrode 9e is changed to the other storage electrodes 9e.
And the charge storage capacity of the transfer electrode 10.

Specifically, as shown in the example of FIG. 1, the length Le in the transfer direction of the last storage electrode 9e is longer than the lengths L ₁ and L ₂ of the other storage electrodes 9 and the transfer electrodes 10. By doing so, the charge storage capacitance in the last-stage storage electrode 9e is increased. In this case, as shown in FIG.
When the phase drive pulses φ1 and φ2 become low level and high level, respectively, and the signal charge e is transferred and stored in the potential well under the final-stage transfer electrode 9e, the charge storage capacity under the storage electrode 9e is reduced. Because it is getting bigger,
The accumulation height h of the signal charges e becomes shallower. Thus, the potential barrier OGp below the output gate OG can be made deeper.

This leads to the fact that the fixed potential Vog applied to the output gate OG can be set higher than in the conventional case, and the degree of freedom in setting the fixed potential Vog is improved. FIG.
, The width n is the set width of the fixed potential Vog as viewed from the height of the potential, and the conventional set width m (see FIG. 13).
(N> m).

In general, in a CCD solid-state image pickup device, when the degree of freedom in setting the fixed potential Vog applied to the output gate OG is expanded, it is easy to rationalize the circuit design and to distribute the reference potential from the reference power supply to the fixed potential Vog. Can be achieved.

In view of the circuit design, the fixed potential Vog
Must be set irrespective of the potential under the output gate OG, then, in the stage of the manufacturing process, the impurity concentration under the output gate OG is changed to optimize the potential under the output gate OG. However, as described above, the output gate OG
If the setting width n of the fixed potential Vog applied to the gate electrode has a degree of freedom, the impurity concentration under the output gate OG does not need to be changed, and can be set to be equal to the impurity concentration in the charge transfer section 2, thereby simplifying the manufacturing process. Can be achieved.

From the above, according to the above reference example , the charge storage capacity below the storage electrode 9e in the last stage of the charge transfer section 2 is made larger than the charge storage capacity of the other transfer stages, so that the output gate OG is connected to the output gate OG. Regarding such a fixed potential Vog,
Since the degree of freedom of the setting is widened, it is possible to rationalize the circuit design in the CCD solid-state imaging device, facilitate the distribution from the reference power supply to the fixed potential Vog, and simplify the manufacturing process.

Next, a CCD solid-state imaging device according to an embodiment in which the degree of freedom in setting the charge-voltage conversion efficiency η in the floating diffusion FD and the fixed potential Vog applied to the output gate OG is expanded. This will be described with reference to FIGS. The components corresponding to those in FIG. 1 are denoted by the same reference numerals.

This CCD solid-state image pickup device has substantially the same configuration as that of the above-described reference example , but connects the output side of the source follower circuit 5 and the output gate OG to output signals (image pickup) output from the source follower circuit 5. It differs by feeding back the signal) S to the output gate OG. In this case, since a signal having the same phase as the voltage change ΔV in the floating diffusion FD is supplied to the output gate OG, the parasitic capacitance COG between the floating diffusion FD and the output gate _OG is reduced. In reality, when the gain of the source follower circuit 5 is G, the parasitic capacitance _COG can be reduced by (1-G) times.

Therefore, according to this embodiment , the output (imaging signal S) from the source follower circuit 5 is output to the output gate OG.
The parasitic capacitance C _OG between the floating diffusion FD and the output gate OG can be reduced. As a result, the total capacitance C _FD of the floating diffusion FD can be reduced. Can be realized. Accordingly, the charge-voltage conversion efficiency η in the floating diffusion FD can be improved, and the sensitivity of the CCD solid-state imaging device and the S / N ratio can be improved.

In this embodiment , the output (image signal S) of the source follower circuit 5 is applied to the output gate OG.
Is supplied to the output gate OG, for example, at t _{1 in} FIGS. 2 and 3.
Is applied. In this case, the potential barrier OGp below the output gate OG becomes low. In time this t _1, since the signal charges are accumulated under the storage electrode 9e of the final stage, usually, as shown in FIG. 13B, a phenomenon that part of the signal charge overflowing to the floating diffusion FD side Occurs.

[0042] In order to solve this problem by changing the bias potential Vgg applied to the gate of the load resistance element Q ₂ of the source follower circuit 5 to adjust the bias voltage Vo of the output signal S from the source follower circuit 5, At time t ₁ , a method of preventing the signal charge under the storage electrode 9 e in the final stage from overflowing to the floating diffusion FD side can be considered. However, at the time t ₂ , the signal charge is transferred to the floating diffusion FD. Since a relatively low potential component corresponding to the signal component of the imaging signal S is applied to the output gate OG at the time of reading the signal charge, as shown in FIG. 13C, the potential under the storage electrode 9e in the final stage is reduced. The potential under the output gate OG becomes lower than that of the output gate OG, so that the transfer of signal charges remains. .

[0043] Therefore, in this embodiment, the above-mentioned Reference
As in the example , the length Le in the transfer direction of the storage electrode 9e in the final stage is set to the length L _{1 of the} other storage electrode 9 and the transfer electrode 10.
And by longer than L _2, the last stage storage electrode 9
The charge storage capacity at e is increased. As a result, t ₁
When the signal charge is transferred below the storage electrode 9e at the last stage, the signal charge is transferred to the floating diffusion F
The phenomenon of overflow on the D side can be avoided. Further, since necessary to change the bias potential Vgg applied to the gate of the load resistance element Q ₂ is not, forwarding the remaining signal charges as shown in FIG. 13C does not occur.

[0044] Therefore, according to this embodiment, it is possible to reduce the parasitic capacitance C _OG between the output gate OG and the floating diffusion FD, and the charge in the floating diffusion FD - with the increase of the voltage conversion efficiency η can be achieved, CCD Improvement of sensitivity of solid-state imaging device and S /
The N ratio can be improved. Moreover, the output gate OG
Since the degree of freedom in setting the potential applied to the CCD solid-state imaging device can be increased, the circuit design in the CCD solid-state imaging device can be rationalized and the manufacturing process can be simplified.

In the above reference example and embodiment , the charge storage capacity of the last-stage storage electrode 9e of the charge transfer section 2 is made larger than the charge storage capacity of the other transfer stages. Although the example in which the length Le in the transfer direction is increased has been described, the following configuration may be employed.

That is, as shown in FIG. 6, the channel width De below the storage electrode 9e in the final stage is made wider than the channel width D in the other transfer stages.

Alternatively, as shown in FIG. 7, the thickness te of the gate insulating film 8 below the storage electrode 9e in the final stage is made smaller than the thickness t of the gate insulating film 8 in the other transfer stages. Here, the charge storage capacity below the storage electrode 9e in the final stage generally indicates, as shown in the energy band diagram of FIG.
The combined capacitance formed by connecting the gate insulating film capacitance Co, the capacitance C _OB between the interface a between the gate insulating film 8 and the silicon substrate and the bulk channel, and the capacitance C _BS between the bulk channel BC and GND in series, respectively. It is.

As described above, reducing the thickness te of the gate insulating film 8 under the storage electrode 9e in the final stage leads to increasing the gate insulating film capacitance Co in FIG. As a result, the final stage storage electrode 9
e, the charge storage capacity can be increased.

As another configuration, as shown in FIG. 9, the depth he of the N-type impurity diffusion region 7e below the storage electrode 9e in the final stage is changed to the impurity diffusion region 7 in another transfer stage.
Shallower than the depth hn. That is, as shown in FIG. 10, the impurity concentration distribution (shown by a curve) under the storage electrode 9e in the final stage is made shallower than the impurity concentration distribution (shown by a curve) in the other transfer stages.

In this case, as shown in FIG. 11, the position of the bulk channel BC under the final storage electrode 9e (see FIG. 11B) is the position of the bulk channel BC in the storage electrode 9 of the other transfer stage (see FIG. 11B). 11A), the capacitance C _OB between the interface a and the bulk channel BC increases. As a result, the charge storage capacitance under the storage electrode 9e in the final stage increases. To increase.

Therefore, by appropriately selecting or combining these configurations, the storage electrode 9 in the final stage can be obtained.
e can easily increase the charge storage capacity.

In the above-described reference example and the embodiment, the example in which the charge storage capacity in the last-stage storage electrode is increased has been described.
In addition, the charge storage capacity of the storage electrode in another transfer stage including the last-stage storage electrode may be increased. Also,
Although the floating diffusion FD is used to convert the signal charge from the charge transfer unit 2 into a voltage in the above-described reference example and the embodiment , other than the floating diffusion FD, the CCD solid-state imaging device of the floating gate output type is used. The present invention is also applicable to devices.

[0053]

According to the CCD solid-state imaging device of the present invention, the degree of freedom in setting the fixed potential applied to the output gate can be increased, the circuit design in the CCD solid-state imaging device can be rationalized, and the reference power supply can be improved. , And the manufacturing process can be simplified.

[0054] Moreover, according to the CCD solid-state imaging device according to the present invention, the charge - the electrical signal converter can reduce the parasitic capacitance between the output gate, the charge - charge in the electric signal conversion unit - improvement of the electric signal conversion efficiency And CCD
It is possible to improve the sensitivity of the solid-state imaging device and the S / N ratio .

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram illustrating a configuration of an output unit of a CCD solid-state imaging device according to a reference example .

FIG. 2 is a waveform diagram showing output timings of a two-phase drive pulse and a reset pulse.

FIG. 3 is a waveform chart showing a relationship between a voltage change from a floating diffusion and an output signal from a source follower circuit.

FIG. 4 is a potential diagram illustrating a charge transfer operation of an output unit according to a reference example .

Figure 5 is an equivalent circuit diagram of an output portion of the CCD solid-state imaging device according to the embodiment.

FIG. 6 is a plan view of a main part showing an example of a configuration (channel width) for increasing the charge storage capacity of a storage electrode in a final stage.

FIG. 7 is a cross-sectional view of a main part showing another example (gate insulating film) of increasing the charge storage capacity of the storage electrode in the final stage.

FIG. 8 is an energy band diagram of a storage electrode at the last stage.

FIG. 9 is a cross-sectional view of a main part showing another example (impurity diffusion region) of increasing the charge storage capacity of the storage electrode in the last stage.

FIG. 10 is a characteristic diagram showing an impurity concentration distribution under a storage electrode in a final stage.

FIG. 11 is an energy band diagram under each storage electrode of another transfer stage and a final stage.

FIG. 12 is an equivalent circuit diagram showing a configuration of an output unit of a CCD solid-state imaging device according to a conventional example.

FIG. 13 is a potential diagram showing a set width of a fixed potential Vog in a conventional example.

FIG. 14 is an equivalent circuit diagram showing the total capacitance relating to floating diffusion.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Output part 2 Charge transfer part 3 FDA 4 Discharge element 5 Source follower circuit 6 Silicon substrate 7 Horizontal register 8 Gate insulating film 9 Storage electrode 9 e Last stage storage electrode 10 Transfer electrode OG Output gate FD Floating diffusion PG Reset gate D Drain region Q ₁ output element Q ₂ load resistance element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/762 H01L 21/339 H01L 27/148 H04N 5/335

Claims (1)

(57) [Claims] 1. A signal charge from a final stage of a charge transfer section constituted by a CCD is temporarily stored in a charge-electric signal conversion section via an output gate, and a change in an electric signal based on the stored charge is output to an output amplifier. The output from the output amplifier is fed back to the output gate in the CCD solid-state imaging device having an output unit configured to take out the image as an image signal from the output terminal of the output amplifier. Wherein the charge storage capacity of the last stage is larger than the charge storage capacity of the other transfer stages.