JP3064991B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device for the purpose of increasing the breakdown voltage by ion implantation at a high acceleration voltage and forming a self-aligned low concentration diffusion layer.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device of this kind for increasing the withstand voltage has been aimed at increasing the withstand voltage of a drain diffusion layer to which a high electric field is applied. A low-concentration diffusion layer having a deep junction is formed before forming the gate electrode.

FIG. 3 is a sectional view showing an example of a conventional method of manufacturing a semiconductor device for the purpose of increasing the breakdown voltage. In FIG. 3, an N-channel MOS (Metal Oxide S)
A description will be given by taking a C.I.C.

First, in FIG. 3A, a LOCOS (LOCal Oxidation) is formed on a P-type silicon substrate 1.
The field oxide film 2 is formed by selectively growing the oxide film by the method of (Silicon).

In order to form a low-concentration diffusion layer having a deep junction in a self-aligned manner with respect to a gate electrode, it is necessary to form a gate electrode and then perform ion implantation at a high acceleration voltage using the gate electrode as a mask. is there. However, in the prior art, since the ionic species penetrate through the gate electrode, a deep junction low concentration diffusion layer is formed before the gate electrode is formed.

Therefore, after the resist 11 is patterned by photolithography, phosphorus, which is an N-type impurity, is ion-implanted at a high accelerating voltage to form a deep junction N
^- -type diffusion layer 7.

Next, in FIG. 3B, boron, which is a P-type impurity, is selectively ion-implanted at a high accelerating voltage by photolithography to form a P-type channel stopper layer 3. Next, a gate oxide film 4 is grown by a thermal oxidation method, and a CVD (Chemical) is formed thereon.
The polysilicon is deposited by a Vapor Deposition method. Next, after the resist 5 is patterned by photolithography, the gate electrode 6 is formed in a desired shape by dry etching. Next, the resist 5 is removed.

Next, in FIG. 3C, after depositing an oxide film by the CVD method, the oxide film is left only on the side wall of the gate electrode 6 by the dry etching method to form a sidewall spacer 8. Then, arsenic, which is an N-type impurity, is selectively ion-implanted by photolithography to form an N ⁺ -type diffusion layer 9.
Double diffusion layer 10 which is a substantial source / drain diffusion layer
Is formed.

[0009]

However, in the conventional example, there is a problem that the diffusion resistance of the double diffusion layer greatly varies, which is disadvantageous for the design of the integrated circuit.

The reason is that the low-concentration diffusion layer is formed before forming the gate electrode and is not formed in a self-alignment manner, and the high-concentration diffusion layer is formed in a self-alignment manner with the side wall spacer after the formation of the gate electrode. This is because the gap between the low concentration diffusion layer and the high concentration diffusion layer varies.

Further, there is a problem that capacitance variation between the gate electrode and the low concentration diffusion layer is large, which is disadvantageous for designing an integrated circuit.

The reason is that since the low concentration diffusion layer is formed before the formation of the gate electrode, the overlap region of the gate electrode and the low concentration diffusion layer varies due to misalignment during the formation of the gate electrode.

Further, extra ions are implanted into the channel stopper layer, so that the channel stopper layer is easily inverted. As a result, there is a problem that the characteristics of the semiconductor device fluctuate.

The reason is that there is no film for preventing penetration of ionic species on the field oxide film immediately above the channel stopper layer, so that ion species penetrate the field oxide film when ions are implanted at a high acceleration voltage.

FIG. 4 shows a manufacturing method disclosed in Japanese Patent Application Laid-Open No. 3-2151971. FIG. 4 is a cross-sectional view of a manufacturing method disclosed in Japanese Patent Application Laid-Open No. Hei 3-215771 for the sake of explanation, in which a channel stopper layer 3 is added and N
Only a channel type MOS transistor is illustrated as a cross-sectional view. The manufacturing method shown here is
The resist 5 is left on the gate electrode 6 (see FIG. 4).
(A)), LDD (Lightly Doped Dr)
a) A region 12 is formed in a self-aligned manner with respect to the gate electrode 6 (FIG. 4B). LDD region 12
Is a low concentration diffusion layer having a shallow junction, and is formed by ion implantation at a low acceleration voltage.

However, since a low-concentration diffusion layer having a deep junction is formed in a self-aligned manner with respect to the gate electrode 6, when ions are implanted at a high acceleration voltage, the ion species do not penetrate through the gate electrode 6 where the resist 5 remains. But resist 6
The ion species penetrate through the field oxide film 2 immediately above the channel stopper layer 3 where no is left. Therefore,
In the manufacturing method disclosed in Japanese Patent Application Laid-Open No. 3-2151971, there remains a problem in forming a low-concentration diffusion layer having a deep junction.

An object of the present invention is to reduce the variation in the diffusion resistance of the double diffusion layer and the variation in the capacitance between the gate electrode and the low-concentration diffusion layer. It is an object of the present invention to provide a method of manufacturing a semiconductor device intended for a matching type.

[0018]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a double diffusion layer.
The deep diffusion layer that constitutes
Gate electrode with sidewalls
A method for manufacturing a semiconductor device formed by ion implantation using a mask as a mask, wherein a gate electrode is formed when a deep diffusion layer is formed.
Ion implantation with resist remaining on top
It is .

Further, in the method for manufacturing a semiconductor device according to the present invention, the deep diffusion layer constituting the double diffusion layer masks the gate electrode.
The shallow diffusion layer has sidewalls.
A method of manufacturing a semiconductor device formed by ion implantation using a gate electrode as a mask, the method being used for forming a deep diffusion layer.
With the resist and insulating film left on the gate electrode
The ion implantation is performed in a state .

According to the present invention, ions are implanted at a high accelerating voltage while the resist is left after the gate electrode is formed. Therefore, a low-concentration diffusion layer having a deep junction can be formed in a self-aligned manner with the gate electrode, and variations in diffusion resistance of the double diffusion layer and variations in capacitance between the gate electrode and the low-concentration diffusion layer can be reduced. Can be realized.

According to the present invention, the gate electrode and the resist are ion-implanted on the field oxide film immediately above the channel stopper layer while leaving the gate electrode and the resist. This prevents ion species from penetrating the field oxide film and being implanted into the channel stopper layer even when ion implantation is performed at a high acceleration voltage.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention in the order of steps. FIG. 1 illustrates an N-channel MOS transistor as an example.

First, referring to FIG. 1A, an oxide film is selectively grown on a P-type silicon substrate 1 to form a field oxide film 2 of several thousand Å. Next, P-type impurities are selectively ion-implanted by photolithography at an acceleration voltage of several hundred KeV to form a P-type channel stopper layer 3. Then, several hundreds of gate oxide film 4 is grown, and several thousand of polysilicon is deposited thereon. Then several μ
m of resist 5 is applied and dried, and the resist 5 is formed into a pattern so that the gate electrode and the resist 5 are left on the conventional pattern for forming the gate electrode and the field oxide film 2 immediately above the channel stopper layer 3. Thereafter, the gate electrode 6 is formed by a dry etching method.

Next, in FIG. 1B, while the resist 5 is left on the gate electrode 6, using the gate electrode 6 and the resist 5 as a mask, an N-type impurity is ion-implanted at an acceleration voltage of several hundred KeV to form a junction. An N ⁻ -type diffusion layer 7 having a depth of several μm is formed in self-alignment with the gate electrode 6. Next, the resist 5 is removed.

Next, in FIG. 1C, after depositing an oxide film on the entire surface, the oxide film is left only on the side wall of the gate electrode 6 by dry etching to form a sidewall spacer 8. Next, N-type impurities are selectively ion-implanted by a photolithography technique to form N ⁺
By forming the mold diffusion layer 9, a double diffusion layer 10, which is a substantial source / drain diffusion layer, is formed.

(Example 1) A specific example according to Embodiment 1 of the present invention shown in FIG.

First, as shown in FIG. 1A, an oxide film is selectively grown on a P-type silicon substrate 1 by a LOCOS method to form a field oxide film 2 of about 5000 °. Next, boron, which is a P-type impurity, is selectively ion-implanted by photolithography under the conditions of an acceleration voltage of 800 KeV and a toe amount of 1.0 × 10 ¹³ cm ⁻² , and the P-type channel stopper layer 3 is placed immediately below the field oxide film. Formed. Next, a gate oxide film 4 of about 400 ° is grown by thermal oxidation, and polysilicon of about 1500 ° is deposited thereon by CVD. Next, phosphoryl chloride (POCl ₃ ) is vapor-phase diffused to convert the polysilicon into an N-type conductor.

Next, a resist 5 of about 1 μm is applied to the entire surface and dried. Next, the resist 5 is applied to the conventional gate electrode pattern and the field oxide film 2 immediately above the channel stopper layer.
Is formed by a photolithography technique in a pattern in which the pattern is left. Next, the gate electrode 6 is formed by etching the polysilicon by a dry etching method.

Then, as shown in FIG. 1B, while the resist 5 is left on the gate electrode 6, the gate electrode 6 and the resist 5 are used as masks to accelerate phosphorus as an N-type impurity at an acceleration voltage of 700 KeV and a dose amount. 1.5 × 10 ¹³ cm ^-2
Is implanted under the conditions described above to form an N ⁻ type diffusion layer 7 having a junction depth of about 1.5 μm in a self-aligned manner with respect to the gate electrode 6.
Further, phosphorus, which is an N-type impurity, is not implanted into the channel stopper layer 3 due to the gate electrode 6 and the resist 5 left on the field oxide film 2 immediately above the channel stopper layer 3.

Next, as shown in FIG. 1C, the resist 5 is stripped with an organic solvent. The gate electrode 6 on the field oxide film 2 immediately above the channel stopper layer 3 is left in order not to increase the number of manufacturing steps. Since the remaining gate electrode 6 is on the field oxide film 2 immediately above the channel stopper layer 3, the channel stopper layer 3 is not inverted to N-type and does not affect the characteristics of the semiconductor device.

Then, about 2000 ° C.
After depositing the VD oxide film on the entire surface, the oxide film is left only on the side wall of the gate electrode 6 by dry etching to form a sidewall spacer 8. Then
Using the resist selectively patterned by photolithography and the sidewall spacers 8 as a mask, arsenic, which is an N-type impurity, is self-aligned with an accelerating voltage 7.
By implanting ions under the conditions of 0 KeV and a dose of 3.0 × 10 ¹⁵ cm ⁻² to form the N ⁺ diffusion layer 9, the double diffusion layer 10, which is a substantial source / drain diffusion layer, is self-aligned. It is formed.

(Embodiment 2) FIG. 2 is a sectional view showing a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.

In the first embodiment shown in FIG. 1, the low concentration diffusion layer is formed by ion implantation at an acceleration voltage of several hundreds KeV. In the second embodiment shown in FIG. 2, a deep junction low concentration diffusion layer is formed. In order to reliably prevent penetration of ion species even when ions are implanted at a high acceleration voltage, an insulating film 21 is formed between the polysilicon and the resist 5.
It is a manufacturing method that sandwiches.

In FIG. 2A, after forming the P-type channel stopper layer 3, a gate oxide film 4 of several hundreds of .ANG. Is grown, and a polysilicon of several thousand .ANG. Is deposited thereon. Next, an insulating film 21, for example, an oxide film, having a thickness of several thousand degrees is deposited on the polysilicon. Next, a resist 5 having a thickness of several μm is applied and dried. The resist 5 is formed into a pattern for forming a conventional gate electrode and a pattern for leaving the gate electrode, the insulating film 21 and the resist 5 on the field oxide film 2 immediately above the channel stopper layer 3. After that, the gate electrode 6 is formed by a dry etching method.

Next, in FIG. 2B, while the resist 5 and the insulating film 21 are left on the gate electrode 6, thousands of N-type impurities are formed using the gate electrode 6, the insulating film 21 and the resist 5 as a mask. Ion implantation is performed at an acceleration voltage of KeV to form an N ⁻ -type diffusion layer 7 having a junction depth of several μm in a self-aligned manner with respect to the gate electrode 6. Next, the resist 5 is removed, and the insulating film 21 on the gate electrode 6 is left.

Next, in FIG. 2C, a double diffusion layer 10 is formed by the same manufacturing method as in the first embodiment.

(Example 2) A specific example according to Embodiment 2 of the present invention shown in FIG.

First, as shown in FIG. 2A, a field oxide film 2 of about 5000 ° is formed on a P-type silicon substrate 1 by the same manufacturing method as in the first embodiment, and the P-type channel stopper layer 3 is formed by field oxidation. A gate oxide film 4 having a thickness of about 400 ° is grown immediately below the film, and polysilicon having a thickness of about 1500 ° is deposited thereon. Next, the polysilicon is converted into an N-type conductor.

Next, an oxide film 21 which is one of the insulating films is deposited on the entire surface by the CVD method at about 5000.degree. Next, a resist 5 of about 1 μm is applied to the entire surface and dried. Next, the resist 5 is formed by a photolithography technique into a pattern for forming a conventional gate electrode and a pattern for leaving the gate electrode, the oxide film 21 and the resist 5 on the field oxide film 2 immediately above the channel stopper layer. Next, the gate electrode 6 is formed by etching the oxide film 21 and the polysilicon by a dry etching method.

Then, as shown in FIG. 2B, while the resist 5 and the oxide film 21 are left on the gate electrode 6, the gate electrode 6, the oxide film 21 and the resist 5 are used as a mask to form an N-type impurity. Is accelerated to 2 Me
V, ions were implanted under the conditions of a dose of 1.5 × 10 ¹³ cm ⁻² and an N ⁻ -type diffusion layer 7 having a junction depth of about 4 μm was formed on the gate electrode 6.
Are formed in a self-aligned manner.

Next, as shown in FIG. 2C, the resist 5 is stripped with an organic solvent. Oxide film 2 on gate electrode 6
1 is left in order not to increase the number of manufacturing steps.
Since oxide film 21 is an insulating film, there is no problem even if oxide film 21 is left on gate electrode 6. For the same reason as in the first embodiment, the gate electrode 6 and the oxide film 21 on the field oxide film 2 immediately above the channel stopper layer 3 are left.

Next, in the same manner as in the first embodiment, about 2000 mm
After depositing a CVD oxide film on the entire surface, a sidewall spacer 8 is formed, and an N ⁺ diffusion layer 9 is formed by ion-implanting arsenic, which is an N-type impurity, in a self-aligned manner.
The double diffusion layer 10 is formed in a self-aligned manner.

[0044]

As described above, according to the present invention, the formation of the low-concentration diffusion layer and the formation of the gate electrode by 0.3 .mu.m.
The misalignment of about m is eliminated, and the variation of the diffusion resistance of the double diffusion layer and the variation of the capacitance between the gate electrode and the low concentration diffusion layer can be suppressed.

The reason is that the low concentration diffusion layer is formed in a self-aligned manner after the formation of the gate electrode.

Furthermore, despite the formation of the gate electrode, a deep junction low concentration diffusion layer can be formed, and as a result, a high breakdown voltage can be realized.

The reason is that ions are implanted at a high accelerating voltage while a film for preventing penetration of ion species is left on the gate electrode.

Further, even if ion implantation is performed at a high acceleration voltage, unnecessary ion implantation into the channel stopper layer can be prevented without increasing the number of manufacturing steps.

The reason is that ions are implanted at a high accelerating voltage while the film for preventing penetration of ion species is left on the field oxide film immediately above the channel stopper layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view showing Embodiment 2 of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device for achieving a high breakdown voltage in the order of steps.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a conventional self-aligned semiconductor device in the order of steps.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate 2 Field oxide film 3 Channel stopper layer 4 Gate oxide film 5 Resist 6 Gate electrode 7 N ^- type diffusion layer 8 Side wall spacer 9 N ⁺ diffusion layer 10 Double diffusion layer 11 Resist 12 N ^- type LDD region 21 Insulating film

Claims (2)

(57) [Claims] A deep diffusion layer constituting a double diffusion layer is formed by a gate.
Shallow diffusion layer formed by ion implantation using
Is an ion implantation using the gate electrode with the sidewall as a mask.
A method of manufacturing a semiconductor device, comprising forming a resist on a gate electrode when forming a deep diffusion layer.
A method of manufacturing a semiconductor device, comprising performing ion implantation in a state where the semiconductor device is left . 2. A deep diffusion layer constituting a double diffusion layer is a gate diffusion layer.
Shallow diffusion layer formed by ion implantation using
Is an ion implantation using the gate electrode with the sidewall as a mask.
A method of manufacturing a semiconductor device, wherein a resist and a resist are formed on a gate electrode when forming a deep diffusion layer.
A method of manufacturing a semiconductor device, wherein ion implantation is performed with the insulating film and the insulating film left .