JP3062900B2 - Inverter control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter control device used for driving a motor, and more particularly, to an induction motor having a high PW.
Suitable for driving at M frequency.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional inverter control device. A current control circuit 17 includes current commands iu ^* , iv ^* , iw ^* from a higher-level control circuit and current detectors 14 and 14. 15 to determine the current deviation of each phase of the motor based on the phase currents iu and iv of the motor 16 detected by
The voltage commands vu ^* , vv ^* , vw ^* to be applied to each phase of the motor are created by proportionally and integrally amplifying this, and PW
The signal is sent to the M signal generation circuit 18. Voltage commands vu ^* , vv
^* , Vw ^* are PWM signals S having an on / off duty proportional to the command value by the PWM signal generation circuit 18.
It is converted into IGU, SIGV, and SIGW, and sent to the dead time generation circuit b20.

The dead time generating circuit b20 converts the PWM signals SIGU, SIGV, and SIGW into on / off signals for the power elements 2 to 7 of the inverter by using a method described later.
The signals are converted into f command signals G1 to G6 and input to the gate circuits 8 to 13 of the power elements 2 to 7, respectively. The gate circuits 8 to 13 are connected to the respective power elements 2 according to the on / off command signals G1 to G6.
7 are turned on / off, the DC voltage rectified by the converter 1 is converted into voltage commands vu ^* , vv ^* ,
It is applied to each phase of the motor 16 with a duty proportional to vw ^* . In this way, the phase current of each phase of the motor is controlled to match the current command.

[0004] An operation example of the dead time generation circuit will be described below. FIG. 4 shows the dead time generation circuit b2 of FIG.
FIG. 7 is a block diagram showing only a portion related to the U phase in the configuration of 0, and similar blocks are included for the V phase. Here, since the blocks of each phase are targets, only the U phase will be described. PWM signal SI as shown in FIG.
The change in GU is detected by the edge detection circuit 21,
The trigger signal TRU of the one-shot circuit 25 as shown in FIG. The one-shot circuit 25 receives the trigger signal T
FIG. 6 shows the time width td for each rising edge of the RU.
The logic circuit b generates the pulse signal DTU as shown in FIG.
26. The logic circuit b26 outputs the pulse signal DTU
And PWM signal SIGU, gate signals G1 and G2 having dead time width td as shown in FIGS. 6 (d) and 6 (e) are generated using the logical expressions of equations (1) and (2).

(Equation 1)

(Equation 2)

[0005]

FIGS. 5A to 5F show signal waveforms at various parts of the conventional inverter control device.
(A) is a PWM signal generation circuit 1 using a triangular wave comparison method
8 is a diagram showing the relationship between the triangular wave VT and the command voltage Vu ^* in FIG. 8, and comparing the two signals to obtain the PWM signal SIGU of FIG. The off width of the signal at this time is T ^* . On the other hand, the gate signals G1 and G2 have the waveforms of (c) and (d) with a dead time td added to prevent the upper and lower power elements from being simultaneously turned on, and the actual U-phase applied voltage is (e). , (F) (depending on the polarity of the U-phase current). Here, the time width T during which the U-phase voltage is on the lower side
_{The n +} and _Tn- are as shown in the following equations (3) and (4), where the on time and the off time of the power element are ton and toff, respectively.

## EQU3 ## T _{n +} = T ^* + td + (ton-toff)

## EQU4 ## T _n− = T ^* −td + (ton-toff)

Therefore, before and after the polarity of the current changes, the applied voltage of the U-phase changes by 2 · td, and the U-phase current waveform is distorted near 0 due to this effect.
As described above, in the conventional inverter control device, the actual applied voltage differs from the command due to the dead time, and the current waveform is 0.
There was a problem of distortion near. The present invention has been made in view of the above problems, and an object of the present invention is to provide an inverter control device capable of preventing current distortion due to dead time without performing calculations in a CPU. .

[0007]

SUMMARY OF THE INVENTION The present invention relates to a PWM signal generating circuit for generating a PWM signal having a duty ratio proportional to an output voltage command of an inverter, and an inverter arm provided with a dead time for preventing a short circuit for the PWM signal. A dead time generation circuit for turning on and off command signals to the upper and lower power elements of the inverter control device for controlling the phase current of the motor, the above object of the present invention, the dead time generation circuit, This is achieved by providing switching means for switching the dead time and the timing to be added to the respective on / off command signals to the upper and lower power elements in accordance with the polarity of the current command from the upper control circuit.

[0008]

In the inverter control device according to the present invention, the control is performed so that the actually applied voltage matches the command voltage regardless of the polarity of the current, so that the current waveform can be prevented from being distorted near zero. . Therefore, torque ripple does not occur in the driven motor.

[0009]

FIG. 1 is a block diagram showing an example of an inverter control device according to the present invention in correspondence with FIG. 3, and portions having the same functions are denoted by the same reference numerals and description thereof will be omitted. In this embodiment, current command polarity signals pu, pv, pw sent from the current control circuit 17 to the dead time generation circuit a19 are added to the conventional inverter control device. The internal block of the dead time generation circuit a19 has two sets of one shot circuits (one shot circuit A22 and one shot circuit B2) as shown in an example of the dead time generation circuit in FIG.
As the number increases to 3), the logical expression of the logical circuit a24 is different from the conventional one.

An example of the operation of the dead time generating circuit will be described below with reference to FIGS. A change in the PWM signal SIGU as shown in FIG. 6A is detected by the edge detection circuit 21, and a one-shot circuit A as shown in FIG.
22 and B23. The one-shot circuit A22 and the one-shot circuit B23 generate pulse signals DTAU and DTBU as shown in FIGS. And the logic circuit a2
4 The ethics circuit a24 outputs the pulse signal DTA
From the U, DTBU, PWM signal SIGU and the current command polarity pu as shown in FIG. 6H, the gates as shown in FIGS. Signal G
1, G2. Here, the conventional gate signal G1,
G2 (FIGS. 5 (c) and 5 (d)), the phase current iu>
When it is 0, the gate signals G1 and G2 are as shown in FIGS.
, And when the phase current iu <0, FIG.
(J) and (k).

[0011]

(Equation 5)

(Equation 6) Thereby, the U-phase voltage actually applied becomes (i) of FIG.
And (l), the time width T _{c +} of the primary voltage when the current is “+” and the time width T _c− of the primary voltage when the current is “−” are as follows: Expressions 7 and 8 show.

## EQU7 ## T _{c +} = T ^* + td + (ton-toff)

Equation 8] ^{_{T c- = T * + td +}} (ton-toff) = T c + that is, the same time width regardless of the polarity of the current.

[0012]

According to the inverter control device of the present invention,
Since the output voltage of each phase of the inverter matches the width of the PWM signal regardless of the polarity of the phase current, a good output current waveform with little distortion can be obtained. In addition, since there is a merit that the calculation accompanying the correction is unnecessary, the present invention can be applied to a control device that performs a current control at a high speed by an analog circuit. Furthermore, in contrast to the conventionally considered dead time correction method using the instantaneous vector selection method, there is an advantage that an operation associated with the correction is not required, and a PWM signal is generated between the PWM signal generation circuit and the dead time generation circuit. Since the connection can be made only with the current polarity signal, even if the inverter bridge and the control circuit are far apart, mounting the dead time generation circuit on the inverter bridge side will affect the noise on the gate signal and the delay time between signal lines. Can be prevented from being short-circuited due to variations in the arm length.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an inverter control device according to the present invention.

FIG. 2 is a block diagram illustrating an example of a dead time generation circuit of FIG. 1;

FIG. 3 is a block diagram illustrating an example of a conventional inverter control device.

FIG. 4 is a block diagram illustrating an example of a dead time generation circuit of FIG. 3;

FIG. 5 is a diagram showing an example of a signal waveform of each unit of the device of the present invention and the conventional device.

FIG. 6 is a diagram illustrating an example of a signal waveform of each part of the dead time generation circuit of FIGS. 2 and 4;

[Explanation of symbols]

 19 Dead time generation circuit 22, 23 One shot circuit 24 Logic circuit

Claims (1)

(57) [Claims] 1. A PWM signal generating circuit for generating a PWM signal having a duty ratio proportional to an output voltage command of an inverter, and a dead time for preventing a short circuit for the PWM signal to turn on and off power elements above and below an inverter arm. A dead time generating circuit as a command signal, the inverter control device controlling the phase current of the motor, the dead time generating circuit, dead time time added to the on and off command signal to each of the upper and lower power elements, and An inverter control device comprising switching means for switching timing according to the polarity of a current command from a higher-level control circuit.