JP3062043B2 - Nonvolatile memory and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a nonvolatile memory having a floating gate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Among nonvolatile memory devices, FIG. 5A is a plan view of a memory cell of a flash memory capable of electrically performing a writing / erasing operation and performing a batch erasing operation, and FIG. Referring to b), the conventional cell structure is as follows.

A 1-bit memory cell comprises one EEPROM (electrically erasable programmable read only memory) provided on the surface of a P-type silicon substrate 101. This EEPROM has a channel region sandwiched between an N-type source region 108 and an N-type drain region 107, a tunnel oxide film 103, and a floating gate electrode 10.
4, inter-electrode insulating film 105 and control gate electrode 10
6 is comprised. The tunnel oxide film 103, the floating gate electrode 104, the inter-electrode insulating film 105, and the control gate electrode 106 are stacked on the channel region. The N-type source region 108 and the N-type drain region 107 are provided in the element formation region on the surface of the P-type silicon substrate 101 in a self-aligned manner with the control gate electrode 106, respectively. This element formation region
5A is a lattice-shaped region provided at a required interval in the vertical direction and the horizontal direction (two orthogonal directions), and the element isolation region surrounded by the element formation region includes: A field oxide film 102 is provided. The control gate electrode 106 serves as a word line, and the N-type source regions 108 of the memory cells belonging to the same word line are common. Two adjacent N-type source regions 108
Two control gate electrodes 106 are provided between the two, and two horizontally adjacent memory cells provided between these two control gate electrodes 106 share one N-type drain region 107. . Although not shown, each digit line (bit line) connected to each N-type drain region 107 is provided to be orthogonal to the word line.

In writing to a memory cell, a voltage (for example, 12 V) sufficiently higher than a power supply voltage (for example, 5 V) is applied to the control gate electrode 106 of the memory cell,
A voltage (for example, 7 V) higher than the power supply voltage is applied to the N-type drain region 107 of the memory cell via the digit line, and the P-type silicon substrate 101 and the N-type source region 10 are applied.
8 is grounded, and is performed for each bit. At this time, N
Electrons generated as hot carriers from the side of the type drain region 107 are injected into the floating gate electrode 104, and a _VTM memory cell (apparently) of a memory cell having a positive value (for example, 2 V) lower than the power supply voltage before writing. Becomes a value higher than the value of the power supply voltage (for example, 7 V: this value is determined by the bias condition and the erase time within a range determined by the capacitance division ratio).

The erasing operation in the flash memory device is performed, for example, every 512 k bits. In the memory cell shown in FIG. 5, erasing is performed by flowing electrons accumulated in the floating gate electrode 104 to the source region 108 through the tunnel oxide film 103 as a Fowler-Nordheim (FN) tunnel current. This method is called source erasing. This is performed by setting the control gate electrode 106 and the P-type silicon substrate 101 to the ground potential, applying a bias (for example, 9 V) sufficiently higher than the power supply voltage to the source region 108, and setting _VTM to a positive value lower than the power supply voltage. (The bias and erase time are set to be equal to VTM before writing). In this erase operation, a negative voltage (for example, −5 V) is applied to the control gate electrode 106 and a positive voltage (for example, +
5V), by applying a ground potential to the P-type silicon substrate 101. This method is called source gate erase.

[0006]

As one of the failure modes in the flash memory device, there is a phenomenon called over-erase. Normally, the erasing condition is set so that the target value becomes _VTM . If there is an abnormality in a specific memory cell, the value of _VTM due to erasure becomes lower than the target value. This occurs because electrons are excessively extracted from the floating gate electrode 104 of the memory cell, and this phenomenon is called excessive erasure. Even in this case, as long as _VTM after erasing is a positive value, writing is performed again. However, if _{VTM at} this time becomes negative, even if writing is performed under the above conditions, the V
_TM rises hard. If writing to this memory cell is not performed (1 state or constant _VTM state), all cells connected to the same bit line are erroneously read as being in 1 state.

[0007] Excessive erasure will be specifically described. First, FIG.
The present inventor manufactured the memory cell shown in FIG.
The power supply voltage of the flash memory device including the memory cells is 5V.

The surface impurity concentration of the P-type silicon substrate 101 having the (100) plane orientation is about 2 × 10 ¹⁷ cm ⁻³ , and the thickness of the field oxide film 102 is 0.6 μm.
It is. Tunnel oxide film 103 formed by thermal oxidation
Is about 10 nm. The floating gate electrode 104 is formed by doping polysilicon with a thickness of about 150 nm with phosphorus, and has an impurity concentration of 1 × 10 ²⁰ c.
m ⁻³ or more. As a doping method, any of a thermal diffusion method of phosphorus and an ion implantation method of phosphorus may be used. When ion implantation is used, 1 × 10 ¹⁵ cm ⁻² or more is implanted into 150 nm polysilicon. When using thermal diffusion of phosphorus using POCl ₃ , diffusion is performed at a temperature of 850 ° C. or more for 10 minutes or more. For example, at 850 ° C., 1
Polysilicon subjected to thermal diffusion of phosphorus for 0 minutes has a crystal grain (grain) diameter of 150 nm. This floating gate electrode 104 extends about 0.2 μm on one side of the field oxide film 102. The inter-electrode insulating film 105 is formed of a silicon oxide film having a thickness of about 8 nm by high-temperature vapor deposition (HTO),
VD) silicon nitride film having a thickness of about 9 nm and H
This is a three-layer insulating film in which a silicon oxide film of about 4 nm in thickness by TO is laminated. The top layer is LP instead of HTO
A film obtained by thermally oxidizing a CVD silicon nitride film may be used. The gate length and gate width of control gate electrode 106 in this memory cell are 0.8 μm and 0.8 μm, respectively.
It is formed by laminating an N-type polysilicon film having a thickness of about 150 nm and a tungsten silicide film having a thickness of about 200 nm. The junction depth of N-type source region 108 is slightly less than 0.4 μm,
8 and the floating gate electrode 104 (the depth of the lateral junction of the N-type source region 108) is about 0.25 μm. The junction depth of the N-type drain region 107 is about 0.15 μm, and the overlap between the N-type drain region 107 and the floating gate electrode 104 is about 0.1 μm.

Next, referring to FIG. 6, the write / erase characteristics of a chip in which memory cells having such parameters are integrated will be described.

The bias conditions for writing are as follows: 12 V is applied to the control gate electrode 106;
07 is applied to the P-type silicon substrate 101 and the N-type source region 108 to ground. The writing time for one memory cell is about 20 μs. The bias condition for erasing is such that the control gate electrode 106 and the P-type silicon substrate 101 are at the ground potential, and the N-type source region 108 is about 9V. However, since the potential of the source region 108 is applied via the load transistor, it varies depending on the erase state and is not constant. Source erasing is performed every 512 k bits, and the erasing time is 1 second.

In a normal chip, although the distribution of the erased state is slightly wider than the distribution of the written state, an erase distribution without any bit that makes _VTM negative is obtained. On the other hand, in a chip in which excessive erasure has occurred, the erasure distribution becomes wide because particularly fast erased bits increase, and some bits having a negative _VTM appear. As will be described later, the occurrence of such excessive erasure is closely related to the grain size of polysilicon. Conventionally, it is impossible to suppress the occurrence of excessive erasure itself, and by giving redundancy to digit lines (for example, providing one extra digit line for eight digit lines), A normally operating chip was obtained by replacing the portion where excessive erasure occurred.

[0012] For example, Japanese Patent Application Laid-Open No. 1-125980 discloses that an oxide film is grown in advance on a floating gate electrode on a polysilicon film, and then phosphorus ions are implanted into the floating gate electrode. It is reported that growth can be suppressed. However, it is well known that, even if phosphorus is implanted in a large amount, the grain grows significantly when the amount of the phosphorus implanted is large.
Very Hard to think.

An object of the present invention is to improve the polysilicon used for the floating electrode of a memory cell to suppress the occurrence of excessive erasure failure itself, which is a problem of the conventional example described above. I do.

[0014]

A nonvolatile memory according to the present invention comprises a second conductive source and drain regions provided on a surface of a first conductive semiconductor substrate, and an end of the source region and the drain region. A channel region provided on the surface of the first conductive semiconductor substrate between the ends of the first conductive semiconductor substrate, and a channel region extending over the source region and the drain region via the gate insulating film and provided on the channel region. A floating gate electrode made of a polycrystalline silicon film, and a control gate electrode covering the floating gate electrode via an inter-electrode gate insulating film, and accumulating electrons in the floating gate electrode; or MOS stacked gate type writing / writing that performs storage and erasing operations by extracting electrons from the floating gate electrode to the outside In the example non-volatile memory,
In the floating gate electrode, when extracting the stored electrons to the outside, the polycrystalline silicon contained in the region where the stored electrons flow as an electron current contains phosphorus at 1 × 10 ²⁰ c.
It is characterized in that it is doped so as to have a concentration of m ⁻³ or less, and the number of crystal grains is 20 or more. Preferably, the method of doping the polycrystalline silicon film with phosphorus is a thermal diffusion method using POCl ₃ at 850 ° C. or lower and within 10 minutes.

[0015]

FIG. 7 shows the relationship between the number of polysilicon grains used for the floating gate electrode 104 in the erased region 110 and the variance of the post-erase distribution shown in FIG. . It can be seen that when large grains are used and the number of grains becomes 20 or less, the variance value sharply increases. That is, the number of over-erased bits increases rapidly. If the number of grains used is reduced and the number included in the erasure area 110 is set to 20 or more, for example, 100, a variance of 0.02 V can be obtained. That is, the width of the distribution can be sufficiently set within the range of 1V. From these facts, if the number of polysilicon grains included in the erasure region 110 is set to 20 or more, occurrence of excessive erasure failure can be suppressed.

[0016]

【Example】

[First Embodiment] FIG. 1A is a plan view of a memory cell of a flash memory which can electrically perform a writing / erasing operation and performs a batch erasing operation, and FIG. The structure of the cell will be described with reference to b).

A one-bit memory cell is composed of one EEPROM provided on the surface of a P-type silicon substrate 101 having a (100) plane orientation and a surface impurity concentration of about 2 × 10 ¹⁷ cm ^-3.
Consists of This EEPROM has an N-type source region 108.
, An N-type drain region 107, a tunnel oxide film 103, a floating gate electrode 104, an interelectrode insulating film 105, and a control gate electrode 106.
Field oxide film 102 has a thickness of 0.6 μm.
Tunnel oxide film 103 is formed of a thermal oxide film and has a thickness of about 10 nm. This tunnel oxide film 103
A floating gate electrode 104, an inter-electrode insulating film 105, and a control gate electrode 106 are stacked on the substrate.

The floating gate electrode 104 has a thickness of 1
It is formed by doping phosphorus of about 50 nm polysilicon with an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ or less. As a doping method, any of a thermal diffusion method of phosphorus and an ion implantation method of phosphorus may be used. When ion implantation is used, 1 × 10 ¹⁵ for 150 nm polysilicon is used.
Inject less than cm ^-2 . It is more effective to perform the implantation at an implantation density of 5 × 10 ¹⁴ cm ⁻² or less. The implantation energy at this time was set to 40 keV. When using thermal diffusion of phosphorus using POCl ₃ , diffusion is performed at a temperature of 850 ° C. or less for a time of 10 minutes or less. Considering the difficulty of time control, lowering the temperature makes better controllability. However, the ion implantation method can easily realize the above conditions from the viewpoint of controllability. Under such conditions, the manufactured floating gate electrode 104 has a polysilicon grain diameter of 50 n.
m or less.

This floating gate electrode 104
One side of the field oxide film 102 extends about 0.2 μm. The inter-electrode insulating film 105 is formed by a high-temperature vapor deposition method (H
This is a three-layer insulating film in which a silicon oxide film of about 8 nm in thickness by TO), a silicon nitride film of about 9 nm in thickness by low pressure vapor deposition (LPCVD), and a silicon oxide film of about 4 nm by HTO are stacked. . The top layer is HT
Instead of O, a film obtained by thermally oxidizing an LPCVD silicon nitride film may be used. The gate length and gate width of the control gate electrode 106 in this memory cell are both 0.8
It is formed by laminating an N-type polysilicon film having a thickness of about 150 nm and a tungsten silicide film having a thickness of about 200 nm.

The N-type source region 108 and the N-type drain region 107 are connected to the control gate electrode 106, respectively.
Are provided in the element formation region on the surface of the P-type silicon substrate 101 in a self-aligned manner. This element formation region is shown in FIG.
(A) is composed of grid-like regions provided at required intervals in the vertical direction and the horizontal direction (two orthogonal directions), and the element isolation region surrounded by this element formation region has a field oxide. A film 102 is provided. The junction depth of N-type source region 108 is slightly less than 0.4 μm, and the overlap between N-type source region 108 and floating gate electrode 104 (the depth of the junction in the lateral direction of N-type source region 108) is zero. .25 μm. The junction depth of the N-type drain region 107 is about 0.15 μm, and the N-type drain region 107 and the floating gate electrode 104
Is less than 0.1 μm.

The control gate electrode 106 is a word line, and the memory cells belonging to the same word line have a common N-type source region 108. Two control gate electrodes 106 are provided between two adjacent N-type source regions 108, and these two control electrodes 1
08, an N-type drain region 107 is provided. Two horizontally adjacent memory cells provided between two N-type source regions 108 share one N-type drain region 107. Although not shown, each digit line (bit line) connected to each N-type drain region 107 is provided to be orthogonal to the word line.

Next, please refer to FIG. 2 and FIG. 1 which are cross-sectional views of the manufacturing process of the nonvolatile memory. The manufacturing method of the above embodiment will be described.

First, it has both positions of (100) and 2 × 1
Stripes having a required spacing in the first direction (longitudinal direction) on the surface of the P-type silicon substrate 101 having a surface impurity concentration of about 0 ¹⁷ cm ^-3 and extending in the second direction (horizontal direction) A LOCOS type field oxide film 102 having a thickness of 0.6 μm is formed in the element isolation region having the shape of FIG. A tunnel oxide film 103 having a thickness of about 10 nm is formed in the element formation region between the element isolation regions by thermal oxidation. The width of this element isolation region in the first direction is 0.8 μm. Then, CVD
A polysilicon film 203 is grown to a thickness of 150 nm by a method. 40% for the grown polysilicon film
An N-type polysilicon film 204 is formed by ion implantation of phosphorus at an energy of keV and a density of 5 × 10 ¹⁴ cm ⁻³ . Next, anisotropic etching is performed using a photoresist film pattern (not shown) as a mask, and the second direction (lateral direction) is set such that the entire element region is large and the overlap with the element isolation region is 0.2 μm. The N-type polysilicon film is left in the shape of an island extending in the direction (direction). Next, high temperature vapor phase epitaxy (HTO)
A three-layer insulating film 205 is formed by stacking a silicon oxide film having a thickness of about 8 nm by a low pressure chemical vapor deposition (LPCVD) method, a silicon nitride film having a thickness of about 9 nm by a low pressure chemical vapor deposition (LPCVD), and a silicon oxide film obtained by thermally oxidizing the LPCVD silicon nitride film. I do. After growing a polysilicon film having a thickness of about 150 nm, the resistance is reduced by phosphorus diffusion, and tungsten silicide is sputtered on the surface to form a polysilicon / silicide film 206.

Next, using a photoresist film pattern (not shown) as a mask, the polysilicon / silicide film 20 is formed.
The sixth and third insulating films 205 and the N-type polysilicon film 204 are sequentially anisotropically etched to form the control gate electrode 10.
6 is formed. Note that the conductor film forming the control electrode 131 is not limited to the polysilicon / silicide film (including the film thickness).

By ashing with O ₂ plasma or the like,
After the photoresist film is removed and the exposed portion of the tunnel oxide film 103 is etched, 10 μm is formed on the side surfaces of the control gate electrode 10 and the floating gate electrode 104.
A silicon oxide film (not shown) of about 20 nm is formed by thermal oxidation. Subsequently, a photoresist film pattern (shown in the figure) covering an element formation region sandwiched between two control gate electrodes 106 provided between portions of two adjacent element formation regions parallel to the first direction. The exposed field oxide film 102 is etched using the photoresist film pattern as a mask,
Further, ion implantation of phosphorus and arsenic is performed. After removing the photoresist film pattern, a heat treatment is performed to form a source region 108. A photoresist film pattern (not shown) is formed so as to cover an area opposite to the previous step,
Arsenic ion implantation is performed. Further, the photoresist film pattern is removed and a heat treatment is performed to form the drain region 107.
Is formed (FIG. 1). Although not shown, the formation of an interlayer insulating film, the formation of a bit line contact 109 reaching the drain region, the formation of a digit line, and the like are further performed, and the nonvolatile memory according to the present embodiment is manufactured.

[Embodiment 2] Next, a second embodiment of the method for manufacturing a nonvolatile memory cell will be described with reference to the cross-sectional view of FIG. 4 during manufacture (corresponding to FIG. 2A). As described with reference to FIG. 2, after forming the tunnel oxide film 102 on the P-type silicon substrate 101, the amorphous silicon 303 is grown by LPCVD at a lower temperature than polysilicon.
Is deposited. 10 to form small grains
Perform a rapid heat treatment (RTP) at 0 ° C. for 10 seconds. afterwards,
The ion implantation of phosphorus is performed under the same conditions as in the first embodiment.
The subsequent manufacturing method is the same as that of the first embodiment shown in FIGS. Further, the order of the steps of ion implantation of RTP and phosphorus may be reversed.

[0027]

As described above, according to the present invention, as is apparent from the experimental data shown in FIG. 6, by setting the number of polysilicon grains included in the erased region to 20 or more, excessive erase failure Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of a nonvolatile memory cell structure according to the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing method of the first embodiment in the order of steps.

FIG. 3 is a cross-sectional view for explaining a manufacturing method of the first embodiment following FIG. 2 in the order of steps;

FIG. 4 is a schematic sectional view showing a second embodiment of the nonvolatile memory cell structure according to the present invention.

FIG. 5 is a schematic sectional view showing a conventional nonvolatile memory cell.

FIG. 6 is a diagram for explaining a problem of the conventional flash memory cell, and is a graph showing a bit distribution after writing and after erasing;

FIG. 7 is a graph showing experimental results for explaining the operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Field oxide film 103 Tunnel oxide film 104 Floating gate electrode 105 Inter-electrode insulating film 106 Control gate electrode 107 Drain region 108 Source region 109 Bit line contact 110 Erase region 201 P-type silicon substrate 202 Silicon thermal oxide film 203 polysilicon 204 N-type polysilicon film 205 Three-layer insulating film 206 Polysilicon / silicide film 303 Amorphous silicon

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Makoto Matsuo 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Noriaki Kodama 5-7-1 Shiba, Minato-ku, Tokyo NEC (72) Inventor Takeshi Okazawa 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Satoshi Muramatsu 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Naoji Nishio 5-7-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (72) Inventor Mitsuhiro Horikawa 7-1-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Shuichi Saito 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Kenichi Arai 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (56) References JP Flat 7-94605 ( JP, A) JP-A-6-85280 (JP, A) JP-A-7-74272 (JP, A) JP-A-64-37876 (JP, A)

Claims (2)

(57) [Claims] A first conductive source region and a second drain region provided on a surface of the first conductive semiconductor substrate; and a first conductive region sandwiched between end portions of the source region and the drain region. A channel region provided on the surface of the semiconductor substrate, a floating gate electrode extending over the source region and the drain region via the gate insulating film and including a single-layer polycrystalline silicon film provided on the channel region; A control gate electrode covering the floating gate electrode with an inter-electrode gate insulating film interposed therebetween, and accumulating electrons in the floating gate electrode, or by extracting the accumulated electrons from the floating gate electrode to the outside, In a MOS stacked gate rewritable nonvolatile memory for performing a storage operation and an erase operation, In the operating gate electrode,
When extracting the stored electrons to the outside, the polycrystalline silicon contained in the region where the stored electrons flow as an electron current is doped with phosphorus so as to have a concentration of 1 × 10 ²⁰ cm ⁻³ or less, and the number of crystal grains is A nonvolatile memory, wherein the number of the nonvolatile memories is 20 or more. 2. A field insulating film is formed in a region for element isolation on a surface of a first conductive semiconductor substrate, and a tunnel insulating film is formed in a region to be an element on the surface of the semiconductor substrate;
Forming a polycrystalline silicon film having a predetermined thickness on the entire surface, the polycrystalline silicon film, the following 850 ° C. using POCl _3, in the thermal diffusion method within 10 minutes, phosphorus 1 × 10 ²⁰ cm ^-3
2. The method for manufacturing a nonvolatile memory according to claim 1, further comprising a step of doping so as to have the following concentration.