JP3061009B2 - Bias test circuit for Rambus DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias test circuit, and more particularly to a bias test circuit suitable for use in a Rambus DRAM.

[0002]

2. Description of the Related Art First, a conventional Rambus DR
The configuration and operation of a test circuit for a bias test (hereinafter abbreviated as “BT”) mounted on an AM (Dynamic Random Access Memory based on Rambus Channel interface technology) will be described.

For simplicity, 18M bits (2M × 9),
A Rambus DRAM having a two-bank configuration will be described as an example. FIG. 5 is a diagram showing a configuration of a conventional bias test circuit. Referring to FIG. 5, BusData
Address decoder 1 which receives 0-8 as input, and bank 1,
A memory cell array 2 composed of banks 2, a write buffer 3, a shift register 4, and a clock TxC
LK, RxCLK and control signals BusCtrl, Bus
Enable and Sin are input, and the internal clock CLK and the internal memory cell array control signals RASB, CAS and WR are input.
It comprises a memory cell array control signal generation circuit 5 that outputs ITE and RSTR, and a voltage detection circuit (also referred to as a “super-voltage circuit”) 6.

The voltage detection circuit 6 sets the output signal BT6011 to H level when the power supply terminal VDD becomes higher than a specific voltage (about 5 V in a 3.3 V operation product).

The memory cell array control signal generating circuit 5
When the output signal BT6011 of the voltage detection circuit 6 is input and the signal BT6011 becomes high level (this mode is referred to as a bias test mode, abbreviated as “BT mode”).
TxCLK5001, BusCtrl5002, Bus
Enable5003, RxCLK5004, SIn5
005, Nch transfer gate 52-56 ON
By doing so, each of the memory cell array control signals RAS
B5011, RSTR5012, CAS5013, CL
K5014 and WRITE5015, the input of the inverter gate 50 becomes H (High) level, and Nc
The gate terminal of the h transfer gate 51 is L (Low)
Level, the external terminal bus data BusData
1-8 (101-108) input is cut (input to the shift register 4 is cut).

The address decoder 1 has a BusData0
-8 (100-108) to row address 1010-1018 and column address 1020 of the memory cell array 2
−1027, and the bank address 1030 by the memory cell array control signals RASB5011, RSTR5012, CA
It occurs at the timing of S5013.

The shift register 4 (72 bits in the figure)
9I / 0 min × 8 bits)
The data of the external signal BusData0 (100) is sequentially shifted in synchronization with the rising edge and the falling edge of the internal clock signal CLK5014.

The write buffer 3 transfers the shift register output 4001 as an output 3001 to the memory cell array 2 of each of the two banks when the internal write control signal WRITE 5015 is at the H level.

Next, the operation of the circuit shown in FIG. 5 will be described. FIG. 6 shows a timing chart of each signal shown in FIG.

In the following, for the sake of simplicity, it is assumed that VDD 6001 is super voltage and BT 6011 is fixed at H level (in BT mode).

The timing chart in the BT mode basically includes: 1. A shift register L write set cycle (TM1) for setting all bits of the shift register 4 to L data; 2. a memory cell L test cycle (TM2) for transferring the data of the shift register 4 set to the data L to the memory cell array 2; 3. Shift register H write set cycle (TM3) in which all bits of shift register 4 are set to H data; It comprises four cycles of a memory cell H write cycle (TM4) for transferring the data of the shift register 4 set to the data H to the memory cell array 2.

Next, the operation of each cycle will be described in detail.

In the shift register L write set cycle, RASB 5011, RSTR 5012 = H, CAS
When 5013 = L, the data of BusData0 (100) is sequentially and serially stored in the shift register 4 at the fall and rise of CLK5014. FIG.
In the case of the 72-bit shift register 4, all bits are stored in 36 cycles.

Further, BusData 1-8 (101-1)
In the input BT mode from step 08), the Nch transfer gate 51 is turned off and is not input to the shift register 4.

In a memory cell L write cycle, RST
When R5012 = H, the address decoder 1
From ATA0-8 (100-108), RASB501
At the L edge of 1, row addresses 1010 to 1018 and bank address 1030 are latched, and at the H edge of CAS, column addresses 1020 to 1027 are latched.

RSTR5012 = H, RASB5011
= L period, the address decoder 1 of the memory cell array 2
The potential of the word line of the row address of the bank specified by the address rises, and during the H period of the CAS 5013, the memory cell of the column address specified by the address decoder 1 is accessed. This is similar to the operation of a normal DRAM.

The least significant bit 101 of the row address
If it is assigned to 0, the input of BusData0 repeats L and H.

At the time of accessing the memory cell as described above, when the write control signal WRITE 5015 is at the L level, a read operation of the memory cell is performed.
Since the ITE operation is performed, the WRITE 5015 is set to the H level, and the shift register 4
The data 4001 stored in the write buffer output 3
001 is written to the memory cell.

The shift register H write set cycle is B shifts compared to the shift register L write set cycle.
This is the operation when usData0 = H, and the memory cell H write cycle is the same operation as the memory cell L write cycle. Details are omitted.

[0020]

As described above, in a conventional Rambus DRAM BT test circuit, in addition to a cycle for accessing a memory cell similar to a normal DRAM, data is previously stored serially in a shift register. In such a case, in a BT device limited in specification for a normal DRAM, there is a case where a cycle for storing data in a shift register cannot be introduced due to a timing limitation, and existing equipment cannot be allocated. Therefore, in producing Rambus DRAM,
There was a problem that was an obstacle.

Accordingly, the present invention has been made in view of the above problems, and its object is to provide a Rambus
An object of the present invention is to provide a test circuit for a bias test which simplifies a bias test of a DRAM to the same extent as a general-purpose DRAM and shares a bias test apparatus.

[0022]

In order to achieve the above object, a test circuit for bias test of the present invention detects a final address of a row address and a column address and generates a pulse signal, and generates a pulse signal. Means for resetting / shifting the shift register by means of the internal memory cell array control signal.
For alternately transferring the data from the shift register.

[0023]

Embodiments of the present invention will be described. In a preferred embodiment of the present invention, a bias test mode is entered at a super voltage of a power supply terminal, and an internal memory cell array control signal and a clock signal for an internal shift register are generated in the bias test mode to generate a shift register (FIG. 1). 4) set the data, the internal memory cell array control signal to generate a row address and a column address, the memory cell array f
An address for transferring the row address and the column address
Rambus DRAM with decoder (1 in FIG. 1)
In the test circuit for bias test mounted on
The shift register (4 in FIG. 1) has a set / reset function, and means (7, 51 in FIG. 1) for separating the bus data input from the shift register in the bias test mode.
And means for generating a detection signal when the last address of a row address and a column address are detected (8 in FIG. 1).
Means for supplying a reset signal (D-type flip-flop 10, inverter 11, AND gate 12, 1 in FIG. 1)
3). Then, in the bias test mode, the shift register 4 is reset, all the row addresses and all the column addresses are accessed by the internal memory cell array control signal, and L is transferred from the shift register to the memory cell array via the write buffer (3 in FIG. 1). After writing the data, the shift register (4 in FIG. 1) is set, and H data is written to the memory cell array (see FIG. 3).

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. In FIG. 1, elements having the same functions as those in FIG. 5 are denoted by the same reference numerals. Referring to FIG. 1, one embodiment of the present invention has a configuration shown in FIG.
between usData0 (100) and shift register 4,
An Nch transfer gate 7 is added, a SET / RESET function is added to the shift register 4, and a row address 1
010-1018 and column address 1020-1027
An address final address detection circuit 8 for detecting the final address of
Inverter gates 9, 11, D-type flip-flop 1
0 and AND gates 12 and 13 are added.

Next, the operation of the embodiment of the present invention will be described. FIG. 3 is an operation timing chart of one embodiment of the present invention.

In the BT mode, the signal BT6011 becomes H
Level, the Nch transfer gate 7
F, the input to the shift register 4 from BusData0 (100) is cut. On the other hand, mutually complementary outputs (Q, Q￣) 1001, 1 of the D-type flip-flop 10
002 is output as complementary SET 1201 and RESET 1301 via AND gates 12 and 13, respectively. The AND gate 12 has a D-type flip-flop 10
The output Q1001 of the D-type flip-flop 10 and the BT 6011 and the AND gate 13
And BT6011 are input.

Thus, at the time of BT mode entry, D
Type flip-flop output Q1001 is at L level, output Q
Assuming that $ 1002 is at the H level, that is, SET 1201 is at the L level and RESET 1301 is at the H level, the output 4001 of the shift register 4 is set at the L level for all bits.

At this time, the write control signal WRITE 501
5 is at H level, the output 400 of the shift register 4
1 writes L data to the memory cell array 2 via the write buffer 3. This is all row address 101
By accessing 0-1018 and all column addresses 1020-1027, L data can be written to all addresses. This operation corresponds to the memory cell L write cycle in FIG.

When the memory cell L write cycle is executed to the last address for both the row address and the column address, the row address 1010 to 1018 and the column address 102
Address final address detection circuit 8 having 0-1027 as input
Outputs an H pulse as the address final address detection signal ADDIN8001 during the L period of the RSTR 5012.

When the D-type flip-flop output 1001 is at the L level at the time of entry into the BT mode, the D input 1101 of the D-type flip-flop is at the H level by the inverter gate 11, so that the ADDFIN8
When the H pulse of 001 is input, the outputs 1001 and 1002 of the D-type flip-flop 10 are at H level and L level, respectively.
Invert to level, ie SET1201, RESET
11 is inverted to H level and L level.

As a result, all the bits of the shift register 4 are set to the H level. By accessing this for all row addresses and all column addresses, the memory cell array 2
Can be written with H data. This corresponds to the memory cell H write cycle in FIG.

[Embodiment 2] FIG. 2 is a diagram showing a configuration of a second embodiment of the present invention. FIG. 2 shows only the differences from the first embodiment shown in FIG.

The second embodiment of the present invention differs from the first embodiment in that an EXOR (exclusive OR) gate 14 is inserted between the D-type flip-flop 10 and the AND gate 12. The output 1001 of the D-type flip-flop 10 and the least significant bit 1010 of the row address are connected as inputs, and the EXOR gate output 1401 is generated as an inverted signal by the inverter 15 and connected as the input of the AND gate 13.

FIG. 4 is a timing chart for explaining the operation of the second embodiment of the present invention.

D-type flip-flop output 1001 is BT
At the time of mode entry, if the L level is assumed to be L level, the least significant bit 1010 of the row address is L level (H level).
, The SET 1201 is at L level (H level), RES
ET1301 becomes H level (L level). In other words, when the row address is even, SET 1201 is at L level, RESET 1301 is at H level, and when RESET 1301 is odd, the opposite is true. For example, a word of an even address of a row is physically replaced with a TRUE cell and a word of an odd address. When a NOT cell is physically arranged in the memory cell, all bits of physical L data can be written to the memory cell.

Further, when the row / column address reaches the final address, the D-type flip-flop output 1001 goes low.
The EXOR gate output 1401 has the least significant bit 1010 of the row address at L level.
At the level (H level), SET 1201 is at H level (L level), and RESET 1301 is at L level (H level). That is, when the row address is an even number, S
When the ET 1201 is at the H level and the RESET 1301 is at the L level and the number is odd, the opposite is true, so that all-bit physical H data can be written to the memory cell.

With this configuration, in this embodiment, a physical stress can be efficiently applied to the memory cell, and the BT time can be reduced.

[0039]

As described above, according to the present invention,
Rambus D at the same timing as a normal DRAM
The BT of the RAM can be executed, and the operation efficiency of the production equipment can be improved.

The reason is that, in the present invention, Ramb
us In the BT test circuit mounted on the DRAM, Nch is connected between BusData0 and the shift register.
Add transfer gate and set to shift register
/ RESET function, an address final address detection circuit for detecting the final address of a row address and a column address,
This is due to the addition of an inverter gate, a D-type flip-flop, and an AND gate.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional technique.

FIG. 6 is a timing chart for explaining the operation of the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Address decoder 2 Memory cell array 3 Write buffer 4 Shift register 5 Memory cell array control signal generation circuit 6 Voltage detection circuit 7, 51-56 Nch transfer gate 8 Last address detection circuit 9, 11, 15, 50 Inverter gate 10 D flip-flop 12 and 13 AND gate 14 EXOR gate 100-108 External input BusData0-8 901, 1101, 1501 Inverter output 1001, 1002 D-type flip-flop output 1010-1018 Row address decode signal 1020-1027 Column address decode signal 1030 Bank address Decode signals 1201 and 1301 AND gate output (SET, RE
SET signal) 1401 EXOR gate 3001 Write buffer output 4001 Shift register output 5001 External input TxCLK 5002 External input BusCtr1 5003 External input BusEnable 5004 External input RxCLK 5005 External input SIn 5011 to 5015 Memory cell array control signal 6001 External power supply terminal 6011 Voltage detection circuit output 8001 Address final address detection circuit output

Claims (3)

(57) [Claims] 1. A bias test mode is entered at a super voltage of a power supply terminal, an internal memory cell array control signal and a clock signal for an internal shift register are generated in the bias test mode, and data is set in the shift register. internal memory cell array control signal, a row address and a column address is generated, the memory cell array f before
Address data for transferring the row address and column address
Bar mounted on Rambus DRAM with coder
A test circuit for performing an eas test, a means for generating a detection signal when detecting a final address of a row address and a column address; a means for setting / resetting the shift register based on the detection signal; and the internal memory cell array. Means for alternately transferring H data / L data as cell data from the shift register to the memory cell array in response to a control signal. A test circuit for a bias test. 2. An entry into a bias test mode at a super voltage of a power supply terminal, an internal memory cell array control signal and a clock signal for an internal shift register are generated in the bias test mode, and data is set in the shift register. internal memory cell array control signal, a row address and a column address is generated, the memory cell array f before
Address data for transferring the row address and column address
Bar mounted on Rambus DRAM with coder
A test circuit for bias test , wherein the shift register has a set / reset function, and means for separating a bus data input from an external terminal from the shift register in a bias test mode, and a final address of a row address and a column address. Means for generating a detection signal upon detection, and supplying a signal for alternately setting / resetting the shift register according to the output of the detection signal;
In the bias test mode, the internal memory cell array control signal accesses all row addresses and all column addresses, writes one logical data from the shift register to the memory cell array, and then writes the opposite logical data. Rambus DRAM characterized by the following:
Bias test circuit. 3. A bias for a Rambus DRAM according to claim 2, further comprising means for switching a signal for activating a signal for setting and resetting the shift register in accordance with evenness of the row address. Test circuit.