JP3060920B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing digital signal processing such as tone generation processing and effect addition processing on digital data such as sound waveform data, and more particularly to an apparatus for executing processing with reference to a memory. (For example, a sound source that performs a tone generation process on waveform data read from a waveform memory, an effector that performs a delay process on tone data using a delay memory, and the like) for inputting and outputting data to and from the outside of the apparatus. The present invention relates to simplifying a circuit configuration and enhancing its applicability.

[0002]

2. Description of the Related Art In recent years, based on advances in semiconductor technology and digital signal processing technology, a waveform memory sound source constituted by an LSI has been adopted in a tone generator such as an electronic musical instrument or a sound source board for a personal computer. The waveform memory sound source reads out waveform data (for example, PCM (pulse code modulated) waveform data or the like) stored in the waveform memory at a pitch corresponding to performance information, and executes a predetermined process on the waveform data. This generates and processes musical sound data.

The tone generation process executed by the waveform memory tone generator includes, for example, the following processes. (1) Digital filter processing for controlling timbre by performing filter operation on waveform data (2) Volume control processing for multiplying waveform data by information indicating a volume envelope (3) Processing for modulating pitch, timbre or volume ( 4) Processing for mixing waveform data of each sounding channel (5) Processing for adding an effect (for example, reverb)

[0004] By the way, such tone generation processing executed by the waveform memory sound source is performed not only on the waveform data from the waveform memory but also on the waveform data from other sources than the waveform memory (for example, the performance sound of a musical instrument by a user by a microphone). This is a useful process even if it is performed on the picked-up analog / digital converted waveform data). Therefore, it is desired that waveform data from a source other than the waveform memory (hereinafter, also referred to as external waveform data) can be input to the waveform memory sound source.

However, the tone generator system including the tone generator LSI and the waveform memory is configured as a closed system as it is, and cannot input external waveform data. For this reason, conventionally, a sound source LSI provided with a dedicated input terminal (for example, a terminal for serial input) for inputting external waveform data is designed and manufactured.
An interface for converting the format of the external waveform data for this input terminal had to be provided.

[0006]

However, providing such an interface leads to an increase in size and cost of the entire sound source system. In addition, providing an input terminal dedicated to external waveform data in a sound source LSI involves the complexity of having to change the design of an existing sound source LSI having no such input terminal.

When it is desired to input a plurality of systems of external waveform data, it is sufficient if an input terminal dedicated to the plurality of systems of external waveform data can be provided in the tone generator LSI. This leads to higher costs. Therefore, generally, only one input terminal dedicated to external waveform data is provided,
The input terminals are used in a time-division manner for the assumed maximum number of systems, so that external waveform data of a plurality of systems can be input. However, how many systems of external waveform data the user wants to input to the input terminal differs depending on the situation. Actually, only a smaller number of systems than expected are often input. Therefore, there is a problem that there is waste in use. Furthermore, with the increase in the width of the waveform data (ie, the number of bits representing the waveform data), providing an input terminal dedicated to external waveform data, even with only one system, still requires a sound source L
This leads to an increase in the size and cost of the SI.

The present invention has been made in view of the above points, and can input waveform data from a device other than the waveform memory with a small and low-cost configuration without providing a dedicated input terminal or interface. It is intended to provide a sound source system. In addition, not only a waveform memory sound source but also a DSP (Digital Signal Processor) for effect processing and a DS used as a physical model sound source
Similarly, in a DSP such as P that exchanges data with a delay memory, there is a demand for inputting and outputting various data while saving input / output terminals and interfaces. For example, DSP for effect processing
In addition, there is a case where an effect is to be added by inputting not only the tone data generated by the sound source but also, for example, tone data of a musical instrument performed by a user by a microphone and analog / digital converted, and the like. Therefore, an object of the present invention is to provide a small-sized and low-cost DSP that saves input / output terminals and interfaces.

[0009]

A digital signal processing apparatus according to the present invention has storage means for storing data, and a data input terminal, and a first address for designating a data storage area of the storage means. Processing means for selectively outputting one of a signal and a second address signal different from the first address signal, and performing required processing on data input through the data input terminal; Outputs the first address signal, and causes the data read from the storage unit to be input to the processing unit through the data input terminal based on the first address signal. In response to outputting the second address signal, data supplied from other than the storage means is input to the processing means through the data input terminal. Those equipped with an input control means.

Further, the digital signal processing device according to the present invention has storage means for storing data, and a data output terminal, wherein a first address signal for designating a data storage area of the storage means and Processing means for selectively outputting any one of the second address signals different from the first address signal and outputting required data from the data output terminal; and the processing means outputting the first address signal. In response, the data output from the data output terminal of the processing unit is stored in a storage area of the storage unit designated based on the first address signal,
On the other hand, output control means for outputting, as output data, data output from the data output terminal of the processing means in response to the processing means outputting the second address signal.

Further, the digital signal processing device according to the present invention comprises: a readable / writable storage means for storing data;
A data input / output terminal connected between the data input / output terminal of the storage means and a first address signal for specifying a data storage area of the storage means; and a first address signal different from the first address signal. Processing means for selectively outputting any of the second and third address signals; and the first means for outputting the first address signal in response to the processing means outputting the first address signal.
Data is written or read between a storage area of the storage means designated based on the address signal of the first step and the data input / output terminal of the processing means, while the processing means transmits the second address signal. In response to the output, the data supplied from other than the storage means is input to the processing means through the data input / output terminal, and further,
Input / output control means for outputting data output from the data input / output terminal of the processing means as output data in response to the processing means outputting the third address signal.

Further, the digital signal processing apparatus according to the present invention has storage means for storing data, and terminal means for at least one of data input and output, and a data storage area of the storage means is provided. Generating an address signal to be specified, writing or reading data between the storage area of the storage means and the terminal means specified based on the address signal, and performing data input or output through the terminal means. Processing means for performing required processing, or outputting the data subjected to the required processing through the terminal means, at least one of a data input end and a data output end, and for the terminal means of the processing means,
Connecting means for selectively connecting at least one of the data input end and the data output end to the storage means; and the terminal means of the processing means being connected to at least one of the data input end and the data output end and the storage means And control means for controlling selective connection of the connection means in accordance with information indicating which connection is to be made.

Further, the digital signal processing apparatus according to the present invention generates a storage means for storing data, and an address signal for designating a data storage area of the storage means, and the storage designated on the basis of the address signal. Processing means for performing at least one of data writing and reading with a data transmission / reception wiring interposed in the storage area of the means; an interruption wiring for at least one of data input and output; and a data transmission / reception wiring. The interruption wiring is connected thereto, and at the time of a required interruption, inputting the data of the interruption wiring to the data transmission / reception wiring and outputting the data of the data transmission / reception wiring from the interruption wiring at least. Control means for performing one of the operations. Further, in the digital signal processing device according to the present invention, a plurality of pairs of the storage means and the processing means are provided, and the interrupt wiring and the control means are provided for each pair, and at least two pairs of the interrupt wiring are provided. Are connected to each other so that data output from one pair of data transmission / reception lines via the interruption line is input to the data transmission / reception line via the other pair of interruption lines.

Further, the digital signal processing apparatus according to the present invention repeats execution of a storage means for storing data and a processing cycle comprising a plurality of time-division time slots. Processing means for generating an address signal for designating a data storage area of the storage means in a divided time slot, and performing at least one of writing and reading of data with respect to the storage area of the storage means specified based on the address signal And has at least one of an input terminal for capturing data and an output terminal for outputting data, and interrupts data wiring between the processing means and the storage means.
Input or output control means for controlling input or output of data between the input terminal or output terminal and the processing means or storage means, wherein at least one of time-division processing time slots in the processing means is provided. The input terminal or the output terminal is used to access the processing means or the storage means, and in other time-division processing time slots, the processing means is controlled to access the storage means.

The processing means in the present invention includes:
Any circuit, such as a waveform memory sound source or an effector, may be used as long as it performs a required digital signal processing by referring to the memory. According to the present invention, when a first address signal designating a data storage area of the storage means is generated from the processing means, the processing means accesses the storage means, and data is read or written to or from the storage means. . On the other hand, when a second address signal or a third address signal which is different from the first address signal (that is, does not designate a data storage area of the storage means) is generated, the processing means accesses the storage means. To input data supplied from other than the storage means to the processing means via an input or output terminal for performing the processing, or to output data output from the processing means as output data to a circuit other than the storage means (to the outside) )Output.

Such switching control by the input or output control means is not limited to being performed based on the use of the first to third address signals as described above, but may be performed by other means such as an appropriate switching command signal. It can also be realized by separately outputting from means or the like. But,
According to the use of the first to third address signals as described above, an effective switching instruction can be issued by decoding the value using the existing address bus (address data output pin). This is advantageous because it is not necessary to set a special data pin (perhaps only about 1 bit) for separately outputting the switching command signal from the processing means.

In a broad sense, the processing content of the processing means repeats execution of a processing cycle including a plurality of time-division time slots. In this case, the plurality of time-division time slots are synonymous with the time-division processing channel in the waveform memory sound source, and are also synonymous with each operation step in one cycle in the effector. Usually, as is known, the processing means accesses the storage means to read or write data. In accordance with the invention, the input or output control means has an input terminal (which can be used for external data capture) or an output terminal (which can be used for external data output) processing means. When accessing the storage means, access to the storage means of the generally known processing means is prohibited. Therefore, the processing means has a common data input or output terminal (data pin)
Can be used to selectively access either the input terminal or the output terminal of the storage means and the input or output control means. This is because when the processing means is configured by an integrated circuit such as an LSI, the data pin configuration can be saved.
It means that it can be simplified. In other words, the embodiment of the present invention is different from the viewpoint in that a wire (interrupt) connected to an input terminal or an output terminal of an input or output control means is connected to a generally known data transfer wiring between a processing means and a storage means. Can be said to be in a form of physically interrupting the wiring. The interrupt would then be controlled by the second or third address signal, or by the switch command signal described above. However, although the term "interrupt" is used, it does not refer to an interrupt of software program processing that is generally known, but rather to a physical interrupt (horizontal insertion) for data transfer wiring.

Thus, according to the present invention, in a digital signal processing apparatus including a processing means and a storage means, an existing input or output provided in the processing means for accessing the storage means is provided. Using a terminal (data pin), external data can be taken into the processing means, or output data of the processing means can be output (outside) to a circuit other than the storage means. Therefore, when the processing means is configured by an integrated circuit such as an LSI, there is no need to increase the number of data pins particularly.
It is possible to easily realize input data input from outside the processing device or data output to the outside of the processing device. Moreover, the switching control of whether to use the existing input or output terminal provided in the processing means for reading / writing data to / from the storage means, or to use external input data or to output data to the outside is performed by: Since this can be achieved by controlling the value of the address signal generated inside the processing means, it can be easily realized by simple control or program processing. Therefore, no special load is imposed on the circuit design / production of the processing means (waveform memory sound source, effector, etc.), and the circuit can be used as it is, so that it is easy, and the number of pins in the case of an integrated circuit is easy. It has excellent effects such as an increase in the size of the configuration and an increase in the cost due to the expansion.

Further, according to the present invention, even if a processing means constituted by an LSI circuit having an existing design concept having no special data pin for external input or external output is used, external input data can be fetched according to the present invention. Alternatively, since data output to the outside can be realized, the function can be extended, and various uses can be performed, thereby achieving an excellent effect that its applicability can be enhanced. Further, since it is easy to perform data input / output by connecting a plurality of pairs of processing means and storage means and connecting them to each other, it is possible to expand the functions of various sound effects or to use a plurality of different sound effects. , Or to extend the musical tone waveform synthesis processing function.

[0020]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. [Embodiment 1] FIG. 1 shows an embodiment in which the present invention is applied to a waveform memory sound source. In FIG. 1, the waveform memory sound source includes a waveform memory 1 and a sound source 2. The waveform memory 1 is a memory that stores a plurality of types of PCM (pulse code modulated) tone waveform data having one or more periods, and may be, for example, a ROM (Read Only Memory) or a RAM (Random). It may consist of a readable and writable storage device, such as an access memory, or a combination of both (for example, ROM in one address range and RAM in another address range). Hereinafter, for convenience of explanation, it is assumed that the waveform memory 1 is composed of a ROM.

The tone generator 2 mainly reads out the waveform memory 1 and reproduces the PCM musical tone waveform data based on the readout. For example, volume control processing, timbre control processing, mixing processing, etc.) are performed, and are composed of LSI circuits. It has an input terminal Tin for receiving various instructions for reproduction processing and other appropriate data, and an output terminal Tout for outputting digital musical tone waveform data after reproduction processing. The sound source 2 has an address output terminal Tad for supplying a read address signal to the waveform memory 1 and a waveform data input terminal Twin for inputting digital tone waveform data read from the waveform memory 1. . The input terminal Tin of the sound source 2 is connected to an appropriate interface (not shown).
And / or via other necessary circuitry (not shown) to an operation panel (not shown) and / or a keyboard (not shown) and / or a MIDI interface and wiring (see FIG. Various commands and data may be input via a not shown). The tone waveform data output from the output terminal Tout may be sent to a sound system (not shown) to be acoustically generated, or may be digitally converted to provide an appropriate tone effect. Signal processor (DS
P) (not shown).

An input control unit 3 is provided between the sound source 2 and the waveform memory 1 so that a sound signal input from the outside can be taken into the sound source 2 via the input control unit 3. Has become. For example, an arbitrary analog sound signal (may be a musical instrument performance sound, a vocal voice, or another noise sound or a sound effect) may be used.
Picked up by the microphone MIC, A /
The signal is converted from analog to digital by the D converter ADC, input to the input control unit 3, and taken into the sound source 2 via the input control unit 3. The input control unit 3, which will be described in detail later, uses the waveform data input terminal Twin provided for taking the musical tone waveform data read from the waveform memory 1 into the sound source 2, and uses the waveform data of the external input sound. Can also be taken into the sound source 2. That is, by the function of the input control unit 3, the sound source 2 does not have to provide a dedicated waveform data input terminal for taking in an external input sound, and the existing waveform data input terminal Twi for taking in the memory read waveform data.
It is characterized in that waveform data of an external input sound can be taken in by also using n.

As an example, the sound source 2 is configured to access the waveform memory 1 in a 16-channel time-division system for reproducing and reading out the waveform memory 1. FIG. 2 shows an example of the time-division reproduction processing timing. In FIG. 2, symbols CH1 to CH16 indicate time-division time slots corresponding to channels 1 to 16, respectively.
As is well known, the reading of the musical tone waveform data stored in the waveform memory 1 is performed with respect to the storage area (address range) of the memory 1 storing the desired musical tone waveform data to be read. Is performed by generating a progressively changing read address signal so as to sequentially designate the sequential addresses at the read rate according to a desired reproduction pitch. In the sound source 2, a read address signal AD that progressively changes progressively at a read rate corresponding to the pitch of a musical tone assigned to be emitted in a certain channel is assigned to a time division time slot of the channel. It occurs in a time-sharing manner and is output from the address output terminal Tad. It is possible to arbitrarily generate a read address signal AD which changes at a unique read rate for each channel, and arbitrary tone waveform data stored in the waveform memory 1 is output at an arbitrary pitch for each channel. It can be read out in a time-sharing manner. Therefore, for example, if all 16 channels are used for reading out the waveform memory 1, the maximum number of musical tones that can be reproduced simultaneously using the waveform memory 1 is 16 tones.

According to the present invention, the sound source 2 is characterized in that one or more of the time-division processing channels can be used for a process of capturing sound waveform data input from the outside. Therefore, when the “external sound input mode” is designated by the command data given from the input terminal Tin, the sound source 2 has one or more predetermined channels (one channel in the example of FIG. 1).
Is set as a channel for taking in an external input sound. The command to specify such “external sound input mode” is
It may be provided based on an operation of an operator (not shown) by the operator, or may be provided by appropriate external data input or the like.

When the "external sound input mode" is designated as described above, the reproduction and reproduction of the musical tone based on the reading of the waveform memory 1 are assigned to channels other than the predetermined channel for taking in the external input sound. The read address signal AD is generated in a time-sharing manner according to the assignment.
On the other hand, a predetermined address signal A is generated in a channel for taking in an external input sound. The predetermined address signal A indicates a predetermined address value other than an address value (address range) corresponding to all data storage areas in the waveform memory 1. Therefore, when the “external sound input mode” is designated, the read address signal AD and the predetermined address signal A for taking in the external input sound correspond to the address output terminal corresponding to the time division time slot of each channel. Output from Tad. For example, when the second channel (CH2) is an “external input sound capturing channel”, a predetermined address signal A for capturing an external input sound is output in the time-division time slot CH2 of the second channel. In the time-division time slots CH1 and CH3 to CH16 corresponding to the channels, the read address signals AD which change in accordance with the pitches of the musical tones assigned to the respective channels are output.

Of course, when the “external sound input mode” is not designated, all channels can be used for reading out the waveform memory 1. In that case, time-division time slots CH1 to CH16 corresponding to all channels
Outputs a read address signal AD which changes in accordance with the pitch of the musical tone assigned to each channel. The predetermined channel for capturing the external input sound may be fixed to a predetermined channel, or the operator may freely select which channel is the “channel for capturing the external input sound”. May be selected. In addition, as described later,
At the timing of latching the external input sound waveform data UD in the latch circuit 8 (for example, the timing of CH1), the output data of the latch circuit 8 may change transiently.
It is better to avoid setting a channel corresponding to the latch timing as a “channel for capturing an external input sound”.

In the input control section 3, the address signal A output from the address output terminal Tad of the sound source 2 in a time-division manner.
D and A are input to the decoder 4. The decoder 4
Based on the address value of the input address signal, it is determined whether the address signal is the read address signal AD or the address signal A for taking in an external input sound, and when the address signal is the read address signal AD, the output X is output. And outputs the signal AD to the address input of the waveform memory 1, and sets the 1-bit output Y signal to L (low) level. On the other hand, when the input address signal of the decoder 4 is the address signal A for taking in the external input sound, the output X is not output, and the 1-bit signal of the output Y is set to the H (high) level. The signal of the output Y of the decoder 4 is input to the control terminal of the tri-state output buffer 5 and, after being inverted by the inverter 6, is input to the control terminal of the tri-state output buffer 7.
The tristate output buffers 5 and 7 output the input data as it is when the input of the control terminal is at the H level (referred to as ON), while the input of the control terminal is at the L level.
When the level is at the level, the output is in a high-impedance state (referred to as off). According to the level of the output Y of the decoder 4, when one of them is on, the other is off. One of the sound waveform data UD will be selected.

The input of the tri-state output buffer 7 includes the tone waveform data PS read from the waveform memory 1.
D is input. On the other hand, the waveform data UD of the external input sound output from the A / D converter ADC is
The latch is latched by the latch circuit 8 according to a latch timing signal generated at a predetermined timing for each reproduction sampling cycle (for example, according to a latch timing signal generated at time division timing of the channel CH1 as shown in FIG. 2). The output of latch circuit 8 is provided to the input of tri-state output buffer 5. The outputs of the tri-state output buffers 5 and 7 are commonly connected for each bit, and are applied to a waveform data input terminal Twin.
Is input to

Therefore, when the address signal output from the tone generator 2 indicates the read address signal AD of the waveform memory 1, the tristate output buffer 7 is turned on by the L level of the output Y of the decoder 4, and The read address signal AD is applied to the waveform memory 1 via the output X of the decoder 4, and the tone waveform data PSD read from the waveform memory 1 in response to the read address signal AD passes through the buffer 7, It is input to the sound source 2 via the data input terminal Twin. On the other hand, when the address signal output from the sound source 2 indicates the address signal A for capturing an external input sound, the tri-state output buffer 5 is turned on by the H level of the output Y of the decoder 4, and the latch circuit 8 is turned on. The externally input sound waveform data UD passed through the buffer 5 is input to the sound source 2 via the waveform data input terminal Twin.

As an example, FIG. 2 shows an example in which the output Y of the decoder 4 becomes H level in the time slot CH2 of the channel 2. In such an example, data applied to the waveform data input terminal Twin is, as shown in FIG.
CH3 to CH16, which are the read output waveform data PSD of the waveform memory 1, and the time slot CH2 of the channel 2
Are output waveform data UD of the latch circuit 8.

The tone generator 2 performs predetermined reproduction tone processing for each channel based on the waveform data PSD or UD input via the input terminal Twin in each of the time-division channel time slots CH1 to CH16.
Output to out. The waveform data of each channel may be mixed and then output to the output terminal Tout, or the output terminal Tou may be separately output for each channel.
t may be output to the output terminal T
You may make it output to out. As described above, the externally input sound waveform data UD can be captured by the sound source 2 without providing a dedicated input terminal for capturing the externally input sound waveform data. 2 can perform various types of reproduction tone processing and mixing processing that can be applied to the external input terminal pins that can be processed without particularly expanding the input / output terminal pin configuration of the LSI circuit for the PCM sound source (namely, the sound source 2). The width of data can be expanded, and therefore, the application range of the waveform memory sound source can be expanded with a simple configuration.

[Embodiment 2] In the embodiment of FIG. 1, the number of external input sounds that can be taken into the sound source 2 is one. This is because the input control section has a modified configuration as shown in FIG. 13 can be changed so that a plurality of external input sounds can be captured. FIG.
In the embodiment, in order to be able to simultaneously capture at most n external input sounds (for example, n is a number arbitrarily selected from an integer of 2 or more and 15 or less), n
The microphones MIC1 to MICn and the A / D converters ADC1 to ADCn are provided in parallel. In response to this, in the input control unit 13, each A / D converter A
N latch circuits 81 to 8n are provided in parallel to latch the external input sound waveform data UD1 to UDn output from DC1 to ADCn, respectively, and inputs the outputs of the latch circuits 81 to 8n, respectively. N tristate output buffers 51 to 5n are provided in parallel. As described above, the outputs of the tri-state output buffers 51 to 5n and 7 are commonly connected for each bit and input to the waveform data input terminal Twin of the sound source 2. Each latch circuit 8
The latch timings 1 to 8n may be the same common predetermined timing as described above (for example, the timing of CH1).

In the sound source 2, the "external sound input mode"
Is designated, the address signals A1 to An different from one another are respectively output to the address output terminals Tad corresponding to the time division time slots corresponding to the predetermined n channels,
It is provided to the decoder 14. Each of the address signals A1 to An is
As in the case of the above-mentioned address signal A, the address signal indicates a predetermined address value for taking in an external input sound, which is different from the value indicated by the address range corresponding to the storage area of the waveform memory 1, and each value is different from each other. ing. Of course, as described above, even when the "external sound input mode" is designated, in the time division time slot corresponding to a channel other than the predetermined n channels, the tone assigned to the channel is not assigned. The read address signal AD, which changes progressively in accordance with the pitch of the
Output to ad.

The decoder 14 decodes the value of the input address signal in the same manner as the above-mentioned decoder 4. If the address signal is the read address signal AD, the decoder 14 outputs the read address signal AD as it is to the output X and outputs each of the outputs Y1 to Y1. All of the signals Yn are set to the L level. On the other hand, if any of the externally input sound capturing address signals A1 to An, the output Y1 is output.
.. Yn, the corresponding output is set to H level, and the remaining output is set to L level. The signals of the respective outputs Y1 to Yn of the decoder 14 that decode the external input sound capturing address signals A1 to An are separately input to the control terminals of the respective tristate output buffers 51 to 5n for capturing the external input sound. After being inverted by the inverter 6 via the OR circuit 11, the signal is input to the control terminal of the tristate output buffer 7.

Next, an example of the operation of reproducing waveform data in the embodiment of FIG. 3 will be described. When it is desired to reproduce only the tone waveform data PSD stored in the waveform memory 1, as in the embodiment of FIG. A read address signal AD which changes in accordance with the pitch is output, and all channels are used for reading the waveform memory 1. A description will be given of a reproduction operation example when the “external sound input mode” is designated. As in the above embodiment, the predetermined channel for capturing the external input sound may be fixed to a predetermined channel, or which channel is set as the “channel for capturing the external input sound”. May be freely selected by the operator. Also,
The number of “channels for taking in external input sounds” may be fixed to n corresponding to the number of microphones MIC1 to MICn, or may be fixed to n and set to arbitrary m (m is (1 ≦ m ≦ n, a natural number).

For example, the operator uses an operation switch or the like to set any m channels as “channels for capturing external input sounds”, and to set waveforms for the remaining 16-m channels. The memory 1 is used for reading. In response to this, the sound source 2 generates the memory read address signal AD and the externally input sound capturing address signals A1 to Am in a time-division manner corresponding to the respective predetermined channels. In response,
In the channel time slot where the external input sound capturing address signals A1 to Am are generated, the decoder 4
H-level signals are generated from the corresponding outputs among the outputs Y1 to Yn, and the corresponding tristate output buffers 51 to 5n are turned on in a time-division manner, and the corresponding external input sound waveform data UD1 to UDn are time-divisionally output. And input to the waveform data input terminal Twin. On the other hand, in the channel time slot in which the memory read address signal AD is generated, all of the outputs Y1 to Yn of the decoder 4 are at L level, and the tristate output buffer 7 is turned on via the OR circuit 11 and the inverter 6,
The tone waveform data PSD read from the waveform memory 1 in accordance with the output X of the decoder 4 is selected in a time-division manner and input to the waveform data input terminal Twin.

In each of the above embodiments, the waveform memory 1 is not limited to PCM-encoded tone waveform data, but may be any other more compressed data encoding method (eg, DPCM, ADPCM, or delta modulation). May be stored. In this case, a process of demodulating the memory read waveform data PSD into ordinary PCM data is performed inside the sound source 2, and the tone waveform data of PCM may be output to the output terminal Tout. In the case where the waveform memory 1 includes a writable storage device such as a RAM, the external input sound waveform data fetched by the input control units 3 and 13 can be written into the waveform memory 1. You may. For that purpose, the tristate output buffer 7 may be configured using a bidirectional tristate output buffer. In each of the above embodiments, the microphones MIC, MIC1 to MI
At least one of the series of the Cn and the A / D converters ADC, ADC1 to ADCn is replaced with a data bus or a communication line or the like, and data supplied from the outside via the data bus or the communication line or the like is input to the input control unit 3. , 13 to the sound source 2. A plurality of series of data UD1 input to the input / output control unit 13 in FIG.
To UDn may be supplied in a time-division multiplexed state.

[Embodiment 3] Next, an electronic musical instrument equipped with a waveform memory sound source according to the present invention will be described. FIG.
FIG. 1 is a block diagram showing the overall configuration of such an electronic musical instrument. This electronic musical instrument comprises a personal computer to which a sound source board is connected, and a display 101, a keyboard 102, a ROM 104, a RAM 105, a MIDI 10
6 and a sound source 108 are connected to the CPU 103 via a data and address bus 107. MIDI106
Is supplied with performance information from a sequencer or the like (not shown).

The tone generator 108 is an LSI circuit which performs tone generation processing in a time-division manner on a predetermined number of tone generation channels (for example, 16 channels (CH1 to CH16)) in the same manner as the tone generator 2 in the embodiment of FIG. is there. CPU1
From 03, information (commands and parameters) for controlling the operation of the sound source 108 for each channel is supplied based on the performance information supplied to the MIDI 106 and the operation of various switches on the keyboard 102. The waveform memory 110 is a memory that stores waveform data of a plurality of types of timbres having one or a plurality of cycles, similarly to the waveform memory 1 in the embodiment of FIG.

Microphone MIC provided in two systems
As in the embodiment of FIG. 1, any sound from outside can be picked up and supplied to the A / D converter ADC. From the system clock generator (not shown) in the sound source 108, as shown in FIG.
It is provided to the D converter ADC. The A / D converter ADC is
Triggered by the synchronization signal S, each microphone M
The digital conversion processing of the external waveform data from the IC is sequentially performed. As a result, from the A / D converter ADC, FIG.
As shown in (b), a completion signal indicating the completion of the digital conversion processing of the external waveform data of each system is generated at each reproduction sampling period, and the waveform data is output and supplied to the input control unit 109. Is done.

FIG. 6 shows an example of the configuration of the sound source 108.
The control information supplied from the CPU 103 is stored in the control register 112. The address generator 113 specifies a read address signal (an address area corresponding to the rising edge of the waveform at a predetermined speed, based on the information from the control register 112, and then specifies an address area corresponding to the sustaining portion of the waveform. ) Is generated in a time-division manner. Of the read address signal, an address signal WMA indicating an integer part of the address is output from the sound source 108 through the address output terminal Tad, and is input to the input control unit 109. The signal indicating the decimal part of the address is supplied to the waveform calculation unit 115.

In the input control unit 109, the address signal WM
A is passed through as it is to the waveform memory 110 and is input to the decoder 117. Decoder 117
Is an address signal WMA at each channel timing.
Is used to specify whether or not designates a storage area of the waveform data in the waveform memory 110. As a method for this decoding, for example, as shown in FIG.
An area (alias) other than the storage area of all the waveform data in the waveform memory 110 is assigned to an address signal WM in which the values of upper predetermined bits (for example, upper 6 bits) are all “1”.
A, the storage area of all the waveform data in the waveform memory 110 may be designated by the address signal WMA of other values, and the decoding may be performed based on the value of the upper predetermined bits. The decoder 117 outputs “X” at an H (high) level and outputs “Y” at an L (low) level at a channel timing at which the decoding result is correct, and at a channel timing at which the decoding result is negative at the channel timing at which the decoding result is positive. , “X” output goes to L level and “Y”
The output becomes H level. The “X” output of the decoder 117 is output from the input control unit 109 and is output to the waveform memory 11.
0 is input to the read control input OE. Waveform memory 11
0 is the channel timing at which the input to the control input OE becomes H level (that is, the address signal WMA is
In the channel timing for designating the storage area of the waveform data in the waveform memory 110, reading is enabled, while the channel timing at which the input to the control input OE is at the L level (that is, the address signal WMA is transmitted to the waveform memory 110) Area other than the storage area of the waveform data in FIG.
Read is prohibited at the channel timing) that specifies the alias of The waveform data read from the waveform memory 110 in accordance with the address signal WMA passes through the input control unit 109 as it is, and the waveform data input terminal T
The signal is supplied to the waveform calculation unit 115 in the sound source 108 through win.

The “Y” output of the decoder 117 is input to the control terminal of the tri-state output buffer 118. The waveform data supplied from the A / D converter ADC is input to the tri-state output buffer 118. The tri-state output buffer 118 stores the channel timing at which the input to the control terminal is at the H level (that is, the address signal WMA is stored in the waveform memory 110).
In the channel timing that designates an area other than the storage area of the waveform data, the input data is output as is,
On the other hand, at the channel timing when the input of the control terminal is at the L level (that is, the channel timing at which the address signal WMA specifies the storage area of the waveform data in the waveform memory 110), a high impedance state is set. The waveform data output from the tri-state output buffer 118 is output from the input control unit 109 and, like the waveform data from the waveform memory 110, the waveform calculation unit 115 in the sound source 108 through the waveform data input terminal Twin.
Supplied to (Note that the input / output terminals of the sound source 108 other than the address output terminal Tad and the waveform data input terminal Twin
Illustration is omitted. )

The waveform operation section 115 has an arithmetic and logic operation mechanism, and outputs waveform data WMD (ie, waveform data from the waveform memory 110 or an external waveform from the A / D converter ADC) supplied through the input terminal Twin. data)
On the other hand, the tone generation process is executed in a channel time-division manner using the information from the control register 112, the signal indicating the decimal part of the address from the address generator 113, the volume envelope data from the envelope generator 114, and the like.

FIG. 8 is an equivalent block diagram of the waveform calculation unit 115 for showing an example of the algorithm of the tone generation processing. First, interpolation processing is performed on the waveform data WMD using a signal indicating the decimal part of the address from the address generator 113 according to the pitch (201). Next, digital filter processing is performed on the waveform data (20
2). In this process, the frequency characteristic (sound quality) is controlled by performing a filter operation while changing the filter coefficient in accordance with performance information such as touch and the passage of time. Further, tone color modulation can also be performed in this process.

Subsequently, a volume control process is performed on the waveform data (203). In this process, the volume envelope data includes a plurality of output sequences (output sequence for the right side of stereo,
Output information for the left side of the stereo, and output sequences for various effects (for example, reverb and chorus) are weighted at a ratio corresponding to each of them, so that volume information of a plurality of systems is obtained, and these are sequentially time-divided. Multiply the waveform data. By appropriately adjusting this ratio for each channel, it is possible to obtain a stereo effect or a sound image localization effect, and to control the type of effect and the degree of effect for the musical sound of the channel. Also, fade-in, fade-out and amplitude modulation (tremolo) can be performed in this process.

Subsequently, the tone data for the plurality of output sequences is generated by accumulating the waveform data of all the channels in a time division manner for each output sequence (204).
Then, effect processing is performed on the generated musical sound data (205). In the effect processing, a predetermined effect is added to the tone data of each output sequence for the effect, and then these are added to the tone data of the output sequence for the right side of the stereo and the tone data of the output sequence for the left side of the stereo. I do. In the course of this effect processing, as shown in FIG. 6, the address generator 113 outputs the write / read address signal DM based on the information from the waveform calculator 115.
A is generated and supplied to the delay RAM 109, and the storage area designated by the address signal DMA and the waveform calculation unit 115
By exchanging the musical sound data with the musical sound data, delay processing is performed on the musical sound data. The tone data generated and processed by the waveform calculation unit 115 in this manner is output from the sound source 108 via an interface 116 for a D / A (digital / analog) converter as shown in FIG. It is supplied to the sound system SS via the converter DAC.

Next, an operation example of the electronic musical instrument will be described.
FIG. 9 is a flowchart showing a main routine executed by the CPU 103. Predetermined initial settings (step S
After 1), the MIDI process (step S2) and the switch event process (step S3) are repeatedly executed. M
In the IDI processing, the performance information supplied to the MIDI 106 is written into an input buffer in the RAM 104, and note-on event processing, note-off event processing, and the like based on the performance information are performed.

In the switch event processing, the keyboard 1
Event processing is performed on various switches (tone color selection switch, effect selection switch, etc.) assigned to the predetermined key 02, and as part of the event processing, A / D switch event processing as shown in FIG. 10 is performed. The A / D switch arbitrarily switches between 0, 1 and 2 the number of external waveform data to be input to the sound source 108 among the two external waveform data that can be supplied to the A / D converter ADC. Switch. In this A / D switch event processing, if there is an ON event of the A / D switch,
The remainder obtained by dividing the sum of the value in the predetermined register ADX and 1 by 3 is newly stored in the register ADX (step S1).
1). That is, the value in the register ADX is initially A /
When there is an ON event of the D switch, it takes one of the values 0, 1, and 2 and thereafter, every time the ON event occurs, the value is changed from 0 to 1, from 1 to 2, from 2 to 0. Change. Subsequently, it is determined whether the value in the register ADX is 0, 1, or 2 (step S12).

If the value is 0, channels A and B (channel CH)
The sound generation in any two channels from 1 to CH16 is stopped (step S13). Subsequently, the digital conversion processing operation of the A / D converter ADC is turned off (step S14). And return. On the other hand, if the value is 1, the setting for reading the external waveform data from the A / D converter ADC is made in the area corresponding to the channel A in the control register 112 (specifically, in the channel A, After performing processing such as setting the signal designating the alias in FIG. 7 as the read address signal WMA, note-on is written in the area (step S15).
Subsequently, only the digital conversion processing operation of the A / D converter ADC for the external waveform data of the first system is turned on (step S16). And return. On the other hand, if the value is 2, in addition to the channel A, the control register 11
A / D converter A in the area corresponding to channel B in
The setting for reading the external waveform data from the DC is performed (step S17). Subsequently, the digital conversion operation of the A / D converter ADC for the external waveform data of the second system is also turned on (step S18). And return.

The channels A and B are shown in FIG.
As shown in (b), the channels after the time required to complete the digital conversion processing of the external waveform data of the first system and the external waveform data of the second system in the A / D converter ADC have elapsed, respectively. Is selected. At the timing of the channels A and B, an address signal WMA designating the alias in FIG. 7 is output from the address generator 113 of the sound source 108 based on the control information from the CPU 103. Thus, at this channel timing, the external waveform data from the A / D converter ADC is supplied to the waveform calculation unit 115 in the sound source 108 via the input control unit 109 and the waveform data input terminal Twin.

FIG. 11 shows an example of the note-on event processing of the MIDI processing of FIG. When the note-on of any MIDI channel is written in the input buffer in the RAM 104, the M
The note number and velocity of the IDI channel are read and stored in predetermined registers NN and VD, respectively (step S21). Next, it is determined whether the value in the register ADX is 0, 1, or 2 (step S22).

If the value is 0, all the channels CH1 to CH16 of the sound source 108 are set as channels for the waveform data from the waveform memory 110 (step S23). On the other hand, if the value is 1, fifteen channels other than the channel A are set as channels for waveform data from the waveform memory 110 (step S2).
4). On the other hand, if the value is 2, 14 channels other than the channels A and B are set as channels for waveform data from the waveform memory 110 (step S2).
5).

Subsequently, in step S23, 24 or 25
Is assigned within the range of the channel set by the note-on, and the register NN is stored in the area of the control register 112 corresponding to the assigned channel.
And a tone generation process based on the data in the VD.
Thereafter, note-on is written in the area (step S
26). And return.

At the channel timing to which the sound generation using the waveform data from the waveform memory 110 is assigned, the address signal WMA specifying the waveform data storage area of the waveform memory 110 is output from the address generator 113 of the sound source 108. . Thereby, at this channel timing, the waveform data from the waveform memory 110 is
Via the input control unit 109, the waveform data input terminal Twin
Is supplied to the waveform calculation unit 115 in the sound source 108 through the.

As described above, in this electronic musical instrument, whether or not external waveform data is to be input to the sound source 108 and how many of the two external waveform data to be input to the sound source 108 are determined by operating the keyboard 102. Can be arbitrarily switched. Furthermore, when some or all of the external waveform data of the system is not input to the tone generator 108, that is, when at least one of the channels A and B is not used for the external waveform data, normal tone generation is assigned to the channel. Therefore, the channels can be used effectively without waste. Then, the waveform memory 110
By controlling the address generator 113 to generate a read address signal for designating an area other than the waveform data storage area of the above, and by providing the input control section 109 having a simple circuit configuration, such external waveform data The sound source 108 can be input through the same input terminal as the input terminal for inputting the waveform data from the memory 110. Therefore, it is not necessary to provide an input terminal dedicated to the external waveform data in the sound source 108, so that the existing sound source LSI can be used without changing the design, and the size and cost of the sound source LSI can be reduced. . In addition, since it is not necessary to provide an interface for such an input terminal, it is possible to reduce the size and cost of the entire sound source system. By arranging the input port for the external waveform data in the memory space of the waveform memory 110 in this way, a part of the timing at which the waveform data from the waveform memory 110 should be input can be changed. Since it is used as needed, it is possible to eliminate waste in use.

In the channel to which the tone using the external waveform data is assigned, the tone generation processing by the waveform calculation unit 115 as described above is executed on the external waveform data. It is a matter of course that the contents of the processing can be designated by operating the keyboard 102 completely independently of the waveform data from the waveform memory 110. That is, for example,
The frequency characteristics are made different between the external waveform data and the waveform data from the waveform memory 110, the amplitude modulation is performed only on the external waveform data, and the output level from the left side of the stereo is increased for the waveform data from the waveform memory 110. On the other hand, for the external waveform data, the output level from the right side of the stereo is increased, and for the waveform data from the waveform memory 110, the specific gravity of the output sequence for reverb is increased. For example, it is possible to arbitrarily realize, for example, increasing the specific gravity of the output sequence for chorus. Then, the external waveform data subjected to the digital filter processing and the volume control processing is mixed with the waveform data from the waveform memory 110, added with an effect, and acoustically generated. As a result, the capability of the sound source 108 can be greatly expanded.

[Embodiment 4] FIG. 12 shows an embodiment in which the present invention is applied to a digital signal processor (hereinafter abbreviated as DSP). In FIG. 12, D
The SP 21 inputs the musical tone waveform data, and performs a predetermined number of steps (for example, 127 steps (each of these steps is indicated by ST1 to ST127 for convenience)) for one cycle of the input musical tone waveform data according to a built-in microprogram. Is performed to give a desired sound effect or sound effect (for example, various effects such as reverb and chorus) to the input musical tone waveform data, and is composed of, for example, an LSI. DS
In the course of the processing, P21 generates an address signal for writing or reading and supplies it to the RAM 22 for signal delay via the address output terminal 21b, and reads data from or to be written to the RAM 22. The output musical tone waveform data is output or input via the data input / output terminal 21a.

As described above, the DSP 21 has a delay RA
A data input / output terminal 21a for inputting / outputting tone waveform data to / from the M22 is provided. A dedicated data input terminal for inputting tone waveform data to be processed supplied from the outside, A dedicated data output terminal for transmitting the tone waveform data after the completion to the outside may not be provided. This is because an input / output control unit 23 is provided between the DSP 21 and the RAM 22 according to an embodiment of the present invention, and the input / output of external data and / or the external data This is because the output can be controlled. Thus, there is no need to provide a dedicated input terminal and output terminal for inputting and outputting data to and from the outside.
The data input / output pin configuration of the SI can be extremely simplified. In this case, the musical tone waveform data processed by the DSP 21 is output via the input / output control unit 23 and transmitted to a sound system (not shown) or transmitted to another DSP (not shown). I do. In the figure, input terminals for parameters, control data, and the like may be provided in the DSP 21 as necessary, but are not shown.

Of course, as another embodiment, the DSP 21
In the above, a signal data input terminal and an output terminal may be separately provided as necessary. Alternatively, as still another embodiment, the DSP 21 may not be provided with input terminals for parameters, control data, and the like, and these may be taken into the DSP 21 via the input / output control unit 23.

The internal basic configuration of the DSP described below may employ any known or unknown basic configuration, and the contents of the microprogram applied there are completely arbitrary. Good. However, in practicing the present invention, the DSP is provided with a configuration and / or a processing program relating to a function of generating an address signal related to the present invention in accordance with the following embodiments.

The tone waveform data and the address signal output from the DSP 21 through the terminals 21a and 21b,
The tone waveform data read from M22 is input to the input / output control unit 23. Also, tone waveform data to be DSP-processed externally supplied via the terminal 23a (for example, tone waveform data from a PCM sound source or tone waveform data obtained by sampling and analog / digital converting an analog audio signal currently being played) SD Is the input / output control unit 23
Is input to In a specific DSP operation step in which data is to be input / output to / from the RAM 22, the DSP 21 supplies an address signal AD specifying a storage area of the RAM 22.
Is output via a terminal 21b, and a read / write signal RW is output when the signal is at the H level, and a write instruction is issued when the signal is at the L level. In addition, DSP21
Is an address signal A indicating a predetermined value different from the address of the storage area of the RAM 22 in a specific DSP calculation step to which the tone waveform data SD given from the outside is to be input.
Through a terminal 21b, and outputs an H level read / write signal RW (read instruction, in other words, an input instruction to the DSP). In a specific DSP calculation step in which the processed tone waveform data SD 'is to be transmitted to the outside, an address signal B indicating a predetermined value different from the address of the storage area of the RAM 22 and the value of the signal A is applied to the terminal 21b. And outputs an L-level read / write signal RW (write instruction, in other words, an output instruction from the DSP).

In response to the DSP 21 outputting the address signal AD, the input / output controller 23 causes the DSP 21 and the RAM 22 to input and output musical tone waveform data through the data input / output terminal 21a. Further, the input / output control unit 23 causes the musical tone waveform data SD to be input to the DSP 21 through the data input / output terminal 21a in response to the DSP 21 outputting the address signal A. Further, in response to the DSP 21 outputting the address signal B, the input / output control unit 23 sends the data input / output terminal 2
Control is performed to output the processed tone waveform data SD ′ output through 1a to the outside from the output terminal 23b.

To explain a detailed example of the configuration of the input / output control unit 23, an address signal given from the DSP 21 via the output terminal 21b is input to the decoder 24. The decoder 24 outputs the address signal AD,
A and B are decoded, and when the signal is the signal AD, the signal AD is output from the multi-bit “X” output, and the 1-bit “Y” output and the “Z” output are respectively set to L.
(Low) level. On the other hand, when the applied address signal is the signal A, the decoder 24 sets the “Y” output to the H level and sets the “X” output and the “Z” output to the L level. When the applied address signal is signal B, the decoder 24 sets the “Z” output to the H level and sets the “X” output and the “Y” output to the L level.
The "X" output of the decoder 24 is input to the address input of the RAM 22, the "Y" output is input to the control terminal of the tri-state output buffer 25, and is inverted by the inverter 26. "Z" is input to the control terminal of the buffer 27.
The output is input to one input of an AND circuit 28. Therefore, the tristate output buffer 25 and the bidirectional tristate output buffer 27 are controlled such that when one is on, the other is off.

The tone waveform data output from the DSP 21 through the data input / output terminal 21a is input to the RAM 22 via the bidirectional tristate output buffer 27. Further, the musical tone waveform data read from the RAM 22 is output via the bidirectional tristate output buffer 27.
The data is input to the DSP 21 through the data input / output terminal 21a. At this time, the read / write signal RW from the DSP 21 is applied to the direction control input D of the bidirectional tristate output buffer 27 which is turned on by the L level of the Y output of the decoder 24, and is applied to the direction control input D. When the read / write signal RW is at an H level (ie, a read instruction), data is passed from the RAM 22 to the DSP 21, while the read / write signal RW applied to the direction control input D is at an L level (ie, a write instruction).
At this time, data is passed from the DSP 21 to the RAM 22.

The tone waveform data SD from the outside is stored in the DSP
At a predetermined calculation step timing every one calculation cycle of step 21 (for example, as shown in FIG.
(At the timing of (2)).
The output of the input latch circuit 31 is input to a tri-state output buffer 25, which is gate-controlled by the Y output of the decoder 24,
a and the bidirectional tristate output buffer 27. As described above, when the Y output of the decoder 24 is at the H level, the tristate output buffer 25 is turned on, the bidirectional tristate output buffer 27 is turned off, and the tone waveform data SD fetched from the outside into the input latch circuit 31 is output. The signal passes through the tristate output buffer 25 and is input to the DSP 21 via the bus 32 and the terminal 21a.

The other input of the AND circuit 28 has D
The read / write signal RW output from the SP 21 is input after being inverted by the inverter 29. AND circuit 2
The output of 8 is given to the control input L of the output latch circuit 30. The data input from the data input / output terminal 21a of the DSP 21 via the bidirectional bus 32 is input to the input of the output latch circuit 30, and when a high-level signal is applied to the control input L, it is input there. Latch the data. Data SD ′ latched by output latch circuit 30
Is connected to an appropriate next-stage device via the terminal 23b (for example, D
Output to the sound system via the / A converter).
That is, when attempting to output data output from the input / output terminal 21a of the DSP 21 through the terminal 23b as output data to the outside, the DSP 21 transmits the address signal B
At the same time, the read / write signal RW is set to L level, the output of the AND circuit 28 is set to H level, and the data output from the input / output terminal 21a is taken into the latch circuit 30.

Next, an example of the processing operation of the musical tone waveform data by the DSP 21 will be described based on the example of the operation timing chart of the input / output control unit 23 shown in FIG. 127 DSP operation steps ST1 to ST12 per operation cycle
7, the input latch 31 latches one sample of the musical tone waveform data SD from outside in a predetermined step ST1. The tone waveform data SD of one sample latched is
As shown in FIG. 5, the data is held by the latch circuit 31 during one operation cycle. The DSP 21 outputs the address signal A from the terminal 21b and outputs the H-level read / write signal RW at a predetermined step as the external data input timing among the steps ST1 to ST127 of one operation cycle. Output. Accordingly, in response to this step, the Y output of the decoder 24 becomes H
Level, the tri-state output buffer 25 is turned on, and external tone waveform data SD latched by the latch circuit 31 is transmitted to the tri-state output buffer 2.
5, DSP 2 through the data input / output terminal 21a.
1 is input. This external data input timing should preferably avoid step ST1, which is the data latch timing for the input latch circuit 31, and FIG. 13 shows an example of step ST2. Of course, DSP2
Other operation steps may be set as external data input timings, depending on how the program 1 is constructed.
The latch 31 is not limited to inputting external data only in one step per operation cycle, but may be performed in a plurality of steps as necessary.
May be input.

The DSP 21 outputs an address signal AD for designating an arbitrary write or read address of the RAM 22 through a terminal 21b in response to a plurality of appropriate steps other than the step of outputting the address signal A, and The read / write signal RW at the L or H level is output according to the write or read instruction. In response, the decoder 24 outputs an address designation output X, which is supplied to the RAM 22, and the output Y goes low, turning on the bidirectional tristate output buffer 27. If it is a read command, the data is read from the RAM 22 and the bidirectional tristate output buffer 27,
The read data is transmitted via the bus 32 and the terminal 21a.
Input to P21. On the other hand, if it is a write command, D
The data output from the SP 21 via the terminal 21a is input to the RAM 22 via the bus 32 and the bidirectional tri-state output buffer 27 and is written. In the data example of the bus 32 in FIG. 13, WD indicates write data to the RAM 22, and RD indicates read data from the RAM 22. That is, in this example, step ST
1 is a write timing, and step ST3 is a read timing. Of course, this is just an example,
In fact, it will depend on the contents of the microprogram in the DSP 21. In this manner, data input / output from the DSP 21 to the data input / output terminal 21a via the bidirectional bus 32 includes input data SD from outside, read data RD from the RAM 22, and write data WD to the RAM 22, As shown in FIG. 13, time-division multiplexing is performed for each calculation step. The DSP 21 receives the input data S according to the content of its own microprogram.
D and RD are appropriately used for calculation, and data that has been processed or is being processed is written in the RAM as write data WD.
22 and stored at the specified address.

The DSP 21 outputs an address signal B from the terminal 21b and outputs an L level read / write signal RW in response to an appropriate predetermined step other than the step of outputting the address signals A and AD. ,And,
The processed musical sound waveform data SD 'is output from the terminal 21a to the bus 32. Accordingly, in response to this step, the Z output of the decoder 24 becomes H level, the AND circuit 28 is turned on, and the latch circuit 30 latches the processed musical sound waveform data SD 'applied to the bus 32 from the terminal 21a. FIG. 13 shows an example in which this output latch timing is step ST127, but it is needless to say that the present invention is not limited to this. The tone waveform data SD 'latched by the latch circuit 30 is sent out through the output terminal 23b.

As described above, the tone waveform data SD to be processed supplied from the outside can be transferred to the delay RAM 22 and D without using a dedicated data input terminal or interface.
The data transmission / reception bus 32 with the SP 21 can be input to the DSP 21 using time division. Also, DSP2
1 is output to the outside without using a dedicated data output terminal or interface, and similarly using the data transmission / reception bus 32 between the delay RAM 22 and the DSP 21 in a time-sharing manner. can do. In the example of FIG. 12, the input / output control unit 23
Uses the data transmission / reception bus 32 between the delay RAM 22 and the DSP 21 in a time-sharing manner to both take in data SD from outside and output data SD ′ to outside, As another embodiment, either one may be performed. In that case, DSP2
In one, a data input terminal or a data output terminal for the other function would have to be provided as appropriate.

The DSP 21 is compatible with the existing LS for DSP.
An I-circuit may be used, in which case the data input terminal Tin and the data output terminal Tout will already be provided, respectively, as shown by the broken lines in FIG. Such existing data input terminal Tin and data output terminal Tou
t may be used as necessary,
It may not be used. For example, digital musical tone waveform data generated from a tone generator circuit inside the electronic musical instrument is taken into the DSP 21 from the data input terminal Tin, and is taken in from the outside via a sound waveform data sampled by a microphone or a data bus or a communication line. The sound waveform data may be fetched from the input terminal 23d into the DSP 21 via the input / output control unit 23.

The data SD 'latched by the output latch circuit 30 and output to the outside via the output terminal 23b is
The data is not limited to the processed data output from the terminal 21a of the DSP 21, but may be data read from the RAM 22 or data from the input latch circuit 31. In this case, the output condition of the decoder 24 is appropriately changed from that of the above example, and the operating condition of the AND circuit 28 is, of course, partially changed in design so as to be different from that of FIG. . That is, in short, RAM
When the data read from the RAM 22 is latched by the output latch circuit 30, a necessary read instruction is issued to the RAM 22, and the read data of the RAM 22 is input to the output latch circuit 30 through the bidirectional tristate output buffer 27, At this time, the design may be changed so that the H level latch instruction signal is output from the AND circuit 28. When the data from the input latch circuit 31 is passed through and latched by the output latch circuit 30, the output data of the input latch circuit 31 is output from the tristate output buffer 25.
, And input to the output latch circuit 30, and at this time, the design may be changed so that the AND circuit 28 outputs an H-level latch instruction signal.

[Fifth Embodiment] FIG.
7 shows another embodiment applied to P. In FIG. 14,
The two DSPs 41 and 43 are connected via the input / output control unit 45 according to the embodiment of the present invention, so that data processed by one DSP can be input to the other DSP. In the embodiment of FIG. 14, two pairs (a pair of the DSP 41 and the delay RAM 42 and a pair of the D
A pair of the SP 43 and the delay RAM 44) is provided, and an input / output control unit 45 is provided between both pairs. DS
To P41, processing target sound waveform data SD supplied from outside (PCM tone generator circuit or the like) is input. DSP41
Is provided with a data input / output terminal 41a for inputting / outputting data to / from the RAM 42.
There is no dedicated data output terminal for transmitting the sound waveform data SD ', which has been processed in the above, to the DSP 43. The DSP 43 is also provided with a data input / output terminal 43a for inputting and outputting data to and from the RAM 44, but is not provided with a dedicated data input terminal for inputting data to be processed from the DSP 41. Instead, the data on the bidirectional data bus 51 between one DSP 41 and the RAM 42 is transferred via the bus 52 to the input / output control unit 4.
5 dual port RAM 47 connected to one data input / output port, and the other DSP 43 and RAM 44
The data of the bidirectional data bus 53 is connected to the other data input / output port of the dual port RAM 47 of the input / output control unit 45 via the bus 54, and both DSPs 41, 41 are connected via the input / output control unit 45. Transmission and reception of data between 43 are controlled. The sound waveform data S that has been processed by the DSP 43
D '' is transmitted to the outside (such as a sound system).

In the step for inputting / outputting data to / from the RAM 22 based on a microprogram command, the DSP 41 outputs an address signal AD for designating a data storage area of the RAM 42 to an address data output terminal 41b.
And write / read command signal RW
Is given to the RAM 42. On the other hand, the sound waveform data SD '
In the step to be output from the SP 41, an address signal B indicating a predetermined value different from the address value of the data storage area of the RAM 42 is output via the address data output terminal 41b. Further, the DSP 43 outputs an address signal AD for designating a data storage area of the RAM 44 to an address data output terminal 4 in a step for inputting and outputting data to and from the RAM 44 based on a microprogram command.
3b and a write / read command signal RW is given to the RAM 44. On the other hand, sound waveform data SD '
In the step of inputting an address signal A, an address signal A indicating a predetermined value different from the address value of the data storage area of the RAM 44 is output via the address data output terminal 43b.

The address signals output from the address data output terminals 41b and 43b of the DSP 41 and the DSP 43 are input to the input control unit 45. Data input / output from the data input / output terminal 41a of the DSP 41 is input not only to the RAM 42 via the bidirectional data bus 51 but also to the input / output control unit 45 via the bus 52. The data input / output terminal 43a of the DSP 43 has
In addition to inputting and outputting data from the RAM 44 via the bidirectional data bus 53, data supplied from the input / output control unit 45 via the bus 54 is input. The input / output control unit 45 inputs the sound waveform data SD ′ that has been processed by the DSP 41 to the DSP 43 in response to the DSP 41 outputting the predetermined address signal B and the DSP 43 outputting the predetermined address signal A. This control is performed asynchronously via the dual port RAM 47.

The configuration of the input / output control unit 45 will be described in detail. The address signal output from the address data output terminal 41 b of the DSP 41 is input to the decoder 46.
The decoder 46 outputs the signal AD or B
And if the signal AD specifies the address area of the RAM 42, the signal AD is output from a plurality of bits of "X" output, and the 1-bit "Y" output is set to L level. The Y output of the decoder 46 is given as a write command signal W to the dual port RAM 47. When the signal is at the L level, the dual port RAM 47 is not accessed. On the other hand, the decoder 46
When the address signal output from the address data output terminal 41b of the SP 41 is a predetermined address signal B,
The write command signal W to be output from the “Y” output to the dual port RAM 47 is set to the H level, and the “X”
The output is set to L level for all bits. "X" of the decoder 46
The output signal is input to an address input of the RAM 42, and reads or writes a specified address. "X"
When all the bits are at L level, the RAM 42 is not accessed. When the write command signal W from the “Y” output of the decoder 46 is at the H level, data given to the bus 52 via the bus 51 from the data input / output terminal 41 a of the DSP 41 is written to the RAM 47. As an example, the dual port RAM 47 is a memory or a register that stores at least one word of waveform data, and the read command signal R given from the decoder 48 is set to H level.
At the time of the level, the data written through the bus 52 is read and output to the bus 54.

The address signal from the DSP 43 is input to the decoder 48. The decoder 48 decodes whether the address signal is the signal AD or A, and outputs the signal AD.
, The signal AD is output from a plurality of bits of “X” output, and the signal R of “Y” output is set to L level. On the other hand, when the signal is A, the read command signal R from the "Y" output to the dual port RAM 47 is set to the H level, and the "X" output is set to the L level for all the bits. The "X" output signal of the decoder 48 is input to the address input of the RAM 44 to read or write a specified address. When all bits of the "X" output are at the L level, the RAM 44 is not accessed. When the read command signal R from the “Y” output of the decoder 48 is at the H level, the data written in the RAM 47 from the DSP 41 via the bus 52 is read and output to the bus 54, and the DSP 43 via the bus 53. Data input / output terminal 43a
To enter.

Since the dual port RAM 47 functioning as an intermediate memory in the input / output control unit 45 is a dual port, even when the write command signal W and the read command signal R become H level at the same step timing, the read and write operations are not performed. Writing can be performed simultaneously. Therefore, the DSPs 41 and 43 can arbitrarily set the writing and reading steps for the dual port RAM 47 in the respective programs. That is, both DSPs 41 and 43 are dual port RAM4
7 can be accessed asynchronously. Note that the dual port RA is used as an intermediate memory in the input / output control unit 45.
Not limited to M47, a single port RAM or a register may be used. However, in this case, the write and read steps for the RAM 47 are set in the programs of the DSPs 41 and 43 so that the write command and the read command for the RAM 47 do not overlap at the same timing.

Next, as an example of the use example of FIG. 14, when the sound effect data of the delay system is applied to the input sound waveform data SD by cooperation of the DSPs 41 and 43, the DSP 41 and 43 are given RAM4 for each attached delay
An example in which a delay process corresponding to the sum of the individual delay times of 2, 44 can be performed will be described. FIG. 15 is a functional diagram showing an example of this use. One delay RAM 42 delays 10 sampling cycles, an intermediate RAM 47 delays one sampling cycle, and the other delay RAM 44 9
By delaying for the sampling period, a total of 2
An example in which a delay of 0 sampling cycle is performed is shown.
Such a process is advantageous because the sound signal can be subjected to a delay process in which the maximum possible delay time of each of the delay RAMs 42 and 44 is extended. That is, for example, assuming that each of the maximum possible delay times in each of the delay RAMs 42 and 44 is equivalent to 10 sampling periods, a maximum of "20 sampling periods" plus "intermediate RA"
Delay processing of the number of delay sampling cycles (for example, 1) of M47 ”can be performed.

In this case, the DSP 41 generates a write address signal AD in a predetermined step (for example, ST2), and writes the input data SD corresponding to the current sampling time to the specified address of the RAM 42. Then, in another step (eg, ST10), a read address signal AD offset by the number of addresses corresponding to the desired delay time (10 samples) is generated, and the data before the desired delay time (10 samples) is read from the RAM 42. Read, DS
The buffer is stored in P41. In a subsequent predetermined step (for example, ST12), a predetermined address signal B is generated, and the data SD 'stored in the buffer is output to the bus 51.
Take it into 47.

On the other hand, the DSP 43 generates a predetermined address signal A at a predetermined step (eg, ST2),
The storage data SD 'of the dual port RAM 47 is read out, and the DSP 43 is connected to the terminal 43a via the buses 54 and 53.
And store it in a buffer. In a subsequent predetermined step (eg, ST10), a write address signal AD is generated, and the data S stored in the buffer is stored.
D ′ is output to the bus 53, and the data SD ′ output to the bus 53 is written to the specified address of the RAM 44. Then, in another step (for example, ST12), a read address signal AD offset by the number of addresses corresponding to the desired delay time (9 samples) is generated, and the data before the desired delay time (9 samples) is read from the RAM 44. Read out, input to the DSP 43, and further output the data SD ''
Output as Thus, the delay RAM 4 of both DSPs
2, 44 and the intermediate RAM 47, for example, a total of 2
Data SD '' delayed by 0 sample periods is obtained. The design may be changed so that the intermediate RAM 47 can further delay the data by a plurality of sample periods.

Incidentally, the additive processing by the two DSP systems connected in series via the input / output control unit 45 is as follows.
The processing is not limited to the above-described delay processing, and may be other appropriate arithmetic processing. Furthermore, not limited to two DSP systems, a larger number of DSP systems (pairs of DSP and RAM) may be sequentially connected in series via the input / output control unit 45. That is, if the sound waveform data SD ″ that has been processed by the DSP 43 is input to yet another DSP using the same means as the input / output control unit 45, a serial connection of three or more DSPs By performing the processing, more advanced arithmetic processing and sound effect imparting processing can be performed.

Further, for example, one of the DSPs 41 and 43 may perform a delay-type sound effect applying process (for example, reverb), and the other may perform a modulation-type sound effect applying process (for example, chorus). Then, different acoustic effect imparting processes can be serially applied to the input sound waveform data SD to be processed. In addition, complex sound effect processing including long steps that cannot be executed by individual DSPs may be shared by the DSPs 41 and 43 and executed in series. Also, during one operation cycle,
After the data given from the DSP 41 to the DSP 43 via the input / output control unit 45 is appropriately processed by the DSP 43, the data is returned to the DSP 41 via the input / output control unit 45, and the DSP 41
And the DSP 4 via the input / output control unit 45
For example, data may be exchanged between the two DSPs to give complicated arithmetic processing.

As described above, the input DSP 41 performs delay processing and / or desired arithmetic processing on the input sound waveform data SD to be processed, and then performs delay processing and / or desired processing on the input DSP 41 in the subsequent DSP 43. Since the arithmetic processing is performed, the number of arithmetic processing steps of the DSP is apparently doubled to enhance the arithmetic function, and the delay RAM
, The data delay capability of the system can be extended. Moreover, this can be done without providing a dedicated data input / output terminal or interface for inputting / outputting data between the DSP 41 and the DSP 43, and using the DSP 4
This can be realized by using the existing bidirectional buses 51 and 53 provided between the RAMs 1 and 43 and the delay RAMs 42 and 44 in a time-division manner.

In the fourth and fifth embodiments, the present invention is applied to a DSP for effects. However, the present invention may be applied to a DSP used as a physical model sound source. In this case, data to be processed (for example, data indicating the magnitude of energy for vibrating the string model) may be input through an input / output terminal for a RAM for delay, or various parameters ( For example, parameters that control the damping characteristics and frequency characteristics of strings)
May be input through the input / output terminal for the delay RAM.

In each of the above embodiments, the input control unit and the input / output control unit are constituted by using the decoder and the tri-state output buffer. An input control unit or an input / output control unit that realizes equivalent functions may be configured. Also,
All or some of the technical configurations of the input control unit and the input / output control unit described in each of the above embodiments may be appropriately combined. In each of the above embodiments, the output control unit is not provided independently. However, the present invention is not limited to this. The output control function in the input / output control unit of FIG. 12 or FIG. It may be constituted as. For example, a portion excluding the buffer 25 and the latch circuit 31 in the input / output control unit 23 in FIG. 12 is configured as an output control unit, and this can be applied to a tone generator circuit and a DSP. Also, instead of the input control units 3 and 13 of FIGS. 1 and 3, the input / output control unit 23 of FIG.
It goes without saying that an input / output control unit similar to the above can be applied. Further, in each of the above embodiments, the present invention is applied to the PCM tone generator circuit or the DSP for processing the tone signal. However, the present invention is not limited to this. The present invention may be applied to an LSI circuit, and further may be applied to an LSI circuit that executes predetermined digital signal processing on appropriate data other than sound waveform data or tone signals.

In each of the above embodiments, an address signal indicating a value other than the storage area of the memory is generated as information indicating an external input or an external output, and this is decoded by a decoder so that each tri-state output buffer is output. However, the present invention is not limited to this, and it is also possible to control the switching of each tristate output buffer by generating a predetermined switching command signal composed of 1-bit data or the like. For example, in the case of FIG. 1, the 1-bit switching command signal corresponding to the output Y of the decoder 4 may be generated from the sound source 2.

In each of the above embodiments, the input control unit or the input / output control unit transmits the external input data to the sound source or the DS.
Input to the P and output the sound source or DSP output data to the outside. If necessary, input the external input data directly to the memory or input the data read from the memory directly to the outside. The design of the control unit or the input / output control unit may be changed.

Finally, some of the embodiments of the present invention will be summarized as follows. (1) A storage means for storing data and a data input terminal, a first address signal for designating a data storage area of the storage means, and a second address signal different from the first address signal And selectively output any of
Processing means for performing required processing on data input through the data input terminal;
In response to the output of the address signal, the data read from the storage unit based on the first address signal is input to the processing unit through the data input terminal, and the processing unit A digital signal processing device comprising: input control means for inputting data supplied from other than the storage means to the processing means through the data input terminal in response to outputting the address signal. (2) A storage means for storing data and a data output terminal, a first address signal for designating a data storage area of the storage means, and a second address signal different from the first address signal Processing means for selectively outputting any one of the following, and outputting required data from the data output terminal; and in response to the processing means outputting the first address signal, the first address signal Storing the data output from the data output terminal of the processing means in a storage area of the storage means specified based on
On the other hand, a digital signal processing device comprising: output control means for outputting, as output data, data output from the data output terminal of the processing means in response to the processing means outputting the second address signal. . (3) readable and writable storage means for storing data;
A data input / output terminal connected between the data input / output terminal of the storage means and a first address signal for specifying a data storage area of the storage means; and a first address signal different from the first address signal. Processing means for selectively outputting any of the second and third address signals; and the first means for outputting the first address signal in response to the processing means outputting the first address signal.
Data is written or read between a storage area of the storage means designated based on the address signal of the first step and the data input / output terminal of the processing means, while the processing means transmits the second address signal. In response to the output, the data supplied from other than the storage means is input to the processing means through the data input / output terminal, and further,
A digital signal processing device comprising: input / output control means for outputting data output from the data input / output terminal of the processing means as output data in response to the processing means outputting the third address signal. . (4) It has storage means for storing data, and terminal means for at least one of data input and output, and generates an address signal for designating a data storage area of the storage means. Data is written or read between the storage area of the storage means designated based on the terminal means and the terminal means, and required processing is performed on data input through the terminal means, or required processing is performed. Processing means for outputting the obtained data through the terminal means, at least one of a data input end and a data output end, and for the terminal means of the processing means,
Connecting means for selectively connecting at least one of the data input end and the data output end to the storage means; and the terminal means of the processing means being connected to at least one of the data input end and the data output end and the storage means Control means for controlling selective connection of said connection means in accordance with information indicating which connection is to be made. (5) A storage unit for storing data, and an address signal for specifying a data storage area of the storage unit are generated, and a data transfer wiring is connected to the storage area of the storage unit specified based on the address signal. Processing means for performing at least one of data writing and reading with interposition, an interrupt wire for at least one of data input and output, and connecting the interrupt wire to the data transfer wire, Digital signal processing comprising control means for performing at least one of inputting data of the interrupt wiring to the data transfer wiring at the time of interruption and outputting data of the data transfer wiring from the interrupt wiring. apparatus. (6) A plurality of pairs of the storage means and the processing means are provided, and the interrupt wires and the control means are provided for each pair, and at least two pairs of the interrupt wires are connected to each other to form one pair. 6. The digital signal processing device according to claim 5, wherein data output from the data transfer wiring via the interrupt wiring is input to the data transfer wiring via the other pair of interrupt wirings. (7) Repeating the execution of a storage means for storing data and a processing cycle comprising a plurality of time-division time slots, and in any one of the time-division time slots in each processing cycle, A processing means for generating an address signal to be specified, performing at least one of writing and reading of data to and from a storage area of the storage means specified based on the address signal; Having at least one of output terminals for outputting, interrupting a data wiring between the processing means and the storage means,
Input or output control means for controlling input or output of data between the input terminal or output terminal and the processing means or storage means, wherein at least one of time-division processing time slots in the processing means is provided. Using the input terminal or the output terminal to access the processing means or the storage means, and controlling the processing means to access the storage means in other time-division processing time slots. .

(8) The storage means is a waveform memory for storing sound waveform data, and the processing means is adapted to perform time-division sound wave data generation processing on a plurality of sound generation channels corresponding to the maximum number of sounds that can be simultaneously generated. The first address signal is generated in any one of the plurality of sound generation channels, and the second or third address signal is generated in any other channel. 4. A digital signal processing apparatus according to any one of the above items 1 to 3. (9) The input control means has a plurality of external input capturing units, and the processing means performs processing in a predetermined plurality of time-division processing time slots in a time-division manner. The second address signal having a plurality of different values is generated in correspondence with an arbitrary plurality of time slots among the slots, and the input control means outputs the second address signal from each of the external input capturing units according to each second address signal. 2. The digital signal processing device according to claim 1, wherein each of the data is fetched and time-divisionally input to a data input terminal of the processing means. (10) The processing means is a digital signal processor that repeatedly executes a program including a plurality of steps, and generates the first address signal in any one of the plurality of steps, 4. The digital signal processing device according to any one of claims 1 to 3, wherein the digital signal processing device generates the second address signal or the third address signal in a step. (11) The digital signal processing device according to any one of (1) to (10), wherein the processing unit performs a process of generating sound waveform data. (12) The digital signal processing apparatus according to any one of (1) to (10), wherein the processing unit performs a process for giving a sound effect to the input sound waveform data. (13) The digital signal processing device according to (1), further comprising at least the digital signal processing device according to (1) and the digital signal processing device according to (2). Data
2. A digital signal processing system according to claim 1, wherein said digital signal processing system is configured to input through said input control means. (14) At least two digital signal processing devices according to the above (3), wherein data output from the input / output control means in one of the digital signal processing devices is
A digital signal processing system wherein the input is made via the input / output control means in the other digital signal processing device.

[0092]

As described above, according to the present invention, in a digital signal processing apparatus including a processing means and a storage means, the processing means is provided in the processing means for accessing the storage means. It is possible to take in external data into the processing means or to output (external) output data of the processing means to a circuit other than the storage means by using an input or output terminal (data pin) of it can. Therefore, when the processing means is configured by an integrated circuit such as an LSI, it is possible to easily capture input data from outside the processing device or output data to the outside of the processing device without having to particularly increase the number of data pins. be able to.
Moreover, the switching control of whether to use the existing input or output terminal provided in the processing means for reading / writing data to / from the storage means, or to use external input data or to output data to the outside is performed by: Since this can be achieved by controlling the value of the address signal generated inside the processing means, it can be easily realized by simple control or program processing. Therefore, no special load is imposed on the circuit design and manufacture of the processing means (PCM reproduction control circuit, DSP, etc.), and the circuit can be used as it is, so that it is easy to use. An excellent effect such as an increase in the size and an increase in cost due to an increase in the number is not exhibited.

Further, according to the present invention, even if a processing means constituted by using an LSI circuit having an existing design concept having no special data pin for external input or external output is used, external input data can be fetched according to the present invention. Alternatively, since data output to the outside can be realized, the function can be extended, and various uses can be performed, thereby achieving an excellent effect that its applicability can be enhanced. Further, since it is easy to perform data input / output by connecting a plurality of pairs of processing means and storage means and connecting them to each other, it is possible to expand the functions of various sound effects or to use a plurality of different sound effects. , Or to extend the musical tone waveform synthesis processing function.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example in FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention according to a modification of FIG. 1;

FIG. 4 is an overall configuration block diagram of an electronic musical instrument employing the present invention.

FIG. 5 is a timing chart showing an operation example in FIG. 4;

FIG. 6 is a block diagram showing an example of the configuration of the sound source in FIG. 4;

FIG. 7 is a diagram showing an example of an area designated by a read address signal generated by the sound source of FIG. 4;

FIG. 8 is a view showing an example of an algorithm of a musical sound generation process executed by the sound source of FIG. 4;

FIG. 9 is a flowchart showing a main routine executed by the CPU of FIG. 4;

FIG. 10 is a flowchart showing an A / D switch event process executed by the CPU of FIG. 4;

FIG. 11 is an exemplary flowchart showing an example of a note-on event process executed by the CPU in FIG. 4;

FIG. 12 is a block diagram showing another embodiment of the present invention.

13 is a timing chart showing an operation example in FIG.

FIG. 14 is a block diagram showing still another embodiment of the present invention related to the modification of FIG. 12;

FIG. 15 is a functional block diagram showing a usage example of FIG. 14;

[Explanation of symbols]

 Reference Signs List 1 waveform memory 2,108 sound source 3,13,109 input control unit 4,14,24,46,48 decoder 5,7,25,118 tristate output buffer 6,26,29 inverter 8,30,31 latch circuit 11 OR circuit 21, 41, 43 DSP 22, 42, 44 Delay RAM 23, 45 Input / output control unit 27 Bidirectional tristate output buffer 47 Dual port RAM 101 Display 102 Keyboard 103 CPU 104 ROM 105 RAM 106 MIDI 107 Data and address Bus 110 Waveform memory 111 Delay RAM 112 Control register 113 Address generator 114 Envelope generator 115 Waveform calculator 116 Interface 117 Decoder

Claims (6)

(57) [Claims] 1. A storage means for storing waveform data, and a sampling period of the waveform data is stored in a plurality of time slots.
Processing that operates in multiple time slot periods divided into
Means for: (a) an address output terminal; and (b) at least one of data input and output.
A data terminal, in (c) the time slot period, generates an address signal for specifying a data storage area of the external of said memory means, prior
Address output means for outputting from the address output terminal; and (d) subjecting the waveform data input through the data terminal to required signal processing in the time slot cycle , or performing required signal processing on the supplied waveform data. a signal processing means for performing signal <br/> processing and outputs to the data terminal
And processing means formed of an integrated circuit, and provided outside of the processing means and adapted to capture waveform data.
At least comprising terminal means an input pin for, provided outside the processing unit, the data of said processing means
Against over data terminal, and connecting means for selectively connecting the said terminal means and said memory means, provided outside of said processing means, usually connected to the data terminal of said processing means to said memory means Control
And a predetermined time of the plurality of time slot periods.
The data terminal of the processing means with the terminal
Control means for controlling connection to the means . 2. A storage means for storing waveform data, wherein a sampling cycle of the waveform data is stored in a plurality of time slots.
Processing method that operates in multiple time slot periods divided into
And generating an address signal for designating a data storage area of the external storage means at each time slot period, and transferring data to and from the storage area of the storage means designated based on the address signal. When the use wiring by interposing performing at least one of data write and read
Both time slots over the sampling period
The operation allows the specified signal processing operation to be performed on the waveform data.
Performing a processing unit constituted by an integrated circuit, and interrupt wire for at least one of the data input and output, provided outside of said processing means, said plurality timeslots
At least one time slot period of the
Te, wherein connecting the interrupt wiring, and outputs the data of the interrupt wire data that and the data transfer wire input to the data transfer wire from該割included wire to the data transfer wire A digital signal processing device comprising control means for performing at least one of the above, wherein a plurality of pairs of the storage means and the processing means are provided, and the interrupt wiring and the control means are provided for each pair,
At least two pairs of the interrupt wires are connected to each other, and data output from one pair of data transfer wires via the interrupt wires is input to the data transfer wires via the other pair of interrupt wires. A digital signal processing device characterized in that: 3. A storage means for storing waveform data, and a processing cycle comprising a plurality of time division time slots is executed for each sampling cycle of the waveform data.
Performs predetermined signal processing on the supplied waveform data.
There, and each time division time slots each of said processing cycle
And generating an address signal individually, based on the address signal performing at least one of writing and reading the waveform data, and processing means configured by an integrated circuit, provided outside of said processing means, and at least one output terminal for outputting the input terminal and the waveform data for capturing waveform data, is provided outside of said processing means, to said processing means,
For the plurality of time slots of the processing cycle,
Usually a first for accessing the storage means respectively.
Generate an address, and
At least one time slot
A second terminal for accessing the output terminal or the output terminal.
Address setting for setting to generate address
Means provided outside of the processing means, and
Out of the plurality of time slots of the vehicle,
In the time slot in which the first address is generated,
Processing means for writing and writing waveform data to the storage means.
Performs at least hand fine read, said processing means first
In the time slot in which the address No. 2 is generated,
Means for writing to said output terminal and for reading from said input terminal;
The processing means and at least one of:
Between the storage means and the input terminal or the output terminal
A digital signal processing device comprising a connection means for controlling connection . 4. A storage means for storing waveform data, including at least the terminal manually input terminal for inputting the waveform data
And the sampling period of the waveform data are divided into multiple channels .
Processing means that operates on multiple time-shared channels
There are, (a) for each time-division channel, add each independently
Address generating means for generating an address signal; and (b) the address corresponding to each time-division channel.
Required signal for waveform data supplied according to signal
And a signal processing means for performing processing.
Processing means, and indicating whether to input waveform data from the input terminal
Indicating means for inputting the waveform data;
For the generating means, any one of the plurality of time division channels
Waveform data is output from the input terminal on one of the time division channels.
Set to generate a specific address for inputting data
And when instructed not to enter,
Input setting means for canceling a tone, sounding instruction means capable of instructing simultaneous sounding of a plurality of musical sounds, and sounding of a new musical sound being instructed by the sounding instruction means.
The specific address of the plurality of time-division channels.
Out of multiple time-division channels with no
Assign sound to any of the time-sharing channels
The new tone is assigned to the
In the time division channel assigned to
The waveform data necessary to generate the new tone
Generating a read address for reading from the storage means
A digital signal processing device comprising a sound generation control means for setting the above . 5. A storage means for storing waveform data, and a plurality of time division timers for each sampling period of the waveform data.
By executing the processing cycle consisting of timeslot
Performs predetermined signal processing on the supplied waveform data.
And each time-division time slot of the processing cycle
Address signals are generated individually, and based on the address signals.
At least one of writing and reading of waveform data
A processing means constituted by an integrated circuit, and waveform data provided outside the processing means.
Terminal means including at least a plurality of input terminals for selecting the number of inputs within a range equal to or less than the number of the input terminals.
Selecting means , provided outside the processing means, for the processing means,
For the plurality of time slots of the processing cycle,
Usually a first for accessing the storage means respectively.
Generating an address and using the plurality of time slots
In the selected number of time slots,
To access different input terminals of each input terminal
Generation address that is set to generate the second address of
Dress setting means , provided outside the processing means, and
Of the several time slots, the processing means
In the time slot in which the processing has occurred, the processing means
Less writing and reading of waveform data to and from the storage means
At least one of them, and said processing means
In the time slot in which the
Processing so as to read from the input terminal
Controlling the connection between the means and the storage means and the input terminal
Digital signal processing device with a connecting means for. 6. The input terminal or the output terminal,
At least one of the latches, and a waveform input from the input terminal for each sampling period.
Data or waveform data output to the output terminal
Latch in the latch and
Latch in the latch at the specified time slot of the
Input the input waveform data to the processing means, or
Converts the waveform data output from the processing means into the
Latch control means for controlling to latch on
A digital signal according to any one of claims 1, 3, 4, and 5.
No. processing unit.