JP3060649B2 - Semiconductor device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an element for converting a charge into a voltage.

[0002]

2. Description of the Related Art Semiconductor devices which accumulate and transfer information input such as incident light and electric signals in the form of electric charges and extract them as signals are used in a wide range of applications such as imaging devices and memories.
FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device, and FIGS.
(B) is a potential diagram for explaining the charge transfer.

This conventional example is an output section of a buried channel type two-phase drive charge transfer device. First, as shown in FIG. 3, a ground potential P of a ground potential formed in an N-type semiconductor substrate 1 fixed at a potential V _3. A first gate electrode 4 made of polycrystalline silicon on the surface of the type impurity well layer 2 with an insulating film 3 interposed therebetween, and a substrate and the first gate electrode 4 made of polycrystalline silicon with an insulating film 5 thereover; A second gate electrode 6 is formed. The charge transfer portion formed by the first gate electrode 4 and the second gate electrode 6 has an N-type charge transfer region 7 on the semiconductor surface immediately below the charge transfer portion for buried channel transfer.
In order to realize the charge transfer by driving by the two-phase clock, the P-type barrier region 8 for the potential barrier is formed with the second gate electrode 6 in the gap between the first gate electrodes 4 at intervals.
It is made on the semiconductor surface directly below.

The potential potential on the semiconductor surface is controlled by alternately applying opposite-phase clock voltages to φ ₁ and φ ₂ as a set of the first and second gate electrodes 4 and 6, respectively. The charge is transferred to the output circuit.
Also made of polycrystalline silicon through the insulating film 3 on the N-type charge transfer region 7 adjacent to the charge transfer section final stage, electric charge transferred to the output gate electrode 9 fixed to the potential V ₂ N-type floating diffusion layer 10 formed of an N-type impurity layer for converting the voltage to a voltage, and an N-type impurity layer 18 having an N-type floating diffusion layer 10 as a source adjacent thereto and fixed at a potential V _1. To the drain and φ _R made of polycrystalline silicon
A transistor whose gate is the clock application electrode 11 is
It is formed by forming an N-type impurity layer 12 on the semiconductor surface immediately below the gate. Further, an output transistor 13 for converting the charge signal into a voltage by connecting to the N-type floating diffusion layer 10 and extracting the voltage to the outside is provided.

In the conventional method of driving a semiconductor device having the above-described structure, first, a positive voltage is applied to the electrode 11 to
The potential of the floating diffusion layer 10 is set to the drain voltage V ₁ ,
Thereafter, the electrode 9 is set to the ground potential, and the N-type floating diffusion layer 10 is formed.
Disconnecting the electrical connection between the drain diffusion layer of the V ₁ voltage and. FIG. 4A shows the potential of the charge transfer unit in FIG. 3 in this state.

Here, the φ ₁ clock voltage is high and the φ ₂ clock voltage is low, and the electric charge 14 transferred from the left side of FIG. 4A is the first gate electrode for applying the φ ₁ clock. 4 is stored in the potential well of the N-type charge transfer region 7 below. Then phi _1, by reversing the voltage of phi ₂ clocks, increasing the low phi ₂ clock voltage a voltage of phi ₁ clock. FIG. 4B shows the potential in this state. As can be seen, the charge 14 stored in the potential well under the φ1 clock flows into the N-type floating diffusion layer 10 through the semiconductor surface immediately below the output gate electrode 9.

Assuming that the amount of charges thus transferred is Q and the capacitance of the N-type floating diffusion layer 10 is C, the potential ΔV of the N-type floating diffusion layer 8 before and after the charge flows in is ΔV = Q / C.

Therefore, if the potential difference ΔV is output via the output transistor 13, information stored in the conventional semiconductor device can be read.

Here, the capacitance C of the N-type floating diffusion layer 10 is
The capacitance between the N-type floating diffusion layer 10 and the P-type impurity well layer 2,
The capacitance is substantially determined by the sum of the capacitance between the N-type floating diffusion layer 10 and the output gate 9, the capacitance between the N-type floating diffusion layer 10 and the gate electrode (φ _R ), and the gate capacitance of the output transistor 13.

The sensitivity of the output signal is determined by the total capacitance C of the floating diffusion layer described above. That is, in order to obtain a high-sensitivity signal output, it is necessary to reduce the total capacitance of the floating diffusion layer.

[0011]

In the conventional charge transfer device described above, it is necessary to reduce the total capacitance C of the floating diffusion layer in order to obtain an output signal having high sensitivity to signal charges.
There is a limit to what can reduce the area of the floating diffusion layer, and there is a disadvantage that high-sensitivity signal output cannot be performed.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device having a charge transfer portion and a floating diffusion layer receiving a signal charge transferred from the charge transfer portion in an impurity region of a conductivity type opposite to that of the semiconductor substrate formed on the semiconductor substrate, the semiconductor substrate The floating diffusion layer potential is set to a reference potential by a potential.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of one embodiment of the present invention, and the same parts as those in the conventional example of FIG.

This embodiment is a charge transfer element having a charge transfer portion and an output portion in a ground potential P-type impurity well layer 2 formed on an N-type semiconductor substrate 1 to which a φ _R clock voltage is applied. Only the P-type impurity well layer 15 immediately below the floating diffusion layer 10 is made shallower than the P-type impurity well layer 2 in other regions. The insulating films 3, 5 and the gate electrodes 4, 6, 9,
The N-type charge transfer region 7, the P-type barrier region 8, and the output transistor 13 are the same as those in the related art.

In the driving method of the semiconductor device according to the present invention, the P-type impurity well 15 is depleted by applying a high positive voltage to the N-type semiconductor substrate 1 by a φ _R pulse. the potential of the N-type floating diffusion layer 10 is set to a potential corresponding to the depletion voltage of the P-type impurity well 15, a low voltage is applied by later phi _R pulses accordingly.

FIG. 2A shows the potential of the charge transfer section of FIG. 1 in this state.

Here, the φ ₁ clock is in a high state and the φ ₂ clock is in a low state, and the electric charge 14 transferred from the left side of FIG. 2A is the first gate electrode 4F for applying the φ ₁ clock.
Are stored in the potential well of the N-type charge transfer region 7. Next, the φ ₁ and φ ₂ clock voltages are reversed, and FIG.
As shown in (b), the charges 14 flow into the N-type floating diffusion layer 10. The charge Q thus transferred is converted into an output signal voltage by the N-type floating diffusion layer 10. And N
A positive high voltage is applied to the N-type semiconductor substrate 1 by a φ _R pulse, whereby the charge Q is drawn out to the N-type semiconductor substrate by a punch-through transistor operation, and the N-type floating diffusion layer 10 is formed.
Set the potential of.

[0018] The present invention made in this way, for example, in a semiconductor substrate of N-type resistivity 30 [Omega · cm, the surface density is created a P-type impurity well layer of ^{2 × 10 15 cm -3, 10} 16
The N-type floating diffusion layer having an impurity concentration of cm ^-3 or higher the P
By forming it in the n-type impurity well, φ _R
By applying 18 V as a pulse, the potential of the N-type floating diffusion layer can be set to 10 V, thereby realizing an output circuit section.

In the present invention described above, the gate electrode portion for setting the potential of the N-type floating diffusion layer, which is present in the conventional example, becomes unnecessary, and the capacitance of the N-type floating diffusion layer is greatly reduced. In the above embodiment, the N-type floating diffusion layer capacitance is 0.02 p
What was F could be reduced to 0.012 pF.

[0020]

As described above, according to the present invention, in order to reduce the total capacitance of the floating diffusion layer, the method of setting the potential of the floating diffusion layer is changed from a conventional MOS transistor with a gate electrode to a semiconductor substrate. Changing to a punch-through transistor has the effect of improving signal detection sensitivity.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a potential diagram for explaining charge transfer according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device.

FIG. 4 is a potential diagram for explaining charge transfer of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-type semiconductor substrate 2, 15 P-type impurity well 3, 5 Insulating film 4, 6, 9, 11 Gate electrode 10 N-type floating diffusion layer 13 Output transistor

Claims (2)

(57) [Claims] A second conductivity type impurity well provided in the first conductivity type semiconductor substrate; and a first conductivity type charge transfer region provided in the second conductivity type well, which are electrically insulated and adjacent to each other. A gate electrode row in which a plurality of paired gate electrodes composed of the first and second gate electrodes are arranged on the first conductivity type charge transfer region with an insulating film interposed therebetween;
A first conductivity type floating diffusion layer that is adjacent to the transfer region and receives the charge transferred from the first conductivity type charge transfer region;
A region of the second conductive type impurity well immediately below the first conductive type floating diffusion layer is made shallower than other well regions ,
By applying a pulse voltage to the conductive type semiconductor substrate,
The charge in the first conductivity type floating diffusion layer is transferred to the first conductivity type semiconductor.
To the body substrate and set the potential of the first conductivity type floating diffusion layer to
A semiconductor device characterized by being cut . 2. A second conductivity type impurity well provided in a first conductivity type semiconductor substrate and a first conductivity type charge transfer region provided in said second conductivity type well, which are electrically insulated and adjacent to each other. A gate electrode row in which a plurality of paired gate electrodes composed of the first and second gate electrodes are arranged on the first conductivity type charge transfer region with an insulating film interposed therebetween; and the first conductivity type charge transfer region. And a first conductivity type floating diffusion layer for receiving the charge transferred from the first conductivity type charge transfer region.
A method for driving a semiconductor device, wherein a region of the second conductivity type impurity well immediately below the first conductivity type floating diffusion layer is shallower than other well regions, wherein a predetermined voltage is applied to the semiconductor substrate to form the second conductivity type impurity diffusion well. After the conductivity type impurity well is depleted and the potential of the floating diffusion layer is set to a potential corresponding to the depletion voltage of the second conductivity type impurity well, a clock pulse is applied to the gate electrode row to form the floating diffusion layer. A method for driving a semiconductor device, comprising transferring electric charges to a layer.