JP3058070B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a power saving function.

[0001]

2. Description of the Related Art In recent years, personal computers having a battery inside and operating without an external power supply for notebook computers, sub-notebook personal computers, palmtop personal computers, and the like have become widespread. For this reason, attention has been focused on how to extend the operation time with a limited battery capacity.
As one of the techniques, a technique for reducing power consumption by power management has been proposed.

FIG. 5 shows a basic configuration of a power management unit in a conventional information processing apparatus.
This power management unit includes an address bus S7 connected to the bus interface logic B5.
I for peripheral devices mapped to I / O space above
/ O address value or peripheral device B
4 and detects peripheral devices connected to the address bus S7, such as fixed disks, floppy disks, display controllers, timers, by detecting that the device is in an active operating state. , An input / output controller, a memory for detecting that the memory and the like are in an operating state, a clock input terminal of the CPU, an output terminal of the active monitor unit B1, and a liquid crystal display (L
CD) or connected to a control input terminal such as a double-part auxiliary storage device to detect the operating state of the CPU or the use state of the peripheral device B4, and to increase or decrease the clock frequency and control the power supply in response to the state. By outputting the signal S8 of the power control, the power
It is composed of a control logic unit B3. Since these peripheral devices rely on a common battery for power, the operating time of the personal computer can be extended by using a power control unit that reduces the power consumption of the peripheral devices. The power control logic unit B3 operates as long as the active monitor unit B1 does not detect the active operation states of the CPU and peripheral devices, in this example, the presence or absence of an address or the presence or absence of a control signal during a certain period of time.
The peripheral device is gradually shifted from the normal operation state to the high power save state, and when the active operation state of the CPU and the peripheral device is detected, the peripheral device is shifted from the power save state to the normal operation state at once, and the power is saved.・
The power consumption of the entire system including the management unit has been reduced.

[0003]

However, in the conventional power management unit, when the active monitor section is already in the power save state, the active monitor section has the CP.
When the active state of the U or the peripheral device is detected, the state returns to the normal operation state in any low power consumption state. Therefore, for example, even if a key input is performed only to turn on the backlight of the LCD, the power consumption returns to the normal level. Thereafter, assuming that the power consumption during normal operation is 1 every time a fixed time elapses, about 1
/ 2 DOSE, about 1/3 SLEEP, about 1/4 S
USPEND and so on. Therefore, even when an active state that occurs sporadically is detected, the power is always returned to the normal state, and the power consumed during the transition to the low power consumption state after returning to the normal operation state is wasted. Become.

Accordingly, it is an object of the present invention to provide an information processing apparatus that reduces power consumption without returning to a normal state in an active state that occurs sporadically.

[0005]

SUMMARY OF THE INVENTION An information processing apparatus according to the present invention detects that a peripheral device is active, outputs a first normal operation request signal, and detects that the peripheral device is inactive . a monitor circuit that outputs a state transition request signal, the number of said first predetermined for a predetermined time
When it is detected that the normal operation request signal of
A normal operation request signal generating circuit for outputting the normal operation request signal, and a second state transition request signal when the first state transition request signal is input .
A power save signal generation circuit that generates a state transition request signal and stops the generation of the second state transition request signal when the second normal operation request signal is input; a state setting signal generating circuit wherein outputs a first control signal a second state transition request signal to output a second control signal by being inputted by the input, receives the first control signal It is provided with means for setting the clock to be supplied the frequency of the torque lock to supply to the peripheral device is set to a normal state receives the second control signal to said peripheral device to a frequency lower than the normal state Te It is characterized by.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a power supply according to a first embodiment of the present invention.
It is a block diagram of a management unit. Here, the same reference numerals are used for the same blocks as in FIG.

In this power management unit, a first active monitor B1 and a second active monitor B2 connected to an output terminal of a peripheral device are connected in series, and a first active monitor B1 is connected to the first active monitor B1. Is connected to the address bus S7. Further, the power control logic section B3 is connected to the second active monitor section B2.

The first active monitor section B1
Monitors the address bus S7 and the output signal S1 from the peripheral device to detect the active operation state of the peripheral device, and to the second active monitor section B2, the active state of the peripheral device. First normal operation request signal S output upon detection of
2 and a control signal generating circuit K2 for generating a first state transition request signal S3 output when an inactive state of the peripheral device is detected. Specifically, when detecting an address from a peripheral device, the control signal generation circuit K2 outputs the first normal operation request signal S2
And an inactive level is output as the first state transition request signal S3. When the inactive state of the peripheral device is detected, the inactive level is output as the first normal operation request signal S2. And an active level as the first state transition supply signal S3.

The second active monitor section B2 continuously outputs a plurality of times during a preset active monitor time by a first normal operation request signal S2 output from the control signal generation circuit K2. Only when a normal operation request is detected, the normal operation request signal generation circuit K4 that generates the second normal operation request signal S4, the first state transition request signal S3, and the second normal operation request signal S4 are generated. as an output enable signal, and is thus configured to the power save request signal generating circuit K7 for generating a second state transition request signal S5. Here, a plurality of second state transition request signals S5 are prepared, and an operation state, a normal operation state, DOSE, SLEEP, and SUSPE with different degrees of low power consumption are provided.
This is for controlling ND.

More specifically, the second normal state request signal S4
Is at the active level, the second state transition request signal S
5 is set to an inactive level. Next,
When the second normal state request signal S4 is at the inactive level, the second state transition request signal S5 is set to the active level, and the first state transition request signal S3 is set to a plurality of levels depending on the active / inactive level. One of the prepared second state transition request signals S5 is set to an active level.

Further, the power control logic section B3 receives the second normal operation request signal S4 or the state transition request signal S5 from the second active monitor section B2, and outputs a power save state in a plurality of stages. A state setting signal generating circuit K5 for outputting a control signal S8 for setting the normal operation state to the peripheral device. Here, although not shown, the control signal S
8 is input to a clock generation circuit, and the clock generation circuit selects and determines a frequency of a clock generated in response to the control signal S8 and a peripheral device to which the clock is supplied, thereby executing low power consumption. When the state setting signal generation circuit K5 detects the active level of the second normal operation request signal S4, it outputs a control signal S8 for bringing the peripheral device into the normal operation state, and outputs the second state transition request signal S4.
When the active level of 5 is detected, a control signal S8 for putting the peripheral device in the power saving state is output.

FIG. 2 shows waveforms indicating the operation of the power management unit. When the first normal operation request signal S2 becomes a high (active) level in one shot during the preset active monitoring time T1, that is, when the sporadic normal operation request signal S2 is generated, the normal operation is performed. The request signal generation circuit K4 keeps the second normal operation request signal S4 at the Low (inactive) level, and the second state transition request signal S5
Is generated by the power save request signal generation circuit K7 and becomes active, and the power control
It is supplied to the logic section B3. At this time, the second state transition request signal S5 is for maintaining a specific power save state for a time arbitrarily set in advance, and thereafter transiting to a power save state of a different level. . As a result, it is possible to realize efficient low power consumption without completely canceling the power save state for a normal operation request of a peripheral device that occurs sporadically.

Next, when the first normal operation request signal S2 continuously goes to the active level a plurality of times during the preset active monitor time T1, the second normal operation request signal generation circuit K4 causes the second normal operation request signal generation circuit K4 to output the second normal operation request signal S2. Normal operation request signal S4
Becomes active, the second state transition request signal S5
There thus generated to the power save request signal generating circuit K7, becomes inactive state, it is provided to power control logic unit B3. As a result, for a normal operation request of a peripheral device that occurs continuously (continuously), the power save state is completely released and a transition is made to the normal operation state.

Therefore, when the power save state is SUS
In the case of PEND, if there is a sporadic active state that turns on the LCD, that is, if there is a key input, SUS
A transition from PEND to SLEEP can be performed so that a transition from SUSPEND to a normal operation state can be performed when a continuous active state is detected. Therefore, after turning on the LCD, that is, after a lapse of a certain period of time after shifting to SLEEP, the state changes to SUSPEND, so that power consumption can be reduced.

Next, FIGS. 3 and 4 show a configuration diagram of a power management unit according to a second embodiment of the present invention and waveforms showing its operation.

Since the basic configuration is the same as that of the circuit shown in FIG. 1, the description of the same parts will be omitted. In this embodiment, a first control signal generation circuit K2 and a second control signal generation circuit K3 that generates a normal operation request signal S6 only when a predetermined operation state of a peripheral device is detected. ing. The normal operation request signal S6 is configured to be input to the power save signal generation circuit K7 and the state setting signal generation circuit K5 as the normal operation request signal S4 without passing through the normal operation request signal generation circuit K4. ing.

In the first embodiment, the first normal operation request signal S2 is set to a predetermined active monitor time T1.
The second normal operation request signal S4 changes to the active level and is input to the power control logic unit B3 only when the active level continuously changes to the active level a plurality of times during this period. When the operation request signal S2 is set to the active level in one shot during the preset active monitoring time T1, that is,
Even when the normal operation request signal S2 is generated sporadically, when the operation state of a predetermined peripheral device is detected, for example, when an address is input from an externally connected device, the normal operation request signal S6 The second normal operation request signal S4 changes to the active level and is supplied to the power control logic unit B3. The active level of the second normal operation request signal S4 is power level
The second state transition request signal S5 is also supplied to the power control logic unit B3 after being given to the save request signal generation circuit K7. As a result, even for sporadic normal operation requests,
If this is due to the detection of the operation state of a specific peripheral device, the power save state is released and the operation returns to the normal operation state. Also in the present embodiment, operations other than the above-described portions perform the same operations as in the first embodiment, so that it is possible to efficiently reduce power consumption.

As described above, the frequency and the clock of the clock supplied to the peripheral device commonly using the power supply are selectively supplied to the peripheral device, and the power is detected by the sporadic detection of the active level and the continuous detection of the active level. -A very efficient power save can be performed by setting the stage of return from the save state.

In the above-described embodiment, the address bus S7 and the signal S1 from the peripheral device have been described separately, but they may use a common address bus.
Furthermore, signals from externally connected printers and communication devices can also be detected by inputting them to this common address bus. This is particularly effective when the printer and the communication device share the power supply with the peripheral device. In this case, it is necessary to supply the control signal S8 to the printer and the communication device to control the operation state of these devices. Can also.

[0021]

As described above, according to the present invention, it is possible to set the stage of returning from the power save state by detecting the sporadic active level of the peripheral device and detecting the continuous active level. , And efficient power saving can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power management unit according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a power management unit according to a second embodiment of the present invention.

FIG. 4 is an operation waveform diagram according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional power management unit.

[Explanation of symbols]

 B1, B2 Active monitor section B3 Power control logic section K1 State detection circuit K2, K3 Control signal generation circuit K4 Normal operation request signal generation circuit K5 State setting signal generation circuit K6 State signal generation circuit K7 Power save request signal generation circuit

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/32

Claims (2)

(57) [Claims] A monitor circuit for detecting that a peripheral device is active, outputting a first normal operation request signal and detecting that the peripheral device is inactive, and outputting a first state transition request signal; A normal operation request signal generation circuit that outputs a second normal operation request signal when detecting that a predetermined number of the first normal operation request signals have been input during a time period, and the first state transition and a power save signal generating circuit for stopping the request signal is inputted to the generating a second state transition request signal a second normal operation request signal is input to the occurrence of the second state transition request signal, A state setting signal generating circuit that outputs a first control signal when the second normal operation request signal is input and outputs a second control signal when the second state transition request signal is input; , The first of said clock frequency lower than the normal state supplies receives a control signal to set the frequency of the torque lock be supplied to the peripheral device to a normal state receives the second control signal to said peripheral device An information processing apparatus comprising: 2. The monitor circuit according to claim 1,
Third normal operation when detecting the operating state of the peripheral device
A control signal generating circuit for outputting a request signal;
Of the normal operation request signal generation circuit
Without passing through as the second normal operation request signal.
A power save signal generating circuit and the state setting signal generating circuit;
2. A signal input to a circuit.
An information processing apparatus according to claim 1.