JP3057643B2 - Color image processing apparatus and method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a color image processing apparatus and method.

2. Description of the Related Art In a color copying machine, a full-color image is formed by sequentially printing images corresponding to four color materials of yellow, magenta, cyan, and black on one sheet of paper.

Then, a character portion of the document is identified, and a character-only process is performed on the character portion, thereby forming a sharp character.

[Problem to be Solved by the Invention] In the above-described color copying machine, a scaling process of an image is possible. For example, when performing a reduction process, it is realized by increasing the scanning speed of a document and thinning out images to be read.

When performing the scaling process, if attributes such as edges of the image are determined, the attributes cannot be obtained accurately, and the subsequent signal processing cannot be executed accurately.

 The present invention aims to solve the above-mentioned problems.

[Means for Enlarging the Problem] In order to achieve the above object, the present invention obtains a color image signal of the same size as the original when the operation unit instructs the original to change the magnification. Acquiring means for acquiring, from the color image signal, image area separating means for obtaining attribute information representing an attribute of a color image corresponding to the color image signal, and the color image according to the attribute information obtained by the image area separating means. And output means for performing a process according to the attribute on the color image signal corresponding to the attribute and outputting the processed color image signal.

Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

<Description of Apparatus (FIG. 1)> FIG. 1 is an external perspective view showing an image processing apparatus according to the present embodiment. Reference numeral 1-1 denotes a document reading unit and an image processing unit, which are located on a line which is an optical light receiving element for scanning a document.
It includes a CCD and various image processing units described later. The CCD according to the present embodiment is a three-line color image sensor constituted by various optical filters of R (red), G (green), and B (blue). Reference numeral 1-2 denotes an image output unit, which is an electrophotographic full color LBP (laser beam printer). Numeral 1-3 denotes a digitizer which also serves as a pressure plate for pressing the original, and is an area designating means for selecting various designated areas on the original by the designation pen 1-4. Reference numeral 1-5 denotes an operation unit, which performs a document reading start instruction, selection of the number of copies, various kinds of editing, selection of image processing, and the like.

<Description of Configuration (FIGS. 2 to 10)> Next, the document reading unit and the image processing unit 1-
1 will be described below with reference to the block diagram shown in FIG.

A document 2-1 is placed below the document pressure plate 1-3 in FIG. Reference numeral 3-2 denotes an optical lens which forms a document image on a CCD. 2-3 is a CCD, R (red), G
(Green) and B (blue) are composed of three lines of CCDs each having an optical filter.

Here, the number of light receiving sections of the CCD and one line is constituted by the number of readings in one direction of the document table, for example, the entire x direction.
If x direction is 30cm and 16pel is read, 30 × 160 = 4800
It is composed of at least two light receiving units. When scanning an original, the imaging lens 2-2 and CCD 2-3 are scanned in the y direction to read the original.

The document information is converted into analog electric signals by the CCD 2-3, and the converted various R, G, B signals are output to the analog signal processing unit 2-4. Reference numeral 2-4 denotes an analog signal processing unit which performs sample / hold, dark level correction dynamic range control, and the like for each color, and then performs A / D conversion.
It performs conversion (analog-to-digital conversion) and outputs R, G, B signals to the input image processing unit 2-5. Reference numeral 2-5 denotes an input image processing unit, which performs shading correction for correcting the light receiving sensitivity of each light receiving unit of the CCD for each of the input R, G, and B colors. Output.

Reference numeral 2-6 denotes an image processing unit, which is an image processing unit for extracting a character portion or a black character portion which is the center of the present embodiment, a bit map memory for storing a determination result of separation, and an edge emphasizing circuit according to the determination result. Control unit, a masking circuit corresponding to the output color characteristics of the LBP, which is the output device of the CCD color filter, an editing circuit such as moving and trimming, and a toner amount of the output unit from the R, G, B color information. Corresponding C (cyan), M (magenta), Y (yellow), B
_{It is} composed of a log conversion circuit for converting to _K (black).

Above C, M, Y, B _K each concentration information is output to the printer unit 2-7, is copied to by connexion paper output device such as a full-color LBP. 2-8 is a control unit (CPU) for controlling various processes, and 2-9 is an operation unit corresponding to 1-3 and 1-5 shown in FIG.

Next, details of the image area determination unit and the image processing unit 2-6 that performs processing according to the determination result in the present embodiment will be described below with reference to FIG.

In the figure, denotes an image information input unit and denotes an output unit, both of which are multi-valued image signals. The image signal is R,
Although there are three colors of G and B, only one color or one circuit is shown for the path of the image signal and various processing units for simplicity, and description will be added as necessary.

First, the more input image information is stored in the FIFO memory 3-
Delayed by one line for each color by 6,3-7, 3 × 3
The edge extraction unit 3-9 forms a 3 × 3 pixel matrix. Then, Laplacian, which is a spatial filter described later, is applied to extract an edge portion of a character or the like. In addition, the edge extraction unit 3-9 uses G (green) 1 to reduce the scale.
It is configured to extract by color.

Next, details of the edge extraction unit 3-9 will be described with reference to FIGS.

FIG. 4 is a detailed block diagram of the edge extraction unit 3-9, and FIG. 5 is a Laplacian operation unit showing details of the 3 × 3 Laplacian unit 4-1.

G1, G2, and G3 shown in FIG. 4 and FIG. 5 correspond to FIG. 3, respectively, and are green image information. The input image information is stored in each clip flop (FF) 5-1.
Is delayed by the video clock (VCK) at ~ 5-6,
A 3 × 3 matrix is configured. A multiplier 5-7 multiplies the target pixel output from the FF 5-3 by eight. Reference numeral 5-8 denotes an operation unit which performs an operation represented by the following equation from the input data A to I.

E− (A + B + C + D + F + G + H + I) The operation result of the operation unit 5-8 is input to A of the comparison circuit 4-4. 4-3 is a logical sum (hereinafter OR) circuit.
The CPU writes fixed density information in F.4-2. This fixed density information has the meaning of the slice level for edge extraction. The information of A> B is output as a binary value from the comparison circuit 4-4.

That is, if the fixed density information is set to an appropriate value (for example, about 1/2 of the maximum value of the image information), the edge extraction unit 3-9 in FIG. Is output.

In addition, R, G,
Each pixel information of B is input to the black determination unit 3-15 to generate binary information indicating whether or not the pixel is black. This black determination unit 3-15
M, and stores data for outputting a black determination signal when the ratios of R, G, and B are substantially equal.

Therefore, in the present embodiment, the above-described edge extraction unit 3-
9. Image area separation information is created by the black determination unit 3-15.

Reference numeral 3-3 denotes a CPU, reference numeral 3-4 denotes a RAM which is a work area of the CPU 3-3, and reference numeral 3-5 denotes a ROM which stores processing procedures (programs) of the CPU 3-3. Reference numeral 3-2 denotes an operation unit, which corresponds to 1-5 in FIG. 1, and 3-1 denotes a digitizer, which corresponds to 1-3 and 1-4. 3-13 is CPU3
Reference numeral 3 denotes an address bus, and reference numeral 3-14 denotes a data bus of the CPU 3-3.

Each of the R, G, and B image information delayed by one line by the FIFO 3-6 is enlarged and reduced by the scaling circuit 3-8 in accordance with an instruction from the operation unit 3-2. The magnification circuit 3-8
The details will be described with reference to the block diagram shown in FIG.

FIG. 6 shows only one color.
−6, 6−10, and 6−11 are each composed of three circuits for three colors.

In brief, the configuration is realized by thinning out image information in the RAM 6-6 and writing it out in the RAM 6-6, and enlarging it by overlappingly reading out image information. The RAM 6-6 has a capacity of two lines for each color and is used by switching the memory area so that the write address and the read address do not alternately overlap, so that the image data is delayed by one line in the RAM 6-6. Will do. For this purpose, the FIFO3-6 shown in FIG.
In addition, the line delay relationship is determined by the edge extraction unit 3 described above.
9, which matches the black judgment unit 3-15.

VCK is an abbreviation of VIDEO CLOCK, and the CPU stores the write address counter 6-
2. Write the enable signal of the read address counter 6-3. The CLOCK signal is the clock from which the frequency is divided by 4 to create VCK. Then, when the image scanning is started, the FIFO 6−
An enable signal corresponding to the scaling factor is output from one memory, and each of the counters 6-2 and 6-3 starts counting. The selector 6-5 switches the write address and the read address at twice the frequency of VCK.
Is switched to the write cycle on the LOW side and to the read cycle on the HIGH side. The memory area of the RAM 6-6 for read addresses and write addresses is switched alternately by the MSB signal from the write address counter 6-2 and the signal inverted by the inverter circuit 6-4.

6-10 is a buffer circuit having an output control function, 6-11 is FF, and 6-12 is logical product (AND).
Circuit), and controls the image data and the RAM 6-6 together with the CS terminal and the WR terminal of the RAM 6-6.

The bit map memory 3-10 shown in FIG. 3 receives the area designation information from the CPU 3-3 together with the information from the edge extraction unit 3-9 and the black judgment unit 3-15. In this area designation information, a region is designated by the digitizer 3-1 and the processing content of the region is designated by the operation unit 3-2.

In this embodiment, the processing contents are not described in detail, but are processing such as trimming, masking or character area, black character area, photograph area, movement, color conversion, and synthesis. If the data width is, for example, 8 bits, the 6-bit, 6-type processing area signal obtained by subtracting the output information of the edge extracting unit 3-9 and the black determining unit 3-15 is stored in the bitmap memory 3-10. Will be. However,
In the present embodiment, in order to improve the erroneous determination of 3-9, 3-15,
The area is specified by the digitizer, and the bit map memory 3-
The signals in the character area and the black character area are always used as the signals stored in 10.

Next, the bitmap memory 3-10 will be described with reference to FIG.

In the figure, an input signal of the D ₀ input from edge extraction unit 3-9, D ₁ is the output signal from the black determination unit 3-15. Hereinafter, the operation will be described.

First, when performing image area separation, at the time of the first document reading,
Image areas are separated by the edge extraction unit 3-9 and the black determination unit 3-15, and written into the bit map memory 7-1. The address control of the memory in this case will be described later.
The image area separation information is written to the bitmap memory 7-1 with a size larger than the unit image size of the image processing unit 2-6 determined by the resolution of D2-3 and the resolution of the printer unit 2-7.
This is for the purpose of saving memory, and if a resolution that does not substantially cause a problem, for example, if a unit area is used as a 1 mm × 1 mm size, an “A4” size document can be configured with 64K RAM.

Next, the CPU reads the image area separation information through the OR circuit 7-3 and the buffer circuit 7-2 with output control, and writes the image area separation information into the bit map memory 7-1 together with the other area signals AR to AR7. At this time, the area information to be written is the information specified by the digitizer 1-3. The change point of the specified area and the type of the area are stored in the RAM 3-4, and the bit map is created based on the information. Information is written into the memory 7-1. Also,
In order to reduce erroneous determinations with respect to the image area separation signals D ₀ and D ₁ , an area can be specified, and AND or OR information of the area specification information and the image area separation information is written.

However, in a case where copying is performed by one operation without performing image area separation, for example, in a case of hurry, information is written in D ₀ and D ₁ similarly to other area signals.

Next, the details of the address counter section 3-11 in FIG. 3 will be described with reference to FIG.

In the figure, VCK2 is a frequency-divided signal of the image signal VCK, and 1
It is a signal corresponding to mm x 1 mm size. FIFO circuit 8-1
Controls the enable signal of the address counter 8-2, and when performing image area separation, the selector 8-3 selects the A input. When the CPU writes the area signal to the bit map memory, the B input address bus (ADRESS BU) is used.
S) will be selected. However, when zooming,
The image signal is scaled by the scaling circuit 3-8 described above, and the area signal is converted to an address counter unit 3 according to the scaling factor.
-11 is controlled and written into the 3-10 bit map memory. By using a system that separates the image area in the first scan,
There is an advantage that the image area separation at the time of zooming can be performed at the same resolution. For example, at the time of reduction, the moving speed of the optical system is increased, and image information is thinned out, so that accurate edge extraction is difficult to perform. Accurate image area separation can be performed even in the case of double time.

Next, the details of the image processing circuit 3-12 for performing control using the area signal and the image area separation signal stored in the bit map memory 3-10 in FIG. 3 will be described with reference to FIG.

In the figure, denotes an image input unit, denotes an image output unit, and denotes a control signal from the bit map memory 3-10. In the present embodiment, the edge enhancement circuit 9-
4 is shown. This is based on the image area separation information.
Applying strong edge emphasis has the effect of reproducing only the black characters in the form of a sharp.If the original is a mixture of a color photograph and its description, the black characters should be in the form of a sharp, and the image should be subjected to soft image processing. There are advantages that can be.

First, the image signals input from FIFOs 9-1 and 9-2
2 × 3 pixel edge enhancement circuit 9-4
Form a 3 × 3 pixel matrix, and Laplacian can be applied. The delay circuit 9-3 is provided with an edge emphasis circuit 9
-4 is a circuit for absorbing the delay in the selector 9-5.
This is to match the timing of input to the. Also,
When the selector 9-5 switches the image signal in accordance with the input image area separation signal, good edge emphasis can be performed only on the black character portion.

<Description of Processing Procedure (FIGS. 11A and 11B)> Next, the processing procedure in this embodiment will be described below with reference to the flowcharts shown in FIGS. 11A and 11B.

First, in step S1, when the magnification is set by the operation unit 3-2, an image area separation signal is written to the bit map memory 3-10 according to the magnification. Next, step S2
Is used to select whether or not to perform image area separation. In this embodiment, when image area separation is performed, original scanning is performed twice, but when not performed, copying is completed by one scanning, so that either one can be selected depending on the degree of urgency.

If image area separation is to be performed, an image area separation type is selected in step S3. As described above, in this embodiment,
Edge extraction and black determination are performed. For example, when a black character is to be extracted, both are selected. Also,
Although color conversion is shown in another embodiment described later,
Color conversion and the like can also be selected. Next, in step S4,
Whether or not to specify an area is selected. As a type of this area designation, in order to reduce erroneous determination of black character extraction,
A rough black character portion may be specified, or image processing such as trimming, masking, or moving may be instructed regardless of image area separation.

When the area is designated, the process proceeds to step S5, and the area designation is input. Then, the processing contents are set in the following step S6. Next, when the same processing area as the image area separation is specified in the area specification, it is selected whether to perform AND and OR of the signal of the area specification and the image area separation. For example, if the image area separation of all black characters is performed, if processing other than characters does not become desired as a result of erroneous determination, roughly specify the area of the character part to be processed and perform AND operation.
In the case of color conversion shown in another embodiment, if an area is specified other than the part where normal color determination is made,
Select

Next, in step S8, it is selected whether or not another area is designated. If the area designation is completed, copying is started in step S9, image area separation is performed by pre-scanning in the next step S10, and an image area separation signal corresponding to the magnification is written in the bit map memory 3-10, and step S11 is performed. Scan for copying according to the magnification. However, when the image area separation is performed and the area designation is not performed, the above-described steps S4 to S4 are performed.
Proceeding to S9, the above processing is performed, and the copying is completed.

On the other hand, if image area separation is not to be performed, the process proceeds from step S2 to step S12 to select whether or not to specify an area. If so, the process proceeds to step S13, where the process is performed by designating an area, and the process content is set in step S14. Then, in step S15, a selection is made as to whether or not there is another area designation. When the area designation is completed, copying is started in step S16. Thereafter, in step S17, copying is completed by one scan. However, when the image area separation is not performed and the area designation is not performed, the processing proceeds from step S12 to step S16, the above processing is executed, and the copying is completed by one scan.

[Other Embodiments] In the above-described embodiment, the edge extraction unit 3-
9 and the black determination unit 3-15 have been described as examples, but a color conversion circuit will be described as another embodiment.

As for the color determination of color conversion, a method of performing smoothing on pixel information in order to reduce erroneous determination is often used, but, for example, good interpolation processing is not performed on image information at the time of enlargement. In some cases, in particular, the image cannot be completely removed by smoothing processing such as image stains and noise components, resulting in erroneous color determination.

On the other hand, at the time of the first manuscript operation, the color judgment is performed at the same speed at the same time as the separation of the other image areas, and the result is stored in the bit map memory according to the scaling ratio, so that even at the time of scaling, Good color judgment can be performed.

The circuit configuration is basically the same as that of FIG. 3, and a color conversion circuit is also provided in the image processing unit 3-12.
-9, the color determination unit is replaced with the black determination unit 3-15.

The configuration of the change determination circuit in this embodiment will be described below with reference to FIG.

In the figure, reference numeral 10-1 denotes a CPU, which controls a color determination circuit. In this block diagram, peripheral circuits of the CPU, operation units, and the like are omitted. R, G, and B are red, green, and blue image signals, respectively, and are binary information of a color determination result. Referring to-intensity, the upper and lower limits of the color determination ranges for pre-intensity, each slice level 2 (10-4) R _H, the slice level 1 (10-2)
_Is set to _RL .

Then, the comparators 10-3 and 10-5 compare the image information with the slice level, and when the image information is R, output a determination signal of _RH > R and a determination signal of _RL <R, respectively, and an AND circuit 10−
According to No. 9, _RH >R> _RL is determined. In a similar manner, it is possible to make a determination for green and blue, and 10-6 and 10-7 correspond to a determination circuit.

As described above, the R, G, and B pixel information is determined, and the AND circuit 10-8 is determined.
If all three colors are within the range, they will be output as color conversion signals.

[Advantage of the Invention] According to the present invention, when an instruction for scaling processing on a document is given from an operation unit, an acquisition unit for acquiring a color image signal of the same size as the document, ,
An image area separating unit that obtains attribute information representing an attribute of a color image corresponding to the color image signal, and a color image signal corresponding to the color image according to the attribute according to the attribute information obtained by the image area separating unit. Output means for performing and outputting the processed image, it is possible to obtain the attribute of the color image with high accuracy, and then perform the process corresponding to the attribute to the color image signal corresponding to the color image.

[Brief description of the drawings]

FIG. 1 is a diagram showing the appearance of an image processing apparatus according to the present embodiment, FIG. 2 is a schematic block diagram showing the configuration of the image processing apparatus according to the present embodiment, and FIG. FIG. 4 is a block diagram showing details of an edge extracting unit in this embodiment. FIG. 5 is a block diagram showing details of a Laplacian unit in this embodiment. FIG. 6 is a block diagram showing this embodiment. FIG. 7 is a block diagram showing details of a bit map memory unit in this embodiment, FIG. 8 is a block diagram showing details of an address counter unit in this embodiment, FIG. 9 is a block diagram showing details of an image processing circuit in this embodiment, FIG. 10 is a block diagram showing a color judgment circuit in another embodiment, and FIGS. 11A and 11B are diagrams in this embodiment. FIG. 12 is a flowchart showing a processing procedure, and FIG. 12 is a block diagram of a conventional example. . In the figure, 3-1 ... digitizer, 3-2 ... operation unit, 3
-3 ... CPU, 3-4 ... RAM, 3-5 ... ROM, 3-8
... Magnification circuit, 3-9... Edge extraction unit, 3-10... Bit map memory unit, 3-11.
3-12: an image processing unit; 3-15: an address black determination unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 H04N 1/387-1/393

Claims (2)

(57) [Claims] An acquiring unit for acquiring a color image signal of the same size as that of the original when an instruction for scaling processing on the original is issued from an operation unit; and converting the color image signal to the color image signal. An image area separating unit that obtains attribute information representing an attribute of the corresponding color image, and performs a process according to the attribute on a color image signal corresponding to the color image according to the attribute information obtained by the image area separating unit, and outputs the processed image. A color image processing apparatus comprising: 2. An acquiring step of acquiring a color image signal of the same size of the original when an instruction of a scaling process for the original is given from an operation unit; and converting the color image signal to the color image signal. An image area separation step of obtaining attribute information representing the attribute of the corresponding color image, and performing a process according to the attribute on a color image signal corresponding to the color image according to the attribute information obtained in the image area separation step, and outputting the processed image. And a color image processing method.