JP3055237B2 - Liquid crystal display panel and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel and a method for manufacturing the same, and more particularly, to a structure technology for a signal line.

[0002]

2. Description of the Related Art A liquid crystal display panel, which is a typical flat panel display, includes a transparent substrate on one side on which a common electrode is formed and a transparent substrate (matrix array) on the other side on which a large number of pixel electrodes are formed. Liquid crystal is sealed between the pixel electrodes, and the potential applied between the common electrode and each pixel electrode is controlled to change the alignment state of the liquid crystal in each pixel region. A typical one is an active matrix system in which a predetermined signal potential is applied to each pixel electrode using a TFT (thin film transistor) or the like. An example of the structure of a matrix array used for this is shown in FIG. In this figure, a polycrystalline silicon layer 52 is formed on the front side of a glass substrate 51, and the polycrystalline silicon layer 52 has a gate electrode 5 on a gate oxide film 54.
5 as a mask, the channel region 53
The source region 56 and the drain region 57 are formed so as to be self-aligned in a region except for. An interlayer insulating film 59 is deposited on the surface side of the TFT 58 having this structure, and an aluminum layer 60 forming a signal line is conductively connected to the source region 56 through the connection hole 59a. The pixel electrode 61 made of ITO is conductively connected to the drain region 57 through one connection hole 59b. In the pixel region having this configuration, when a drive potential from a gate line is applied to the gate layer 55 in a state where a predetermined signal potential is applied to the source region 56 via the aluminum layer 60, , A predetermined signal potential is applied to the pixel electrode 61. Thereby, the pixel electrode 6
An electric potential is applied to the liquid crystal sealed between the liquid crystal 1 and the common electrode opposed thereto, and the alignment state of the liquid crystal changes.

[0003]

In the liquid crystal display panel having such a structure, the aluminum electrode 6 constituting the signal line is provided.
If a disconnection state occurs at 0 and a display operation cannot be performed in all the pixel areas to which a signal potential is to be applied, a line defect of display occurs on the liquid crystal display panel. Such a disconnection is caused by, for example, a break in a step portion generated at a step portion or generation of flakes at the time of forming the aluminum layer 60 by sputtering. In particular, when the size of the liquid crystal display panel is increased and the number of pixels is increased, there is a problem that the probability of the presence of a broken portion is increased, the yield is reduced, and the production cost is increased.

In order to prevent the occurrence of display line defects, for example, adoption of a redundant wiring structure (a plurality of bus lines) provided with a plurality of wirings has been studied. However, when a redundant wiring structure using a plurality of wiring layers is adopted, a region (aperture ratio) functioning as a pixel becomes narrow depending on the arrangement position, which causes a decrease in display quality of a liquid crystal display panel and a narrow wiring interval. As a result, new problems such as a short circuit between the wirings easily occur. Originally, the redundant wiring structure does not expect an improvement in display quality, but is a passive means for preventing abnormalities from becoming apparent.On the contrary, a structure in which display quality or reliability is reduced can be adopted. Not something.

Here, the inventor of the present application proposes to realize a redundant wiring structure without sacrificing an aperture ratio and display quality by using a multilayer structure of signal lines. As this multilayer structure, first, as a possible structure, after forming a lower aluminum layer by patterning an aluminum layer formed by sputtering, aluminum is again formed by sputtering and patterning, and an upper layer is formed on the lower aluminum layer. There is a signal line that overlaps the aluminum layer on the side. If this structure is adopted, each aluminum layer is patterned in a separate process, so even if there is a defect in each resist mask used for it, disconnection does not occur unless the respective defects overlap. Become. However, as long as the same material is used, if there is a defect in the resist mask for patterning the upper aluminum layer, in the etching process, the lower aluminum layer is also etched from the defect. As a result, it is impossible to completely prevent a disconnection accident. In contrast,
A method of interposing a silicon oxide film or the like between each aluminum layer is also conceivable, but a process for forming a silicon oxide film and a process for forming a connection hole are required, which poses a practical problem. is there.

[0006] In view of the above problems, a first object of the present invention is to realize the multilayer wiring structure proposed above, and to prevent disconnection of a signal line without greatly increasing the number of steps. An object of the present invention is to realize a liquid crystal display panel and a method of manufacturing the same that can be reliably prevented.

A second object of the present invention is to realize a liquid crystal display panel and a method of manufacturing the same, which can improve display quality by using a multi-layer wiring structure.

[0008]

A liquid crystal display panel according to the present invention.
Is formed on the front side of the thin film transistor in the pixel area.
On the surface side of the interlayer insulating film through a first connection hole.
Signal line conductively connected to the source region of the thin film transistor
And the drain of the thin film transistor through the second connection hole.
And a pixel electrode conductively connected to the input region.
A line is connected to the source region through the first connection hole.
A first metal wiring layer to be connected, and on a surface of the metal wiring layer
And a second metal wiring layer formed on the first metal layer.
The metal wiring layer is made of chromium, and the second metal wiring layer is made of metal.
The pixel electrode is made of ITO,
The second connection hole has therein the first metal wiring layer.
And a buried electrode layer formed at the same time.
The electrode comes into contact with the embedded electrode layer, thereby
It is characterized by being conductively connected to the rain region .

Further , the manufacture of the liquid crystal display panel according to the present invention.
The method includes a first step of forming a thin film transistor on a substrate.
And depositing an interlayer insulating film on the thin film transistor.
A second step, a source region of the thin film transistor, and
A first connection hole and a second connection respectively on the drain region;
A third step of forming holes;
To form the first metal wiring layer of the signal wiring.
Fourth step of leaving an embedded electrode layer inside the second connection hole
And apply ITO and pattern to form pixel electrodes
Fifth process to form and apply aluminum and etch
And a second metal wiring of the signal line.
And a sixth step of forming a line layer.
You. Note that the fifth step and the sixth step may be reversed.
No.

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

According to the present invention, the signal line is formed of the first interlayer insulating film.
And a second metal wiring layer formed on the surface of the first metal wiring layer conductively connected to the source region through the connection hole. In addition, the first metal wiring layer and the second metal wiring layer are made of different materials. For example, in wet etching, an etchant for a metal material forming the second metal wiring layer is used to etch the first metal wiring layer. Do not etch constituent metal materials. For this reason, when forming the second metal wiring layer by patterning,
Even if there is a defect in the mask layer and the second metal wiring layer is etched to be disconnected, the first metal wiring layer is not affected and no broken portion occurs. Therefore, since the disconnected portions of the first and second metal wiring layers do not overlap each other, even if there is a disconnection in one of the metal wiring layers, the conductive connection of the disconnected portion is performed by the metal wiring layer on the other side. In addition, the signal line itself is not disconnected.

In the step immediately after the opening of the first and second connection holes,
In this case, the second connection hole is formed simultaneously with the formation of the first metal wiring layer.
Embedded in the buried electrode layer
The region does not remain exposed through the second connection hole,
The display quality can be prevented by preventing damage to the drain region during processing.
Can be improved .

The first metal wiring layer is made of chromium and the second metal wiring layer is made of chromium.
Since the metal layer is aluminum, the chromium
The pole layer is formed without interposing aluminum of the second metal wiring layer.
Since it is in direct contact with the pixel electrode, the second gold
Thinner by the thickness of the metal wiring layer, resulting in lower contact resistance.
Resistance can be achieved. Furthermore, at the contact
Oxidation degradation caused by oxygen contained in ITO of pixel electrode
Contact can be suppressed compared to aluminum.
High resistance can be avoided and display quality is extended.
I can .

[0018]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a plan view showing a part of a matrix array of a liquid crystal display panel according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view taken along line II.

In this embodiment, as shown in FIG. 1, vertical signal lines 2a, 2b.
are wired in a grid pattern, and pixel regions 1a, 1b,... are formed between them.

The structure of the pixel region 1a will be described below by taking the pixel region 1a as an example. In this pixel region 1a, the signal line 2a
The TFT 8 is formed by a source region 4 to which a conductive connection is made, a gate electrode 5 to which a gate line 3a is conductively connected, and a drain region 7 to which a pixel electrode 6 is conductively connected. Here, the pixel electrode 6 is a transparent electrode made of ITO, and is formed over substantially the entire surface of the pixel region 1a.

As shown in FIG. 2, the sectional structure of the TFT 8 is such that a polycrystalline silicon layer 10 is formed on the front side of a transparent glass substrate 9 which supports the entire liquid crystal display panel.
Except for the channel region 11 which is an intrinsic polycrystalline silicon region, phosphorus as an n-type impurity is introduced into the polycrystalline silicon layer 10 to form the source region 4 and the drain region 7. Here, the introduction of phosphorus is performed by the gate oxide film 1 formed on the surface side of the polycrystalline silicon layer 10.
The source region 4 and the drain region 7 are self-aligned by utilizing ion implantation using the gate electrode 5 on the mask 2 as a mask. On the front side of the TFT 8, an interlayer insulating film 13 made of a silicon oxide film is deposited, and a first connection hole 13a and a second connection hole 13b are opened in the interlayer insulation film 13. The signal line 2a is conductively connected to the source region 4 via the first connection hole 13a. This signal line 2a is connected to the first connection hole 13a.
Has a two-layer structure including a lower chromium layer 14 which is conductively connected to the source region 4 through an aluminum layer 15 formed on the surface thereof. One second connection hole 1
The pixel electrode 6 is conductively connected to the drain region 7 via 3b.

In the liquid crystal display panel, as described later, the signal line 2a is formed by the chrome layer 14 and the chrome layer 1
4 and an aluminum layer 15 formed in a separate step, so as shown in FIG. 3 showing a cross section taken along line II-II in FIG. As long as the positions of the disconnection portions 16 do not overlap, the signal line 2a does not become disconnected. In other words, since the redundant wiring structure has a relationship in which the disconnection state of one side is complemented by the other side, a signal potential is reliably applied to each source region to all pixel regions connected to the signal line 2a. Line defects are extremely unlikely to occur in this liquid crystal panel.

A method for manufacturing a matrix array of a liquid crystal display panel having such a structure will be described with reference to FIG.

FIG. 4 is a process sectional view showing a part of a method of manufacturing a liquid crystal panel display.

First, as shown in FIG. 4A, an intrinsic polycrystalline silicon layer 10a is deposited on the surface of a glass substrate 9 by a CVD method, and then thermal oxidation is performed to form a gate oxide film 12. Form.

Next, a phosphorus-doped polycrystalline silicon layer is formed on these surface sides by a CVD method, and then patterned to leave the gate electrode 5. Thereafter, as shown in FIG. 4B, phosphorus is ion-implanted using the gate electrode 5 as a mask to make the source region 4 and the drain region 7 conductive. Here, an intrinsic polycrystalline silicon portion is left directly below the gate electrode 5, and this becomes the channel region 11.

After the TFTs 8 are formed in this manner, an interlayer insulating film 13 is formed on these surfaces by CVD.
Is deposited. Thereafter, as shown in FIG. 4C, a first connection hole 13a and a second connection hole 13b are formed above the source region 4 and the drain region 7.

Next, as shown in FIG. 4 (d), chromium is deposited on these surface sides by sputtering to form a chromium layer 14a over the entire surface, and then a resist mask having a predetermined region opened in a window. The layer 17a is formed. In this state, the entire chromium layer 14a is chemically etched with an etching solution for chromium containing cerium ammonium nitrate and the like, and the chromium layer 14 is left.

Next, after an ITO layer is deposited on these surfaces by a sputtering method, a resist mask layer having a predetermined region opened in a window is formed on the surface. In this state, with an etching solution for ITO containing hydrochloric acid, nitric acid, etc.,
The ITO layer is chemically etched to leave the pixel electrode layer 6 as shown in FIG.

Further, as shown in FIG. 4 (f), aluminum is deposited on these surface sides by a sputtering method.
After forming the entire surface aluminum layer 15a, a resist mask layer 17b having a predetermined region opened in a window is formed. In this state, the entire aluminum layer 14a is chemically etched with an etching solution for aluminum containing phosphoric acid, nitric acid, etc., as shown in FIG.
Are formed to form the signal line 2a.

As described above, in this example, the signal line 2a
To form a multilayer structure, a chromium layer 14
The upper layer employs an aluminum layer 15 which can be etched with a phosphoric acid or nitric acid-based etchant having no etching ability with respect to the chromium layer.

Therefore, even if there is a defect in the resist mask layer 17b for forming the aluminum layer 15 and a disconnection occurs in the aluminum layer 15, no disconnection occurs in the lower chromium layer 14. Therefore, a disconnection portion does not occur at the same position of the chromium layer 14 and the aluminum layer 15 so that the signal line 2a itself does not become disconnected. Therefore, in the liquid crystal display panel of this example, a display line defect due to the disconnection of the signal line 2a hardly occurs. In addition, ITO represented by hydrochloric acid-nitric acid system
The etching solution for aluminum generally has an etching ability for an aluminum layer, whereas the etching solution for aluminum represented by phosphoric acid-nitric acid has no etching ability for ITO. In this example, these relationships are used to the utmost, and the aluminum layer 1 is formed after the pixel electrode 6 is formed.
5, and the step of forming an unnecessary mask layer is omitted. Therefore, even if a redundant wiring structure is adopted for the liquid crystal display panel, an increase in the number of manufacturing steps is kept to a minimum, so that the liquid crystal display panel has cost responsiveness. In addition, since the formation area of the signal line 2a is not expanded, the aperture ratio is maintained, so that the display quality does not deteriorate.

Second Embodiment Next, a liquid crystal display panel according to a second embodiment of the present invention will be described with reference to FIG.

FIG. 5 is a cross-sectional view of the matrix array of the liquid crystal display panel according to the second embodiment. Unlike the liquid crystal display panel according to the first embodiment, the second connection hole 1 of the interlayer insulating film 13 is different.
3b, a buried electrode layer 21 made of chromium is provided, and through this buried electrode layer 21, a pixel electrode 22 is formed.
Are conductively connected to the drain region 7. Other structures are the same as those of the liquid crystal display panel according to the first embodiment shown in FIG. 1, and corresponding parts are denoted by the same reference numerals and description thereof will be omitted. Here, the buried electrode layer 21 is formed simultaneously with the chromium layer 14. Therefore, before forming the pixel electrode and the aluminum layer, the buried electrode layer 2
Since 1 is formed, after this is formed, the drain layer 7 is not exposed. Therefore, even if a drain layer 7, that is, an etchant having a corrosive property to silicon is used in a later step, the drain layer 7 is not eroded, so that the restrictions on the manufacturing conditions can be relaxed. .

A method of manufacturing a liquid crystal display panel having this structure is described below.
This will be described with reference to FIG.

FIG. 6 is a process sectional view showing a part of the method of manufacturing the liquid crystal display panel of this embodiment.

Here, the steps up to depositing chromium by sputtering to form the chromium layer 14 and the buried electrode layer 21 are the same as those up to FIG. 4D described above. In this example, instead of the resist mask layer 17a covering only the region where the chromium layer 14 is formed, as shown in FIG. 6A, the position above the second connection hole 13b is also covered. A resist mask layer 24a is formed. Therefore, when the entire chromium layer 14a is chemically etched with an etching solution for chromium containing cerium ammonium nitrate and the like in this state, the buried electrode layer 21 can be left as shown in FIG. 6B. .
Accordingly, in this state, since the drain layer 7 is not covered and exposed by the buried electrode layer 21, there is no limitation on the subsequent steps.

Therefore, an example in which aluminum containing copper is used for the aluminum layer 15 will be described. Here, the reason why aluminum containing copper is used is that the miniaturization of the cell and the signal line 2
This is to prevent the occurrence of a disconnection accident due to stress, electromigration, or the like when a is also miniaturized. In some cases, aluminum containing silicon or the like may be used.

First, as shown in FIG. 6C, aluminum containing copper is deposited by sputtering to form an aluminum layer 23a over the entire surface. Next, chemical etching is performed in a state where a predetermined region is covered with a mask layer 24b having an opened window, and the signal line 2a is formed while leaving the aluminum layer 23 on the chromium layer 14, as shown in FIG. I do.

In this chemical etching, aluminum is dissolved and removed, but the dissolution rate of copper is low, and copper residues may remain. This residue needs to be removed in order to maintain good light transmittance. For this removal, wet etching, plasma etching, or the like is used. Here, if the drain region 7 is exposed, the drain region 7 will be damaged at the same time.
Is not damaged because it is covered with the buried electrode layer 21, thereby preventing the occurrence of point defects and the like due to the damage. Therefore, there is no restriction on various conditions such as employment of aluminum containing copper or silicon and employment of plasma etching, so that the degree of freedom in the configuration and manufacturing of the liquid crystal display panel is increased.

In this embodiment, since the aluminum layer 23 is formed before the pixel electrode 22 is formed,
If a hydrochloric acid-nitric acid based ITO etchant is used as it is as in the first embodiment, the aluminum layer 23 is also etched. Therefore, in the ITO patterning step, masking of the aluminum layer 23, an etching solution for ITO having no corrosiveness to aluminum, a dry etching method, or the like is employed.

Third Embodiment Next, a liquid crystal display panel according to a third embodiment of the present invention will be described with reference to FIG.

FIG. 7 is a sectional view of the matrix array of the liquid crystal display panel according to the third embodiment, which has the same structure as the liquid crystal display panel according to the second embodiment shown in FIG. The code is attached. In the liquid crystal display panel according to the present embodiment, unlike the liquid crystal display panel according to the second embodiment, a thick polyimide layer 31 as a surface protection film is formed on the surface side of the signal line 2a including the chromium layer 14 and the aluminum layer 23. The pixel electrode 32 is conductively connected to the buried electrode layer 21 through the connection hole 31a. That is, the pixel electrode 32 is configured to be conductively connected to the drain region 7 via the buried electrode layer 21. The end 32a of the pixel electrode 32 extends to the vicinity of the signal line 2b in the adjacent pixel region 1b. Since other structures are the same, the description thereof is omitted. Note that, also in this example, aluminum containing copper is used for the aluminum layer 23.

In the liquid crystal display panel having such a structure,
As in the liquid crystal display panel according to the second embodiment, the redundant wiring structure of the signal line 2 a prevents display defects from occurring, and in addition, the drain region 7 is covered by the buried electrode layer 21 formed simultaneously with the chromium layer 14. In this state, the aluminum layer 23 and the pixel electrode 32 are formed, so that the drain region 7 is not damaged in the step of forming them. For example, after using aluminum containing copper for the aluminum layer 23 and performing patterning by chemical etching or dry etching, there is no problem even if a cleaning step is performed in order to remove the remaining residue such as copper.
The polyimide layer 31 also has a function of protecting the aluminum layer 23 when forming the pixel electrode 32.

Further, in the liquid crystal display panel of this embodiment, the end 32a of the pixel electrode 32 is
b extends to the vicinity of the signal line 2b and is in an overlapping state. In the conventional structure, the end of the pixel electrode is
When the pixel electrode and the signal line are arranged close to the signal line in the adjacent pixel region, the pixel electrode and the signal line are likely to be short-circuited,
In addition, even if it is not in the short-circuit state, the electric field generated between them causes disturbance in the alignment of the liquid crystal, which causes display unevenness. Therefore, although the aperture ratio is sacrificed, the formation region of the pixel electrode has been reduced. On the other hand, in this example, the thick polyimide layer 31 is interposed between the end portion 32a and the signal line 2b to prevent a short-circuit state and a strong electric field between them. Does not occur. For this reason, display deterioration due to the electric field does not occur, so that the adjacent pixel regions 1a, 1b
There is no cross talk between each other. Therefore, the display quality is improved by arranging the end portion 32a close to the signal line 2b to increase the area of the pixel electrode 32 and increase the aperture ratio. In addition, the signal lines 2a and 2b are in contact with the liquid crystal via the polyimide layer 31, and a strong electric field is prevented from being generated between the common lines and the opposing common electrodes. For this reason,
Since the disturbance of the alignment state of the liquid crystal generated by the electric field is suppressed, the display quality is further improved.

A method for manufacturing a liquid crystal display panel having such a structure will be described with reference to FIG.

FIG. 8 is a process sectional view showing a part of the method of manufacturing this liquid crystal display panel.

First, the chromium layer 14, the buried electrode layer 2
1 and the steps up to the formation of the aluminum layer 23 are the same as those up to FIG. 6D described as the second embodiment, and the description of the steps up to that point is omitted.

In this example, from this state, FIG.
As shown in (a), a thick polyimide layer 31 having a connection hole 31a is formed above the embedded electrode layer 21.

Next, as shown in FIG. 8B, an ITO layer 32b is formed on the entire surface by sputtering.
Using a hydrochloric acid-nitric acid based etchant for ITO,
The O layer is chemically etched. Here, as shown in FIG. 7, the IT is adjusted so that the end 32a of the pixel electrode 32 is located above the signal line 2b of the adjacent pixel region 1b.
Leave the O layer to ensure the maximum aperture ratio. Here, the polyimide layer 31 also has a function of preventing the aluminum electrode 23 from being etched by the etching solution for ITO.

In the liquid crystal display panel of this embodiment,
If necessary, each layer may be formed by dry etching. For example, even when plasma etching or the like is used for etching the aluminum layer, chromium has a higher etching resistance with respect to the etching species used therefor, so that no disconnection occurs at the same position as the aluminum layer. The effect of the redundant wiring structure is exhibited.

The arrangement, shape, structure, etc. of each region and each layer are properties that should be set to predetermined conditions according to the size, application, etc. of the liquid crystal display panel to be manufactured, and are not limited. is there.

Further, the order of the steps after the formation of the chromium layer is a property to be set in an optimum order according to the structure of the liquid crystal display panel to be manufactured, etching conditions and the like.

[0055]

As described above, the liquid crystal display panel according to the present invention is formed on the surface of the thin film transistor in the pixel region.
Through the first connection hole on the surface side of the formed interlayer insulating film.
A signal line conductively connected to the source region of the thin film transistor
And the drain of the thin film transistor through the second connection hole.
And a pixel electrode conductively connected to the input region.
A line is connected to the source region through the first connection hole.
A first metal wiring layer to be connected, and on a surface of the metal wiring layer
And a second metal wiring layer formed on the first metal layer.
The metal wiring layer is made of chromium, and the second metal wiring layer is made of metal.
The pixel electrode is made of ITO,
The second connection hole has therein the first metal wiring layer.
And a buried electrode layer formed at the same time.
The electrode comes into contact with the embedded electrode layer, thereby
Characterized by being conductively connected to the rain area
There is . Therefore, according to the present invention, the following effects can be obtained.

When forming the second metal wiring layer on the first metal wiring layer, even if the mask used for patterning has a defect and the second metal wiring layer is disconnected, Disconnection does not reach even one metal wiring layer. Therefore,
Since the probability of occurrence of a disconnection at the same position of the first metal wiring layer and the second metal wiring layer is extremely low, disconnection of the signal line is unlikely to occur. Therefore, it is possible to suppress the occurrence of display line defects due to the disconnection.

Work immediately after the opening of the first and second connection holes
In the step, the second connection hole is formed with the formation of the first metal wiring layer.
At the same time, since it is embedded and sealed by the embedded electrode layer,
If the in area remains exposed through the second connection hole
And prevent the drain region from being damaged during the process.
The display quality can be improved .

The chromium embedded electrode layer is made of a second metal.
Direct contact with the pixel electrode without aluminum in the wiring layer
Because it is touching, the thickness of the second metal wiring layer
To reduce the contact resistance.
Can be .

Further, the contact portion of the pixel electrode
Oxidation degradation caused by oxygen contained in ITO
The contact resistance can be reduced compared to the case of
Resistance can also be avoided, and the display quality can be extended .

[0060]

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of a matrix array of a liquid crystal display panel according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view taken along line II of FIG.

FIG. 3 is a sectional view taken along line II-II of FIG.

FIGS. 4A to 4F are process cross-sectional views each showing a part of a process of manufacturing a matrix array of the liquid crystal display panel according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a part of a matrix array of a liquid crystal display panel according to Embodiment 2 of the present invention.

FIGS. 6A to 6D are process cross-sectional views illustrating a part of a process of manufacturing a matrix array of a liquid crystal display panel according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing a part of a matrix array of a liquid crystal display panel according to Embodiment 3 of the present invention.

8 (a) and (b) show Embodiment 3 of the present invention.
FIG. 6 is a process cross-sectional view showing a part of the process of manufacturing the matrix array of the liquid crystal display panel according to the embodiment.

FIG. 9 is a sectional view showing a part of a matrix array of a conventional liquid crystal display panel.

[Description of Signs] 1a, 1b: Pixel region 2a, 2b: Signal line 3a, 3b: Gate line 4: Source region 5: Gate electrode 6, 22, 22, 32 ... Pixel electrode 7 ... Drain region 8 ... TFT 14 ... Chromium layer (first metal wiring layer) 15, 23 ... Aluminum layer (second metal wiring layer) 21 ... Embedded electrode layer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1343 G09F 9/30

Claims (3)

(57) [Claims] 1. A signal line conductively connected to a source region of the thin film transistor via a first connection hole on a surface side of an interlayer insulating film formed on a surface side of the thin film transistor in a pixel region; A pixel electrode conductively connected to a drain region of the thin film transistor through a hole, the signal line being a first metal wiring layer conductively connected to the source region through the first connection hole; A second metal wiring layer formed on a surface of the metal wiring layer, wherein the first metal wiring layer is made of chromium, and the second metal wiring layer is made of chromium.
The metal wiring layer is made of aluminum, and the pixel electrode is made of IT.
O, and the second connection hole has the first connection hole therein.
Buried electrode layer formed simultaneously with the metal wiring layer
The pixel electrode contacts the buried electrode layer.
A liquid crystal display panel, wherein the liquid crystal display panel is conductively connected to the drain region . 2. A method for forming a thin film transistor on a substrate.
Step 1 and depositing an interlayer insulating film on the thin film transistor
A second step of stacking, and a source region of the thin film transistor.
A first contact hole and a second contact hole on the region and the drain region, respectively.
A third step of forming a connection hole of
To form a first metal wiring layer for signal wiring.
And leaving a buried electrode layer inside the second connection hole.
And ITO patterning and patterning
A fifth step of forming the poles, and
Patterning by means of the
And a sixth step of forming a metal wiring layer.
A method for manufacturing a liquid crystal display panel. 3. A method of forming a thin film transistor on a substrate.
Step 1 and depositing an interlayer insulating film on the thin film transistor
A second step of stacking, and a source region of the thin film transistor.
A first contact hole and a second contact hole on the region and the drain region, respectively.
A third step of forming a connection hole of
To form a first metal wiring layer for signal wiring.
And leaving a buried electrode layer inside the second connection hole.
Process and patterning by etching aluminum
To form a second metal wiring layer of the signal line
A fifth step of depositing and patterning the ITO
And a sixth step of forming a pixel electrode.
Characteristic liquid crystal display panel manufacturing method .