JP3053270B2 - Power supply backup method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention utilizes a main power supply and an auxiliary power supply and uses a power supply from the auxiliary power supply to back up data when the main power supply is off, or saves data to a nonvolatile memory when the main power supply is off. The present invention relates to a power supply backup method and apparatus in which backup processing is improved in a microcomputer system or the like that performs backup.

[0002]

2. Description of the Related Art Conventionally, a general microcomputer system is a CP.
U (Central Processing Uni)
t), ROM (Read Only Memory) and RAM (Random Access Memory)
And the like, an input / output port, a counter, a timer, a clock generator / controller (hereinafter simply referred to as CGC) for generating a system clock, and the like.

FIG. 9 shows an example of this microcomputer system. The microcomputer system 1 shown in FIG.
AM11, ROM12, I / O port 13, CGC14
It consists of. In the device using the microcomputer system shown in FIG. 9, data for controlling the device by a program stored in the ROM 12 in advance is transmitted to the input / output port 1.
3 and outputs the data input to the device to RA
It operates to store the data in the M11 or calculate the data in the RAM 11, and further execute each process according to a program to control the device.

For example, a VT using a microcomputer system
In R (Video Tape Recorder), it is as follows. The microcomputer system of the VTR constantly monitors various switches provided in the device through an input / output port, and when a certain switch is pressed, works on the device so as to perform a process corresponding to the switch. For example, when the pressed switch indicates the reproduction of the tape, the VTR is controlled through the input / output port so as to reproduce the tape.

On the other hand, in a device utilizing the microcomputer system 1 as described above, an auxiliary power supply 3 may be provided so that data stored in the RAM 11 does not disappear even when the main power supply of the device is turned off.

For example, in the microcomputer system 1 shown in FIG. 9, the main power is supplied from the power supply terminal 2, and the auxiliary power supply 3 including the battery 30 and the diode 3b is supplied with power from the battery 3a when the main power is turned off. In the event of a power failure or the like, the data stored in the RAM 11 is protected (backed up) so as not to be lost. The auxiliary power supply 3 is configured to back up the microcomputer system 1, and the microcomputer system 1 may be a one-chip IC or an individual IC.

Next, the operation of the system of FIG. 9 will be described with reference to the timing chart of FIG. 5 and the flowchart of FIG. The voltage detection circuit 6 generates an L-level signal when the main power supplied via the terminal 2 is turned off, and generates an H-level signal when the main power is on.
For example, when the main power supply is turned off at t ₁ , the voltage detection circuit 6
The signal of the level is input to the CPU 14, and the interruption of step S31 is performed.

When the CPU 14 receives the L-level interrupt signal, it performs pre-processing (hereinafter simply referred to as "back-up processing") to enter the backup state in step S33.
Execute This backup processing is performed, for example, in a RAM
While data of a predetermined length is being written into the memory 11, the writing is continued until all the data has been written. The processing time (t _{1 to} t ₃ ) is, for example, several hundred μsec.
c. During the period of the backup process, it is necessary to operate without using the battery 3a having a voltage equal to or lower than the normal operation voltage. Therefore, in the example of the microcomputer system shown in FIG. 9, the capacitor 7 is used. This capacitor 7
Is charged when the main power supply is turned on, and the microcomputer system 1 is operated during the backup process by the charged electric charge.

After the backup process is completed, the CPU 14 outputs an L-level HALT signal so as to stop the operation and enter the backup state (t ₃ ). Then, the CGC 15 stops the oscillation and stops the clock output. As a result, the microcomputer system 1 proceeds to step S35.
As a result, a backup state (HALT state) is established and current consumption is extremely reduced.

For example, although the current consumption differs depending on the configuration of the microcomputer system 1, a CMOS (Comple
entry Metal-Oxide Semico
In the case of employing N.sub.ductor, it is about several mA to several tens mA or more in an operation state driven by a normal main power supply, whereas it is about several μA to several tens μA in a HALT state driven by an auxiliary power supply. For example, when comparing current consumption per IC, a clock generator / controller for Toshiba Z80: TMPZ84C61A
According to the specifications, the current consumption during operation is 3 mA (6 M
Hz operation), but less than 10 μA in the HALT state.

Next, the operation when the main power supply is turned on will be described. First, the main power supply detects the rise of the main power supply voltage detection circuit 6 is turned on at t _4, the rising edge is input to CGC15. When this rising edge is input, the CGC 15 restarts oscillation (t ₅ ).

The CGC 15 has a period until the clock oscillation stabilizes (a so-called warm-up period (t _4)).
To t ₅ ), which is usually several ms to several tens ms) is CG
It does not output a clock to the outside of C15, nor does it output an interrupt signal to the CPU 14 indicating that the main power supply has been turned on. After the end of the warm-up period, CG
C15 outputs a clock, and further outputs an interrupt signal to the CPU 14 indicating that the main power supply has been turned on. CP
When U14 receives this interrupt signal and clock, H14
Set the T signal to H level. As a result, the microcomputer system 1 enters an operating state.

Next, in the microcomputer system 1 shown in FIG. 9, a description will be given of a case where the period during which the main power supply is turned off is shorter than the time from the above-mentioned backup processing until the CGC stops oscillating. This is performed with reference to the flowchart of FIG.

[0014] As shown in FIG. 11, the main power source interrupt signal is output to the voltage detection circuit 6 from CPU14 is turned off at t ₄₁ (step S31). CPU1 receiving this
4 executes a backup process (step S33).
However, the example of FIG. 10, again the main power before (t ₄₅₎ of the microcomputer system 1 is a backup state (HALT state) is in the ON state at t _43. In this case, when a rising edge is input from the voltage detection circuit 6,
The CPU 14 is still performing the backup process. Also CG
C15 is not in the backup state (HALT state).
In this state, a rising edge is input from the voltage detection circuit 6. Therefore, no interrupt signal is output from the CGC 15 to the CPU 14. Then, CPU 14 is a HALT to L level After completion of the backup process by t ₄₅ (step S35). CGC that received this HALT
15 stops the oscillation, the clock output stops, and the microcomputer system 1 enters a backup state (HALT state). Then, the microcomputer system 1 does not operate again in the backup state (HALT state).

[0015]

As described above, in the conventional microcomputer system, if the period during which the main power supply is turned off is shorter than the backup processing period, the microcomputer system 1 enters the backup state (HALT state). It stops operating again.

The present invention has been made in view of the above problems, and
An object of the present invention is to provide a power supply backup method and apparatus for a microcomputer system that can return from a backup process to a normal operation state even when a period during which a main power supply is turned off is shorter than the backup process period.

[0017]

According to a first aspect of the present invention, there is provided a power supply backup method for a microcomputer system which is driven by a supplied power supply and is turned off after a backup process is completed when the power supply is turned off. In the above, the backup processing is performed by turning off the power supply, and after the backup processing is completed, the power supply is turned off, and the power supply is turned off.

According to a second aspect of the present invention, there is provided a power supply backup device for a microcomputer system which is driven by a supplied power supply and is turned off after a backup process is completed when the power supply is turned off. The power supply is determined to be off by the determination means. When the power supply is off, when the power supply is off, the power supply is turned off. And a control means for setting a driving state when the power is on.

[0019]

According to the power supply backup method for a microcomputer system of the first invention of the present application, when the microcomputer system is brought into a halt state after the backup processing when the supplied power is turned off, the power supply is re-started after the backup processing is completed. Check the status of the device, and when it is off, stop the device.
When it is on, it returns to the driving state.

Further, the power supply backup device of the microcomputer system according to the second invention of the present application is adapted to determine whether the power supplied by the determination means is on or off, and the control means uses the determination means to turn off the power supply. When the power is again determined by the determination means after the backup process started after the determination is completed, the microcomputer system is in a stopped state, and when the power is on, the microcomputer system is in a driven state.

Therefore, according to the power supply backup method and apparatus of the microcomputer system of the present application, when the power supply is restored before the backup process started by turning off the power supply is completed, the microcomputer is not required. Put the system back into operation.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS.

FIG. 1 shows an example of a microcomputer system employing a power supply backup device according to the present invention.
The difference is that the input signal from the power supply voltage detection circuit 6 as the determination means is input to the input / output port 13 as compared with the conventional microcomputer system shown in FIG. Some commercially available input / output port circuits (ICs) have an interrupt control circuit. In this case, as shown in the circuit configuration of FIG. In this case, an interrupt input from the power supply voltage detection circuit 6 to the CPU 14 can be omitted.

The microcomputer system 1 shown in FIG.
11, ROM 12, input / output port 13, CPU 14, C
The GC 15, the address bus B _A , the data bus _{BD, the} control line C, and the like constitute one chip.
In FIG. 1, the CPU 14 has a RAM 11 and a ROM 1
2. Illustration of a so-called address decoder and a clock line for decoding an address generated when accessing the input / output port 13 to make each IC accessible (a state where an enable input terminal of each IC is enabled). I haven't. The interrupt request signal input to the CPU 14 is one of the control lines C shown in FIG. 1 (there are other control signals for a memory and an input / output port). Are shown only in FIG.

The voltage detection circuit 6 monitors the voltage of the power supply input to the microcomputer system 1 and the voltage detection circuit 6 through the power supply terminal 2, and when the supply of the power supply is stopped (turned off), A signal that the power is turned off from the voltage detection circuit 6 directly interrupts the CPU 14. Thus, backup processing such as saving data in the RAM 11 to a non-volatile memory (not shown) or receiving power from the auxiliary power supply 3 and retaining data is performed.

The backup capacitor 7 requires a power supply capable of operating the circuit for the time required for the microcomputer system 1 to save data to a non-volatile memory (not shown).
The charge stored in the capacitor is used. Also,
The diode 4 is for preventing the electric charge accumulated in the backup capacitor 7 for supplying the power when the power is turned off from flowing back to the microcomputer system 1 side.

Further, in the example shown in FIG. 1, the microcomputer system 1 is not operated while the power is supplied from the battery 3, so that the power supply voltage at the time of backup may be lower than the normal operation voltage (5V). (For example, the minimum power supply voltage for retaining data in the RAM 11 is about 2.5 V). This is effective when the microcomputer system 1 is a one-chip IC and the auxiliary power supply 3 is configured to back up the whole.
If the CPU 1 is not operated in this manner, the auxiliary power supply 3 may be lower than the normal operating voltage. In addition, by not operating the microcomputer system 1 at the time of backup, power consumption is reduced. Can be reduced.

Next, the microcomputer system 1 shown in FIG.
The configuration and operation of the CGC 15 will be described with reference to FIG. 2 and FIG. The input of the CGC 15 is a power ON / OFF signal from the voltage detection circuit 6 and an H signal from the CPU 14.
ALT signal, and the output of CGC 15 is
This is an interrupt signal indicating that the power is turned on.

First, when the main power supply is turned off at t ₁ , the CPU
14 sets HALT to L level after the backup process is completed (t ₃ ). The falling edge detection unit 151
At the falling edge of the ALT, an L level detection signal is generated, and the RS flip-flop 154 and the counter 159 are reset. Then, the output of the RS flip-flop 154 becomes L level, and the switch 155 connecting the oscillator 156 and the crystal 158 is opened. This stops oscillation,
Clock output stops.

Next, when the main power supply is turned on at t ₄ ,
A rising edge is input from the voltage detection circuit 6. This signal is inverted by the inverter 152, and the falling edge detector 153 generates an L level detection signal at the falling edge. With this detection signal, the RS flip-flop 154 is set, and the output of the RS flip-flop 154 becomes H level. The switch 155 for connecting the oscillator 156 and the crystal 158 is closed at the H level of the RS flip-flop 154, oscillation starts, and the AND gate 1
A clock is output from 57. Next, the counter 159
After the warm-up period will continue to count the clock (t ₄ ~t ₅₎ (the order of several tens ms from several ms) counting, with respect to CPU 14, and outputs an interrupt signal indicating that the main power is turned on. When receiving the interrupt signal and the clock, the CPU 14 sets the HALT signal to the H level. As a result, the microcomputer system 1 enters an operating state.

Next, the operation of this embodiment will be described with reference to the flowchart shown in FIG. As is clear from FIG.
In the present embodiment, after the main power supply is turned off and the backup processing in step S3 is completed, the process proceeds to step S5 to check the output signal level of the voltage detection circuit 6. That is, the state of the main power supply is confirmed at the end of the backup processing. If the output signal of the voltage detection circuit is at the H level, it is considered that the power supply has returned to the on state again. If it is at the L level, it is considered that the main power supply remains off. Therefore, after the backup processing is completed, the output signal level of the voltage detection circuit is checked. If the output signal of the voltage detection circuit is at the H level, the process proceeds to step S7, and returns to the normal processing state. If the output signal is at the L level, the process proceeds to step S9. Advance to HALT state.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 5 is a timing chart at the normal time in the embodiment, and FIG. 6 is a timing chart at the time of the momentary power-off.

[0033] In the timing diagram during the normal shown in FIG. 5, when the main power is turned off at t ₁ CPU 14 starts execution of the backup process. During the backup processing period t _{1 to} t ₃ , as described above, the microcomputer system operates by the electric charge charged in the capacitor 7, and the power supply voltage is kept at approximately 5V. Then, the CPU 14 sets t ₃
After the backup process is completed, the output signal level of the voltage detection circuit 6 is confirmed. In the normal state, the output signal of the voltage detection circuit 6 is at the L level at this time. Therefore, HALT is set to L level. C who received this HALT
The GC 15 stops oscillating, the clock output stops, and the microcomputer system 1 enters a backup state (stop state).

Next, when the main power supply is turned on at t ₄ ,
A rising edge is input from the voltage detection circuit 6. Upon receiving this signal, the CGC 15 restarts oscillation, and after a warm-up period (about several ms to several tens ms) of a predetermined period (t _{4 to} t ₅ ), outputs a clock again and turns on the main power supply to the CPU 14. and outputs an interrupt signal indicating that at t _5. Then, the CPU 14 sets the HAL
The T signal is set to the H level to enter the operating state.

[0035] Next, in the timing chart at the time of momentary power-off shown in FIG. 6, when the main power is turned off at t ₁₁ CP
U14 performs the backup process, check the output signal level of the voltage detection circuit 6 at t ₁₅ Upon completion of the backup process. In time instantaneous power-off (t ₁₁ ~t _13), the output signal of the voltage detecting circuit 6 in this case (t ₁₅₎ is in the H level. Therefore, the CPU 14 returns to the normal operation state without setting the HALT state.

That is, when the CPU 14 confirms the output signal from the voltage detection circuit 6 after the execution of the backup process by the CPU 14, if the output signal is still at the L level, the CPU 14 is in the backup state (HA).
The HALT is set to the L level so as to be in the (LT state), the CGC 15 receiving the HALT stops the oscillation and stops the clock output, and the microcomputer system 1 enters the backup state (HALT state). However, if the output signal from the voltage detection circuit 6 has returned to the H level, the CPU 14 performs processing to return to the normal operation state.

In the above description, the auxiliary power supply 3 is configured to back up the microcomputer system 1.
However, the auxiliary power supply 3 may be supplied only to the RAM 11 that requires the auxiliary power supply 3 as in the microcomputer system shown in FIG.

Also in this case, when the main power supply is turned off, the voltage detection circuit 6 inputs an L level signal to the CPU 14.
Upon receiving this L-level interrupt signal, the CPU 14 executes pre-processing (back-up processing) to enter the backup state. This backup process is, for example, a process in which while writing data of a predetermined length in the RAM 11, the writing is continued until all the data has been written, and the processing time is, for example, about several hundred μsec.

After the backup process is completed, the CPU 14
Stops the operation and outputs an L-level HALT signal. When the CGC 15 receives the L level HALT signal, the CGC 15 stops the oscillation and stops the clock output. As a result, even if the voltage of the power supply supplied to other than the RAM 11 drops, there is no possibility that the CPU 14 runs away and destroys the contents of the RAM 11. Therefore, even in such a microcomputer system, even when the period during which the main power supply is turned off is shorter than the backup processing period, the microcomputer system can return from the backup processing to the normal operation state.

The present invention also relates to an auxiliary power supply 3 as described above.
In addition to backing up the RAM 11 by the battery 3a, as shown in the microcomputer system of FIG. 8, an EEPROM (Electrically E
rasable Programmable ROM) 1
6 can be applied to a microcomputer system using the same.

Also in this case, when the main power supply is turned off, the voltage detection circuit 6 inputs an L level signal to the CPU 14.
Upon receiving this L-level interrupt signal, the CPU 14 executes pre-processing (back-up processing) to enter the backup state. This backup process, even if EE
While data of a predetermined length is being written to the PROM 16, writing is continued until all the data has been written, or the RAM 11 is used to prevent data loss when the power is turned off.
The processing time is, for example, about several hundred μs to several tens ms.

After completion of the backup process, the CPU 14 stops the operation and outputs an L level HALT signal. When the CGC 15 receives the L level HALT signal, the CGC 15 stops the oscillation and stops the clock output.
Even if the voltage of the supplied power drops, the CPU 1
4 no longer runs away and destroys the contents of EEPROM 16. Therefore, even in such a microcomputer system, even when the period during which the main power supply is turned off is shorter than the backup processing period, the microcomputer system can return from the backup processing to the normal operation state.

[0043]

As described above, the power supply backup method and apparatus according to the present invention can be used even when the period during which the main power supply is turned off is shorter than the backup processing period.
It is possible to return to the normal operation state immediately after the backup processing is completed.

[Brief description of the drawings]

FIG. 1 is an example of a microcomputer system employing a power supply backup device of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a CGC in the microcomputer system shown in FIG.

FIG. 3 is an example of a microcomputer system employing the power supply backup device of the present invention, and is a block diagram showing a circuit configuration of an input / output port circuit having an interrupt control circuit.

FIG. 4 is a flowchart showing an operation in the microcomputer system shown in FIG. 1;

FIG. 5 is a timing chart of the microcomputer system shown in FIG. 1 in a normal state.

FIG. 6 is a timing chart when the power supply of the microcomputer system shown in FIG. 1 is momentarily turned off.

FIG. 7 is another embodiment of a microcomputer system employing the power supply backup device of the present invention.

FIG. 8 is another embodiment of a microcomputer system employing the power supply backup device of the present invention.

FIG. 9 is an example of a conventional system.

FIG. 10 is an example of a conventional timing chart (at the time of momentary power off).

FIG. 11 is an example of a conventional flowchart.

[Explanation of symbols]

Reference Signs List 1 microcomputer system 2 power supply input terminal 3 auxiliary power supply 4 diode 6 voltage detection circuit 7 capacitor 11 RAM 12 ROM 13 input / output port 14 CPU 15 CGC B _A address bus B _D data bus C control line

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/26

Claims (2)

(57) [Claims] 1. A power supply backup method for a microcomputer system which is driven by a supplied power supply and is turned off after the backup processing is completed when the power supply is turned off, wherein the backup processing is performed by turning off the power supply, and the backup processing is completed. A power supply backup method for a microcomputer system, wherein when the power supply is turned off, the power supply is turned off, and when the power supply is turned on, the power supply returns to a driving state. 2. A power supply backup device of a microcomputer system which is driven by a supplied power supply and is brought into a stop state after a backup process when the power supply is turned off, a determination means for determining whether the power supply is on or off; When the power is off by the means, and when the power is on and off again by the determination means after the end of the started backup process, the power supply is turned off, and the power is turned off. A power supply backup device for a microcomputer system, comprising: control means for setting a driving state.