JP3050341B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit provided on an integrated circuit chip, and more particularly to an output buffer circuit having a CMOS structure.

[0002]

2. Description of the Related Art Today, integrated circuit chips are widely used in the electronic sciences. An electronic product is usually composed of a plurality of integrated circuit chips, and an output buffer is one of important components for interfacing each of them.

FIG. 6 shows an example of the configuration of a generally well-known three-status output buffer circuit. An inverter A60 receives an output buffer enable signal (hereinafter referred to as an EN signal) and a binary data (hereinafter referred to as DATA). And an EN signal and an inverted output logic (hereinafter referred to as N
And an inverted output logic (hereinafter referred to as N) of a logical sum of a data signal and an output of the inverter A60.
A62) and the NAND gate A
P-channel transistor TP6 having an output 61 as a gate input and a power supply voltage (hereinafter referred to as VDD) as a source input
0, and N whose gate input is the NOR gate A62 and whose source input is ground level (hereinafter referred to as GND).
It comprises a channel transistor TN60 and an output terminal P60 to which the drain outputs of the P-channel transistor TP60 and the N-channel transistor TN60 are connected.

In the output buffer circuit having this configuration, when the EN signal is at the "0" level, the output of the NAND gate A61 is "1", the output of the NOR gate A62 is "0", and each of the transistors TP60 and TN60 is off. , DAT
Regardless of the level of the A signal, the output level of the output terminal P60 becomes high impedance (hereinafter, referred to as Hi-Z).

On the other hand, when the EN signal is "1", NAN
The output levels of the D gate A61 and the NOR gate A62 are D
When the DATA signal is "1", the outputs of the NAND gate A61 and the NOR gate A62 are "0", the P-channel transistor TP60 is turned on,
Since the N-channel transistor TN60 is turned off, the output level of the output terminal P60 becomes “1”,
Conversely, when the TA signal is "0", the NAND gate A6
1, the respective outputs of the NOR gate A62 are "1", the P-channel transistor TP60 is off, and the N-channel transistor TN60 is on, so that the output level of the output terminal P60 is "0".

Therefore, the output buffer circuit having the configuration shown in FIG. 6 functions as a three-state output buffer having three values of "0", "1", and "Hi-Z".

In recent years, with the development of device process technology, the operating speed of a chip has been dramatically increased.
Due to the application of electronic technology in all fields, the number of electronic components around us is expanding to a part that we are not usually aware of. In such an environment, one of the things that are particularly highlighted is electromagnetic radiation noise radiated from the integrated circuit chip.

In an era where the degree of integration is low and the operation speed is low, most of the causes of electromagnetic radiation noise are those of integrated circuit chips that improve the selection of a substrate constituting an electronic component and the improvement of wiring. It could be reduced by measures against external factors.

[0009] However, as the degree of integration increases and the operating speed increases due to the development of technology, the current consumption increases accordingly, and a new cause of electromagnetic radiation noise occurs.

The cause of such electromagnetic radiation noise is complicatedly intertwined, and although there are certain guidelines-based know-how for the countermeasure, there is no definitive method, and it is dealt with by a so-called cut-and-try method. That is the reality.

However, due to the miniaturization of the integrated circuit system, measures against these external factors alone are insufficient.
Also, measures against electromagnetic radiation noise of the integrated circuit chip itself have become an important factor.

As a countermeasure against the integrated circuit chip, for example, by optimizing the transistor size of the final stage of the output buffer, the necessary current driving capability can be minimized, or by adjusting the transistor of the final stage of the output buffer and the gate of the preceding stage. By reducing the output waveform to some extent, electromagnetic radiation noise from signal lines is reduced. Further, the timing at which a plurality of output buffers are turned on is slightly shifted to suppress power supply fluctuations, thereby reducing power supply radiation noise of the power supply system.

That is, the measures for these integrated circuit chips can be said to be measures performed in a so-called chip design and manufacturing stage.

[0014]

As described above, the characteristics of the conventional output buffer circuit are determined at the design and manufacturing stages. However, the cause of electromagnetic radiation noise is closely related not only to the integrated circuit chip itself, but also to external factors such as the length and routing of signal lines connected to the integrated circuit chip. There was a problem that the effect could not be exhibited.

Further, in order to change the characteristics of the output buffer, it is necessary to change the output buffer at least from the design and manufacturing stages. This is not a typical method.

The present invention has been made under such a background, and an object of the present invention is to provide an output buffer circuit capable of adjusting a current driving capability and an output waveform characteristic after mounting.

[0017]

SUMMARY OF THE INVENTION An output buffer circuit according to the present invention has an output stage including a P-channel transistor and an N-channel transistor, one of the outputs of which are connected to each other, and an output signal input to the gate of each transistor.
At least each gate control logic circuit
The control logic circuit controls the DATA signal, the EN signal, and the waveform control.
Control signal is input and the state of DATA signal and EN signal
ON / OFF of the output signal is determined accordingly, and further waveform control
Extra resistor inside control logic circuit by turning on signal
And connect it to the gate of the transistor to change the output signal.
The rising and falling slopes during
Is so that configuration and adapted to control the output waveform of the transistor of the output stage.

The output buffer circuit of the present invention also includes a first P-channel transistor having one of its outputs connected to each other.
Transistor, a first N-channel transistor and a second
P-channel transistor and second N-channel transistor
An output stage including a first P-channel transistor and a first
Gate of each transistor of one N-channel transistor
Gate control logic for inputting a first output signal to each
Circuit, second P-channel transistor and second N-channel
The second output is connected to each gate of each transistor of the
And at least each logic gate for inputting a force signal.
The gate control logic circuit includes a DATA signal, an EN signal, and a signal.
Live waveform control signal is input, DATA signal and EN
ON / OFF of the first output signal is determined according to the state of the signal
And the control logic circuit is turned on by turning on the waveform control signal.
Insert extra resistor inside the transistor gate
Rising gradient and rising when the first output signal changes
It is configured to make the descending slope gentle.
The processing gate is for the DATA signal, EN signal and drive waveform
The control signal is input and the drive waveform control signal is turned on.
A second P-channel transistor and a second N-channel transistor.
Second output signal for turning off each of the channel transistors
The output of the output stage transistor
Waveform and drive ability can be controlled.

[0019]

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an output buffer circuit according to the present invention will be described below in detail with reference to FIGS.

(First Embodiment) FIG. 1 is a circuit diagram of a first embodiment of the present invention. This circuit is an example of a three-state output buffer circuit, and includes first to third inverters A10 and A1.
2, A13, first to third NAND gates A11, A1
4, A15, first and second NOR gates A16, A
17, first and second P-channel transistors TP1
0, TP11, first and second N-channel transistors TN10, TN11, and an output terminal P10 are connected as shown, and controlled by a DATA signal, an EN signal, and a transistor selection signal (hereinafter, referred to as a SEL1 signal). You.

In such a configuration, the EN signal is "
When the output is 0, the output of the first NAND gate A11 and the output of the third inverter A13 are both "1", and the output of the second inverter A12 is "0".
The outputs of the D gates A14 and A15 are both "1", and the P-channel transistors TP10 and TP11 are both turned off.

At the same time, each of the NOR gates A16, A1
7 are both "0", the respective N-channel transistors TN10 and TN11 are also turned off, and the output terminal P10
Is Hi-Z.

Next, when the EN signal is "1" and SEL
When the 1 signal is "0", the output of the first inverter A10 is "1", the output of the first NAND gate A11 is "0", and the output of the second inverter A12 is "1".
1 ". The output of the third inverter A13 is" 1 ".
0 ", so that the second and third NAND gates A14,
A15 and each NOR gate A16, A17 are DATA
The output level is determined by the signal.

Assuming that the DATA signal is "0", the outputs of the second and third NAND gates A14 and A15 and the NOR gates A16 and A17 are both "1", and the P-channel transistors TP10 and TP11 are both Off,
Conversely, since the N-channel transistors TN10 and TN11 are both turned on, the output level of the output terminal P10 becomes "
0 ". At this time, the drive current value driven from the output terminal P10 is the N-channel transistor TN1
0 and TN11.

When the DATA signal is "1", N
AND gates A14, A15, NOR gates A16, A
The outputs 17 are both "0", the P-channel transistors TP10 and TP11 are turned on, and conversely, the N-channel transistors TN10 and TN11 are turned off, so that the output level of the output terminal P10 is "1". At this time, the drive current value driven from the output terminal P10 is the sum of the P-channel transistors TP10 and TP11.

When the EN signal is "1" and the SEL1 signal is "1", the output of the first inverter A10 is "1".
0 ", the output of the first NAND gate A11 becomes" 1 ", so that the output of the second NOR gate A17 becomes" 0 ",
Further, since the output of the second inverter A12 becomes “0”, the second P-channel transistor TP11 and the second N-channel transistor TN are independent of the level of the DATA signal.
11 are both turned off.

The output of the third inverter A13 is "
Since it is "0", the outputs of the third NAND gate A15 and the first NOR gate A16 are determined by the DATA signal as in the case where the SEL1 signal is "0".

When the DATA signal is "0", the third N
Output of AND gate A15, first NOR gate A16
Are both "1", the first P-channel transistor TP10 is turned off, and the first N-channel transistor TN10 is turned on.
0 ". At this time, the transistor driving the output terminal TP10 is the first N-channel transistor T.
Only N10 is provided, and the current drive capability is reduced by the amount of the second N-channel transistor TN11 as compared with the case where the SEL1 signal is "0".

Similarly, when the DATA signal is "1",
As compared with the case where the SEL1 signal is "1", the current drive capability is reduced by the amount of the second P-channel transistor TP11.

As described above, according to the present embodiment, the second P
In addition, the current drive capability is relatively reduced by the provision of the N-channel transistors TN11 and TP11, and the current drive capability can be changed even during operation. This makes it possible to reliably suppress electromagnetic radiation noise.

(Second Embodiment) FIG. 2 is a circuit diagram showing a second embodiment of the present invention. This circuit is also an example of a three-state output buffer circuit, and a P-channel for inputting a DATA signal, an EN signal, and a waveform control signal (hereinafter, referred to as a SEL2 signal) and controlling a signal output from an OUT terminal. Control logic circuit for N-channel and N-channel transistors
TYPEA, TYPEB and a P-channel transistor TP20 having the gate of the output signal of the P-channel transistor gate control logic circuit TYPEA and the source connected to VDD.
And the gate control logic circuit TYPE for N-channel transistor
An N-channel transistor TN20 having the output signal of B as a gate input and a source connected to GND;
An output terminal TP20 is connected to each drain output of the channel transistors TP20 and TN20.

FIG. 3 is a detailed circuit diagram of the P-channel transistor gate control logic circuit TYPEA, and FIG. 4 is a detailed circuit diagram of the N-channel transistor gate control logic circuit TYPEB.

First, referring to FIG. 3, a gate control logic circuit TYPEA for a P-channel transistor includes a first inverter A30 for inverting the SEL2 signal, an EN signal and an SE signal.
First NAND gate A3 for NANDing with L2 signal
1 and the NAND of the EN signal and the first inverter A30
And a first NAND gate A32
Second inverter A33 for inverting the output of gate A31
A third inverter A34 for inverting the output of the second NAND gate A32, a first N-channel transistor TN30 having a DATA signal as a gate input, and having a source connected to GND, and an output of the second inverter A33. As the gate input, the source of the second N-channel transistor TN31 connected to the drain of the first N-channel transistor TN30, the output of the third inverter A34 as the gate input, and the source of the first N-channel transistor TN30 And a third N-channel transistor TN32 to which the drain of the third N-channel transistor TN32 is connected to the drain of the third N-channel transistor TN32 and a DATA signal to the gate input. , VDD is connected to the source First P-channel transistor T
P30, a second P-channel transistor TP31 having an EN signal as a gate input and a source connected to VDD,
A third P-channel transistor TP32 having GND as a gate input and having the source connected to the drain of the second N-channel transistor TN31.

The third N-channel transistor TN32,
The drain outputs of the first N-channel transistor TN30, the N-channel depletion type transistor TND30, and the first to third P-channel transistors TP30 to TP32 are respectively connected to each other and output as an OUT signal A35 to the outside of the block.

Here, the functions of the N-channel depletion type transistor TND30 and the third P-channel transistor TP32 will be described.

The N-channel depletion type transistor TND30 is a transistor having a negative threshold voltage, unlike an enhancement type transistor having a positive threshold voltage.
Therefore, in the case of the circuit of FIG. 3, the gate input of the N-channel depletion type transistor TND30 is VDD.
Therefore, it is always on. Also, the third P-channel transistor TP32 is always on because the gate input is GND. That is, these gates function not for logic but as resistors generally used in an integrated circuit having a CMOS structure.

Next, the circuit operation will be described. First, when the SEL2 signal is "0" in FIG.
The output of the ND gate A31 is "1", the output of the second inverter A33 is always "0", and the output of the first inverter A30 is "1".
The output of the ND gate A32 and the third inverter A34 is E
N signal, in this case the third inverter A
The output level of 34 matches the level of the EN signal.

At this time, the P-channel transistor gate control logic circuit TYPEA includes the first and second P-channel transistors TP30 and TP31, and the first and third N-channel transistors TP30 and TP31.
The well-known NA of the DATA signal and the EN signal formed by the channel transistors TN30 and TN32
It becomes an ND gate.

Conversely, when the SEL2 signal is "1", the output of the first inverter A30 is "0",
The output of the gate A32 is "1" and the third inverter A34
Is "0", the third N-channel transistor TN32 is turned off. The output of the first NAND gate A31 is EN as the SEL2 signal is "1".
The output of the second inverter A3
The output level of 3 matches the EN signal.

The N-channel depletion type transistor TND30 and the third P-channel transistor T
As described above, both P32 function as resistors, so that the P-channel transistor gate control logic circuit TYPEA when the SEL2 signal is "1" also has the DATA signal and EN signal.
It becomes a NAND gate with a signal. SEL2 signal is "0"
The difference from the above case is that the N-channel depletion type transistor TND30 and the third P-channel transistor TP3 are connected between the OUT signal output A35 and the bus between GND.
2 is that the resistor formed by 2 is inserted extra.

Therefore, when the SEL2 signal is "1", P
The output characteristic of the OUT signal A35 of the channel transistor control logic circuit TYPEA has a gentler falling characteristic when the signal SEL2 changes from "1" to "0" than when the signal SEL2 is "0".

Next, the gate control logic circuit TYPEB for an N-channel transistor will be described. Referring to FIG. 4, the gate control logic circuit TYPEB includes a first inverter A40 for inverting the EN signal, a second inverter A41 for inverting the SEL2 signal, and a first inverter A for NANDing the EN signal and the SEL2 signal. NAND gate A42 and E
A second NAND gate A43 for NANDing the N signal with the second inverter A41; a first P-channel transistor TP40 having a DATA input as a gate input and a source connected to VDD; a first NAND gate A42 , A second P-channel transistor TP41 having a source connected to the drain of the first P-channel transistor TP40, and a second NAND gate A
A third P-channel transistor TN42 having an output of 43 as a gate input, a source connected to the drain of the first P-channel transistor TP40, a GND as a gate input, and a second P-channel transistor TN4 as a source.
A fourth P-channel transistor TP43 connected to the drain of the first N-channel transistor T1 and a first N-channel transistor T3 connected to the source GND with the DATA signal as a gate input.
N40, the output of the first inverter A40 as a gate input, a second N-channel transistor TN41 having a source connected to GND, a VDD as a gate input, and a source connected to a drain of a second P-channel transistor TP41. And an N-channel depletion type transistor TND40.

The first N-channel transistor TN40,
Second N-channel transistor TN41, N-channel depletion type transistor TND40, and third and fourth P-channel transistors TP42, TP43
Are all output to the OUT output signal line A44 and output outside the block.

In this case, similarly to the P-channel transistor gate control logic circuit TYPEA, both the N-channel depletion type transistor TND40 and the fourth P-channel transistor TP43 have a function as a resistor.

Next, the circuit operation will be described. First, in FIG. 4, when the SEL2 signal is “0”, the first NA
Since the output of the ND gate A42 is "1", the second P
Since the channel transistor TP41 is always turned off and the output of the second inverter A41 is always "1", the output of the second NAND gate A43 is always an inverted output of the EN signal.

The second N-channel transistor TN4
The gate input of 1 also receives the EN signal via the first inverter A40. Therefore, the SEL2 signal becomes "
When it is 0 ", it functions as a NOR logic gate for NORing the DATA signal and the inverted signal of the EN signal.

On the other hand, when the SEL2 signal is "1", the output of the second inverter A41 is "0", the output of the second NAND gate A43 is "1", and the third P-channel transistor TP43 is always off. Also, the first NAND gate A42 outputs an inverted signal of the EN signal. At this time, the gate input of the second N-channel transistor TN41 also becomes the inverted signal of the EN signal. Logic circuit
TYPEB functions as a NOR logic gate.

However, the second P-channel transistor TP
Since a resistor composed of an N-channel depletion type transistor TND40 and a fourth P-channel transistor TP43 is inserted between the drain output of the P.41 and the OUT signal line A44, the output from the OUT signal line A44 becomes " The output characteristic when changing from “0” to “1” is S
It becomes slower than when the EL2 signal is "0".

The output buffer circuit shown in FIG. 2 using such P-channel and N-channel transistor gate control logic circuits TYPEA and TYPEB as the gate control of the last-stage transistor has a characteristic of each gate input signal. When the SEL2 signal is "0", it functions as a normal three-state output buffer.
In the case of "1", when the output of the P-channel transistor gate control logic circuit TYPEA, which becomes the gate input of the P-channel transistor TP20, changes from "1" to "0", SEL2
The signal changes more slowly than when the signal is "0", and N
When the output of the gate control logic circuit for N-channel transistor TYPEB, which becomes the gate input of the channel transistor TN20, changes from "0" to "1" and the SEL2 signal changes to "0", the output changes gradually from the output terminal TP20. When the SEL2 signal is "1" as compared with the case where the SEL2 signal is "0", the rising and falling gradients of the output signal change gradually.

(Third Embodiment) FIG. 5 is a circuit diagram showing a third embodiment of the present invention, which is a combination of the first and second embodiments. In this embodiment, a drive waveform selection signal having both functions of a transistor selection signal and a waveform control signal is referred to as a SEL3 signal.

Referring to FIG. 5, the output buffer circuit of the present embodiment includes a first inverter A for inverting the SEL3 signal.
AND of the inverter A50 with the EN signal
And a second inverter A52 for inverting the output of the NAND gate A51.
And N between the output of the inverter A52 and the DATA signal.
A second NAND gate A53 that takes an AND
A NOR gate A54 for NORing the output of the AND gate A51 and the DATA signal, and a gate control logic circuit TYPEA for P-channel and N-channel transistors for inputting the DATA signal, the EN signal and the SEL3 signal to control each output signal OUT. , TYPEB, the output signal OUT of the P-channel transistor gate control logic circuit TYPEA as a gate input, the output of a first P-channel transistor TP50 having VDD as a source input, and the output of a second NAND gate A53 as a gate input, A second P-channel transistor TP51 having VDD as a source input, a first N-channel transistor TN50 having an output signal OUT of an N-channel transistor gate control logic circuit TYPEB as a gate input and GND as a source input, and a NOR gate The output of A54 is used as a gate input, and GN The second of N to the source input
Channel transistor TN51 and each transistor TP
50, TP51, TN50, and TN51 each include an output terminal P50 to which a drain output is connected.

Here, each gate control logic circuit TYPE
A and TYPEB are the same as those shown in FIGS. 3 and 4 described in the second embodiment.

Next, the circuit operation will be described. In FIG. 5, when the SEL3 signal is "0", the respective SEL signal inputs of the gate control logic circuits TYPEA and TYPEB are "0".
Therefore, at this time, the gate control logic circuit TYPEA for the P-channel transistor outputs the N signal of the DATA signal and the EN signal.
The gate control logic circuit TYPEB for the N-channel transistor becomes an AND gate, and becomes a NOR gate for the DATA signal and the inverted signal of the EN signal. Therefore, the output buffer circuit at this time is SEL in the output buffer circuit shown in FIG.
The buffer is the same as when one signal is "0".

On the other hand, when the SEL3 signal is "1", the output of the first inverter A50 is "0" and the first NAN
Since the output of the D gate A51 becomes "1", the output of the NOR gate A54 becomes "0", and the second N-channel transistor TN51 is turned off. Further, the output N-channel transistor TN51 of the second inverter A52 is turned off. The output of the second inverter A52 is "0".
And the output of the third NAND gate A53 becomes "1", so that the second P-channel transistor TP51 is also turned off.

Therefore, at this time, the output buffer circuit of FIG. 5 has the same configuration as the output buffer circuit shown in the second embodiment. Therefore, when the SEL3 signal is "1", SEL3
Compared with the case where the three signals are "0", the current drive capability from the output terminal P50 is reduced, and the output waveform characteristic is also moderate.

[0057]

As described above, in the present invention, the number of transistors to be turned on is changed by the transistor selection signal, so that the current drive capability can be adjusted even during the operation of the output buffer circuit. .

In addition, since the gate control logic circuit is provided and the rising and falling gradients of the output of the transistor to be turned on are made gentle, generation of noise at the time of switching binary data is suppressed.

Further, the current drive capability control and the output waveform control are combined so that the level and waveform characteristics of the signal guided to the output terminal can be adjusted arbitrarily. Driving capability and characteristics effective for reducing electromagnetic radiation noise can be set as required.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an output buffer circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a gate control logic circuit for a P-channel transistor used in a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a gate control logic circuit for an N-channel transistor used in a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of an output buffer circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a conventional output buffer circuit.

[Explanation of symbols]

TP10, TP11, TP20, TP30, TP31,
TP32, TP40, TP41, TP42, TP43,
TP50, TP51, TP60 ... P-channel transistors TN10, TN11, TN20, TN30, TN31,
TN32, TN40, TN41, TN50, TN51,
TN60: N-channel transistor A10, A12, A13, A30, A33, A34, A
40, A41, A50, A60 ... Inverters A11, A14, A15, A31, A32, A42, A
43, A51, A53, A61 ... NAND gates A16, A17, A54, A62 ... NOR gates P10, P20, P50, P60 ... output terminals A35, A44 ... OUT output signals TYPEA, TYPEB ... gate control logic circuits DATA signals ... binary Data EN signal: Output buffer enable signal SEL1 signal: Transistor selection signal SEL2 signal: Waveform control signal SEL3 signal: Drive waveform selection signal

Claims (2)

(57) [Claims] An output stage including a p-channel transistor and an n-channel transistor having one of their outputs connected to each other; and an output signal connected to a gate of each of the transistors.
At least each gate control logic circuit
Each of the gate control logic circuits outputs a DATA signal, EN signal.
The signal and the waveform control signal are input, and the DATA signal and the
ON and OFF of the output signal according to the state of the EN signal.
And the control is performed by turning on the waveform control signal.
Insert an extra resistor inside the control logic circuit to
Connects to the gate of the transistor and rises when the output signal changes
It is configured to reduce the slope and falling slope.
Is, the output buffer circuit, wherein the this <br/> for controlling the output waveform of the transistor of the output stage. 2. A first circuit having one of its outputs connected to each other .
P-channel transistor and first N-channel transistor
A transistor, a second P-channel transistor and a second N-channel transistor.
An output stage including a channel transistor;
And a first N-channel transistor
The first output signal to the gate of each transistor
Input gate control logic circuits and said second P-channel
A transistor and each of the second N-channel transistors
Inputting a second output signal to each gate of the transistor
A logic gate, and each of said gate control logics
Circuit controls DATA signal, EN signal and drive waveform
A signal is input and the DATA signal and the EN signal are
On / off of the first output signal is determined according to the state.
And the control logic is turned on by turning on the waveform control signal.
Insert an extra resistor inside the circuit to
Rises when the first output signal changes.
It is configured to reduce the slope and falling slope.
Each of the logic gates is connected to the DATA signal,
The EN signal and the drive waveform control signal are input,
And, when the drive waveform control signal is turned on, the second
P-channel transistor and the second N-channel transistor
The second output signal, which turns off each of the transistors,
An output of the output stage transistor
An output buffer circuit for controlling a waveform and a driving capability .