JP3045413B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device . More particularly in the semiconductor device capable of non-destructive readout using a ferroelectric film, a semiconductor device and a method with improved patterning of the ferroelectric film.

[0002]

2. Description of the Related Art A conventional semiconductor memory device using a ferroelectric capacitor has a structure as shown in FIG. In this figure, 1 is a semiconductor substrate, 2 is a source region, 3 is a drain region, 4 is a field oxide film for element isolation, 5 is a gate insulating film, 6 is a channel region, 7 is a ferroelectric film, and 8 is a gate. Electrode film, 9 is an interlayer insulating film, 10,
Reference numerals 11 and 12 denote aluminum wirings of source, gate and drain electrodes, respectively, and reference numeral 13 denotes a passivation film.

In the structure of this conventional example, when a voltage is applied between the gate electrode film 8 and the semiconductor substrate 1 to polarize the ferroelectric, the ferroelectric has a hysteresis characteristic. The remnant polarization remains, and the polarization remaining in the ferroelectric film 7 by applying a voltage between the source and the drain induces electrons or holes in the channel region 6 on the surface of the semiconductor substrate 1. ON during,
An OFF switching action occurs, and the stored data can be read out nondestructively.

In the conventional method of manufacturing a semiconductor memory device, a field oxide film 4 is first formed on a semiconductor substrate 1, a gate insulating film 5, a ferroelectric film 7, and a gate electrode film 8 are formed.
After patterning such that they are formed on the channel region 6, impurity ions are implanted using the mask as a mask to form the source region 2 and the drain region 3. After that, an interlayer insulating film 9, electrodes and the like are formed.

[0005]

However, the ferroelectric used for this semiconductor memory element is usually PZT (Pb (Zr _1-x Ti _x ) O).
₃ ) A perovskite structure such as PbTiO ₃ is used because of its large spontaneous polarization, but these materials have poor workability by etching or the like.

Therefore, dry etching such as ion milling must be used to perform fine processing. However, since ion milling is performed by ion beam etching such as argon ion, the ferroelectric film and other insulating materials are used. It is not possible to obtain a large selection ratio with a film or a semiconductor material. Therefore, it is easy to damage surrounding semiconductor materials. If the ferroelectric film 7 formed on the particularly thin gate insulating film 5 is processed by dry etching, if the etching is performed too long, the gate insulating film 5 is broken and the semiconductor substrate 1 is damaged, thereby deteriorating the characteristics of the transistor. If the etching is insufficient, there is a problem that the ferroelectric film 7 remains.

If wet etching is used as an etching method that does not cause much damage, sufficient fine processing cannot be performed, and it cannot be used for a recent semiconductor device that requires processing on the order of submicron, which is a super LSI. .

In view of such circumstances, an object of the present invention is to enable processing of a ferroelectric which is difficult to perform fine processing without affecting the characteristics of a semiconductor device .

[0009]

The semiconductor device <br/> according to the present invention, there is provided a means for solving] is source over source region, drain region and channel region form
Semiconductor substrate formed, and the source region and the drain
A low dielectric constant film formed on the region, and
A ferroelectric film formed in the opening of the low dielectric constant film,
The low dielectric constant is formed on the ferroelectric film,
And an electrode film extending on the film .

[0010] Preparation of a semiconductor device of the present invention is formed in the above-mentioned structure, in order not to damage the semiconductor material during the etching, the step of patterning the protective film on the channel area of the semiconductor substrate, wherein that Yusuke forming a source region and a drain region by diffusing impurities into both sides of the protective film, the different properties and the protective film on the source region and the drain region of the formed semiconductor substrate
Forming a low dielectric constant film, and exposing the protective film to be exposed.
Planarizing the low dielectric constant film with
By removing the protective film and exposing the surface of the semiconductor substrate,
Step of forming an opening on a channel region in a low dielectric constant film
When the steps that constitute the form or directly ferroelectric film via a gate insulating film on a semiconductor substrate surface and the exposed, is planarized as before Symbol low dielectric constant film is exposed, the opening of the low dielectric constant film
A step of leaving the ferroelectric film in the mouth, is intended to include a step of forming an electrode film on the ferroelectric film.

[0011]

According to the present invention, a dielectric film having a low dielectric constant (hereinafter, referred to as a low dielectric constant film) is formed on a source / drain region, and then a ferroelectric film is deposited thereon to form a ferroelectric film on a channel region. Since the body film surface and the low dielectric constant film surface are formed so as to be on the same surface, the ferroelectric material is excessively processed by dry etching with a small selectivity such as ion milling and strong processability. However, only a part of the thick low-k film is etched, and the semiconductor material itself is not etched,
There is no effect on device characteristics.

According to the present invention, the surface of the ferroelectric film formed on the channel region and the low dielectric constant film formed on the surrounding source and drain regions are formed so as to be flush with each other. Since the electrode film is formed on the low dielectric constant film on the surface, the ferroelectric film works effectively from end to end on the channel region sandwiched between the source and drain regions (the low dielectric constant film has a dielectric constant of Is small, so that it does not act as a capacitor even if an electrode film is formed on the upper portion). Moreover, since the electrode film is formed in parallel with the semiconductor substrate, the direction of polarization becomes uniform, and a high capacitor is formed efficiently.

[0013]

Next, the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram showing a cross-sectional structure of a semiconductor memory device according to one embodiment of the present invention. In FIG.
Refers to the same part as

In this embodiment, low dielectric constant films 14 and 15 are formed on the source region 2 and the drain region 3, respectively, and thereafter, a ferroelectric film 7 is formed and a ferroelectric film on the channel region 6 is formed. The body film 7 and the low dielectric constant films 14 and 15 are formed so as to be on the same plane, and the ends of the body film 7 and the low dielectric constant
The electrode film 8 is formed so as to be on the upper surface 15. The low dielectric constant films 14 and 15 are, for example, a silicon oxide film or a silicon nitride film having a relative dielectric constant of about 4 to 7, which is conveniently used in the manufacture of a normal semiconductor device, and a thickness of 0.5 to 0.5. μm
Is formed.

The ferroelectric film 7 is made of, for example, PbTiO ₃ , PZT
(Pb (Zr _1-x Ti _x ) O ₃ ), PLZT ((Pb _1-x La _x ) (Zr _1-y
A material having an oxide perovskite structure having a large spontaneous polarization such as Ti _y ) _{1-x / 4} O ₃ ) and having a relative dielectric constant of about 100 to 2000 is used. The ferroelectric film 7 adheres to the entire surface of the semiconductor substrate by, for example, a sputtering method, a CVD method, or a sol-gel method, and then flattens the surface to expose a low dielectric constant film by dry etching such as ion milling. Back etching until the ferroelectric film and the low dielectric constant film are formed on the same plane.

Since this back etching is performed on the low dielectric constant films 14 and 15 at the interface with the ferroelectric film, even if dry etching is performed, the semiconductor substrate 1 may be damaged or the ferroelectric film may be damaged. The film is not removed and left. That is, the place to completely remove the ferroelectric film is a source such as an oxide film,
Since the low dielectric constant film portion is formed on the drain regions 2 and 3, even if the etching is performed excessively, only a part of the thick oxide film or the like is removed. Is not affected.

On the other hand, the end of the electrode film 8 formed on the channel region 6 sandwiched between the source region and the drain region extends over the channel region 6 so that the source region 2 and the drain region 3
Although it extends above the low dielectric constant films 14 and 15 above, even if a voltage is applied to the low dielectric constant films 14 and 15 during writing actually used as a storage element, the polarization of this portion is almost eliminated. Without
Does not work as a capacitor. Therefore, low dielectric constant film
By extending over the ferroelectric film, the end-to-end of the ferroelectric film can be effectively used as a capacitor.

Next, a method of manufacturing the semiconductor memory device will be described. 2 to 8 are cross-sectional views showing the steps of manufacturing a semiconductor memory device according to one embodiment of the present invention.

First, as shown in FIG. 2, a field oxide film 4 for element isolation is formed on a semiconductor substrate 1 by patterning with a nitride film or the like, and then a protective film 16 is formed by patterning at a place where a channel region 6 is to be formed. I do. As a specific example, CVD is performed on the p-type semiconductor substrate 1 on which the field oxide film 4 is formed.
By a gaseous reaction between SiH ₂ Cl ₂ gas and NH ₃ gas at about 750 ° C. by a method, a nitride film of 0.5 μm was formed, and plasma etching was performed to form a protective film 16.

Next, as shown in FIG. 3, impurities are diffused on both sides of the protective film 16 to form a source region 2 and a drain region 3. As a specific example, As ions are implanted at a dose of 5 × 10 ¹⁵ cm ⁻² by ion implantation,
Diffusion was performed by heat treatment for 30 minutes to form an n ⁺ -type source region 2 and a drain region 3.

Next, as shown in FIG. 4, a low dielectric constant film 17 having a property different from that of the protective film 16 is formed on the entire surface of the semiconductor substrate. As a specific example, SiH ₄ gas and N ₂
O 2 gas was introduced to cause a gas phase reaction at about 800 ° C. to form a silicon oxide film of about 0.6 μm.

After that, as shown in FIG. 5, the film formed on the surface of the semiconductor substrate is etched back so as to be flat, and the protective film 16 is exposed. As a specific example, by etching by the reactive ion etching (hereinafter, referred to as RIE) method, the surface is etched to the same thickness, and the protection film 16 is exposed, so that the low dielectric constant film 14, which is a silicon oxide film, is formed around the protection film 16. 15 were formed on the source region 2 and the drain region 3.

Next, as shown in FIG.
15 and the field oxide film 4 are not corroded, and only the protective film 16 is corroded.
The semiconductor substrate 1 is exposed. As a specific example, heat H ₃ PO
Protective film that is a nitride film by etching with ₄ solutions
Only 16 is removed by corrosion, and the field oxide film 4, which is a silicon oxide film, and the low dielectric constant films 14 and 15 are left as they are, and the protective film 16 is removed.
The surface of the semiconductor substrate 1 below was exposed.

Subsequently, as shown in FIG. 7, a gate insulating film 5 and a ferroelectric film 7 are sequentially formed, and the surface is flattened. As a specific example, a silicon oxide film of about 0.6 μm was formed by a CVD method using TEOS, and then PbTiO ₃ was formed to a thickness of 0.5 μm by sputtering. After that, resist 17 on the surface
Was applied to eliminate the concave portions and flattened. If the ferroelectric film and the semiconductor substrate do not react, the gate insulating film 5
Is unnecessary.

Next, as shown in FIG. 8, the low dielectric constant films 14 and 15 are exposed by etching back from the flattened surface, and the ferroelectric film 7 on the channel region 6 and the exposed low dielectric constant film are exposed. The films 14 and 15 are formed so as to be flush with each other. Thereafter, an electrode film 8 is formed on the ferroelectric film 7. It is desirable that the end of the electrode film 8 is formed on the low dielectric constant films 14 and 15.

As a specific example, the surface of the substrate was etched back by dry etching by ion milling. Since the etch back is etched by the same thickness from the entire surface of the substrate even if the material is different, the resist portion 17 and the ferroelectric film 7 on the source and drain regions 2 and 3 are also etched by the same thickness. Since the surface is flattened, the etch-back is stopped when the low dielectric constant films 14 and 15 are exposed, so that the ferroelectric film 7 and the low dielectric constant films 14 and 15 are exposed.
The same surface as was formed.

During the back etching, when the gate insulating film 5 is formed, an insulating film is also formed on the low dielectric constant films 14 and 15, and this insulating film has the same low dielectric constant as the low dielectric constant film. Since it is a film, it may remain. Since this insulating film is a thin film, it may be etched at the time of back etching, but the base is a thick low dielectric constant film, the semiconductor region is not damaged, and the characteristics are not affected at all. Was.

Thereafter, platinum metal was deposited by sputtering and etched by RIE to form an electrode film (gate electrode film) 8. At this time, etching was performed so that the end of the electrode film 8 was located on the low dielectric constant films 14 and 15.

Finally, the interlayer insulating film 9 is formed, the aluminum wiring of the source electrode 10, the gate electrode 11, and the drain electrode 12 is formed by a method performed in a normal semiconductor process, and the passivation film 13 is formed. A semiconductor memory element having a structure as shown in FIG. 1 can be formed. As a specific example
A silicon oxide film is formed as an interlayer insulating film 9 by a CVD method, an electrode contact hole is punched by an RIE method, and an aluminum film is formed by sputtering to form each electrode.
Further, a silicon oxide film was formed as a passivation film by a CVD method.

[0030]

As described above, according to the present invention, a low dielectric constant film formed on a source region and a drain region is subjected to fine processing, and a ferroelectric film is formed between the films to form the low dielectric constant film. Since it is formed by etching back so as to be on the same plane as the film, there is no need to perform fine processing for forming capacitors by etching the ferroelectric, and unnecessary portions of the ferroelectric film can be removed by a thick low Since the back etching is performed on the dielectric constant film, a high-performance and high-performance semiconductor memory element in which processing problems are solved can be formed without damaging the semiconductor region.

Further, according to the present invention, the ferroelectric film and the low dielectric constant films 14 and 15 on the surrounding source and drain regions are formed on the same plane, and the electrode film is formed on the surface. ,
The electrode film 8, the ferroelectric film, and the semiconductor substrate are formed in a completely parallel state, and the polarization directions can be formed completely in the same direction, so that a capacitor can be formed efficiently. As a result, a large polarization can be obtained even at a low voltage, and a semiconductor memory element with high characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory cross-sectional view showing a structure of a semiconductor memory element according to one embodiment of the present invention.

FIG. 2 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 3 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 4 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 5 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 6 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 7 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 8 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 9 is an explanatory cross-sectional view showing a structure of a conventional semiconductor memory element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Source region 3 Drain region 6 Channel region 7 Ferroelectric film 8 Electrode film 10 Source electrode 11 Gate electrode 12 Drain electrode 14, 15 Low dielectric constant film

Claims (2)

(57) [Claims] 1. A source over source region, drain region and channel <br/> a semiconductor substrate Le region is formed, a low induced formed in the source region and the drain region
An electric conductivity film and an opening formed in the low dielectric constant film on the channel region.
And a ferroelectric film formed on the ferroelectric film, the end of which has the low dielectric constant.
A semiconductor device having an electrode film extending over the film . 2. A process of patterning the protective film on the semiconductor substrate in the channel area on the steps of forming a source region and a drain region by diffusing impurities into both sides of the protective layer, the source region and the drain region forming a low dielectric constant film formed on a semiconductor substrate that have a different nature and the protective layer, planarizing the low dielectric constant film to the protective film is exposed
A step to remove the protective film the exposed, exposure of the semiconductor substrate surface
The opening on the channel region in the low dielectric constant film.
Forming, is planarized so that the step that forms the form or directly ferroelectric film via a gate insulating film, the previous SL low dielectric constant film is exposed to said exposed semiconductor substrate surface, wherein the low dielectric constant A method for manufacturing a semiconductor device , comprising: a step of leaving the ferroelectric film in an opening of a film; and a step of forming an electrode film on the ferroelectric film.