JP3043823B2 - PCM audio recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a digital audio recording apparatus, in particular, a super VHS (S-VHS) video tape recorder (VTR), and records an audio signal in a pulse code modulation (PCM) system. The present invention relates to a PCM audio recording device.

[0002]

2. Description of the Related Art In a conventional VTR, the recording and reproduction of an audio signal, which is initially started with a fixed head system, is performed by a helical scan in order to cope with a reduction in tape speed in a long recording mode and audio multiplexing of television broadcasting. The recording and reproduction of the FM system, that is, the so-called HiFi (HiFi) audio system has been shifted. For example, in the VHS-HiFi method, a method of FM-modulating each carrier of 1.3 MHz and 1.7 MHz with a stereo audio signal and recording the audio FM signal in a deep layer by a rotary head of ± 30 degrees azimuth is adopted.

[0003]

The above-mentioned conventional VTR
In the HiFi audio system, the reproduced FM signal is not completely continuous because the reproduced signal of the two heads is spliced by the head switching signal. For this reason,
There is a problem that the reproduced audio signal is distorted every 30 Hz in accordance with the head switching signal.

Further, with the enhancement of digital audio sources such as B-mode (PCM) satellite broadcasting and the like, a VTR audio signal recording / reproducing apparatus capable of obtaining sound quality equivalent to that of a compact disk (CD) and digital audio tape recorder (DAT) system. Was eagerly awaited.

[0005] In order to solve the above-mentioned problems, the present invention reduces the memory capacity required for interleaving in subframe units for error detection and correction, thereby reducing the circuit scale. It is an object of the present invention to provide a PCM audio recording device provided with an interleave circuit that enables high-speed interleave processing.

[0006]

In order to solve the above-mentioned problems, according to the present invention, a signal of a predetermined number of sub-frame units is generated from a digital audio signal of one TV frame, and is used for error detection and correction. Interleaving means for interleaving a signal of the number of subframes one less than one TV frame in a frame and interleaving a signal of one subframe between frames is provided, and the interleaving means is one interleaving means for one TV frame.
The first and second memories for storing the signal of the next smaller number of subframes, the third memory for storing the signal of one subframe unit, and the signal writing / reading processing of the first to third memories are controlled. An address conversion circuit for storing a signal in a subframe unit to be interleaved in a frame in one of a first and a second and reading the stored signal from the other memory to write and read the signal Interleave processing within a frame is performed by controlling the position and timing, and a signal in a subframe unit for performing interleaving between frames is written in a third memory, and read timing of a signal written in the third memory To perform interleave processing between frames.

[0007]

FIG. 10 shows an interleave circuit 8 according to an embodiment of the present invention. In FIG. 10, a RAM for storing interleaved data in a block in subframe units.
The auxiliary RAMs 81 and 82 interleave data for 20 sub-frames under the control of the inter-block address conversion circuit 83 during the 2TV frame period.
84, and transfer to RAMs 85 and 86. RAM 85, 86
Has a memory capacity corresponding to one sub-frame, and the RAMs 85 and 86 each have a memory capacity corresponding to nine sub-frames. Accordingly, 20 for 2 TV frames subjected to interleaving between blocks
Auxiliary RAM 84, RAM 85, 8 for subframe
The total capacity of 6 is for 19 subframes. The inter-block interleaving is performed under the control of the inter-block address conversion circuit 83 with this much smaller memory capacity than in the prior art.

[0008] The sub-frames subjected to interleaving between blocks are stored in the RAM 85 and the auxiliary RA in TV frame units.
M84, or a sequential synchronization / subcode addition circuit 87 from the RAM 86 and the auxiliary RAM 84 via the selector S83.
Is output to As described above, the synchronization / subcode addition circuit 87 assigns one symbol of the synchronization code Sync to each input block (31 symbols / block, see FIG. 3).
Symbol subcode W1, 1 symbol subcode W
The parity code of 2 and 1 symbol is added and output to the M ² conversion circuit 9.

[0009]

Next, an embodiment of a PCM audio recording apparatus according to the present invention will be described in detail with reference to the drawings.

[0010] In order to meet the above-mentioned demand, S-VHS V
Format related to PCM audio recording for TR
"Recording format" has been published ("JVC, prototype of VTR capable of recording digital audio signals", Nikkei Electronics, January 1990).
No. 22, issue No. 491, p. 93).

A recording format is a standard for ensuring compatibility when reproducing an audio signal.
The specification in the SC system is shown. In the figure, 48 kHz-2 channel mode (hereinafter, referred to as “48 k-mode”) is a B mode satellite broadcast (hereinafter, referred to as “BS”) or DAT.
The 32 kHz 4-channel mode corresponds to European MAC satellite broadcasting, Japanese satellite broadcasting A mode, and DAT option 3 mode. In addition, for each mode, specifications for systems other than the NTSC system are shown, but are omitted.

FIG. 2 is a diagram showing the track pattern in FIG. 1 in the case of the NTSC system. FIG. 2 (A)
1 shows a relationship between an analog audio signal and a digital audio signal obtained by sampling for one TV frame. FIG. 2B shows a track pattern of a digital audio signal deeply recorded on a video track.

FIG. 3 is a diagram showing a block format in each video track of the NTSC system.
One track is composed of a total of 156 blocks including a preamble (4 blocks), a data block (150 blocks = 5 subframes), and a postamble (2 blocks). Further, each data block includes data (31 symbols, where one symbol is 8 bits), a synchronization code SYNC.
(4EH), address subcode W1 (8 bits), I
It is shown that it is composed of a total of 35 symbols (280 bits) of the D subcode W2 (8 bits) and the subcode parity P (8 bits).

FIG. 4 is a block diagram showing an example in which the PCM audio recording apparatus according to the present invention is applied to an S-VHS VTR. Hereinafter, the 48k-mode will be described. However, when the circuit configurations and the processing contents for the signals of channel 1 (L) and channel 2 (R) are similar, only channel 1 (L) is shown. 2
The redundant circuit configuration and description of (R) are omitted.

In FIG. 4, reference numeral 1 denotes an input terminal for L and R digital audio signals, which is connected to, for example, a digital output terminal of a BS tuner. The input digital audio signal is supplied to an error correction code (ECC) adding circuit 7 via an input selector 6.

Reference numeral 2 denotes an input terminal for L and R analog audio signals. The input analog audio signal is supplied to an analog-digital (A / D) converter 5 via a low-pass filter (LPF) 3 in order to prevent aliasing during reproduction. The LPF 3 is composed of, for example, a combination of a third-order LC filter and a digital filter, or a ninth-order active filter.

Reference numeral 4 denotes a timing generation circuit. The timing generation circuit 4 operates at 52.416 MHz (or 26.2 MHz).
08 MHz), a sampling clock, a bit clock BCK, etc. are generated from the
It is supplied to the D converter 5 and each circuit block (not shown).

Reference numeral 5 denotes an A / D converter. The A / D converter converts an input analog audio signal into a digital audio signal by 16-bit linear quantization based on the sampling frequency fs, channel clock, bit clock BCK, and the like supplied from the timing generation circuit 4. The A / D converter 5 is a 1-bit A
A / D converter or a 16-bit integrating A / D converter is employed.

Reference numeral 6 denotes an input selector. Input selector 6
A / D converts A / D between a digital signal input through the input terminal 1 and an analog signal input through the input terminal 2.
Either the digital signal output from the / D converter 4 is selected, and an error correction code (ECC) adding circuit 7 is selected.
To supply.

Reference numeral 7 denotes an ECC adding circuit. The digital signal input to the ECC adding circuit 7 has 648 symbols (= 27 symbols × 24 data blocks) as one block as shown in FIG.
3240 symbols), that is, one TV frame at a time in the random access memory (RAM). For the stored data, the ECC addition circuit 7 applies 282
Parity code of a symbol, that is, a duplex Reed-Solomon code C1 (31, 27, 5) for error correction / detection,
C2 (30, 24, 7) is generated and added. Therefore,
One block has 930 symbols (= 648 + 282 symbols).

The ECC addition circuit 7
This will be described later in detail.

Reference numeral 8 denotes an interleave circuit. The interleave circuit 8 has 9300 symbols (= 1TV frame) to which a parity code has been added by the ECC addition circuit 7.
930 symbols × 5 blocks × 2 channels) are interleaved. Interleaving is a well-known method for coping with intensive loss of data in a defective portion of a tape, that is, a burst error. That is, the order of the symbols and blocks is interchanged and recorded on the tape, and the interleave is returned (de-interleaved) at the time of reproduction, thereby converting the burst error into a substantially random error, thereby facilitating data correction and correction. Is to try.

In this embodiment, the parity code C
Simultaneously with the calculation of C1 and C2, the frames O00 and E00, O01 and E01,..., O04 and E04 shown in FIG. Are formed. In addition, each of the subframes E00 to E
04, O00 to O04, etc. are rearranged by the inter-block interleaving like the track pattern shown in FIG. Further, as shown in FIG. 3, the block includes a synchronization code Sync indicating the start of the block, an address subcode W1 indicating the subframe and the block address,
Four symbols of an ID subcode W2 indicating a mode and the like and a parity code Parity of the subcodes W1 and W2 are added.

The interleave circuit 8 will be described later in detail.

Reference numeral 9 denotes a mirror-scared (M ² ) conversion circuit. M ² conversion circuit 9, the data input from the interleave circuit 8, C1 parity, and M ² converts the C2 parity subcode W1 as an initial value, converted to M ² code.
The M ² conversion limits the run length of the recording code, converts the recording code into a DC-balanced recording code, and outputs it as serial data, in order to match the differential transfer characteristic of the magnetic recording system.

The M ² conversion circuit 9 will be described later in detail.

Reference numeral 10 denotes a pre- and postamble adding circuit. The pre- and post-amble adding circuits perform the respective track data output from the M ² conversion circuit 9 (see FIG. 3).
The serial data obtained by adding four blocks of the preamble pattern (90H) and two blocks of the postamble pattern (90H) before and after the QDPSK circuit 11
Output to

Reference numeral 11 denotes a QDPSK (four-phase differential phase modulation) circuit. The QDPSK circuit 11 performs four-phase modulation using a point before the modulation point as a reference phase.

FIG. 5 is a block diagram showing an example of the QDPSK circuit 11.

In FIG. 5, a serial / parallel converter 62 fetches serial data 61 supplied from the pre / postamble adding circuit 10 two bits at a time and converts it into parallel two bits (dibits). The difference conversion circuit 63 generates two bit sequences from the current dibit with reference to the immediately preceding dibit, and supplies one to the balanced modulation circuit 65 and the other to the balanced modulation circuit 66. The balance modulation circuits 65 and 66 perform two-phase modulation on the 3 MHz carrier supplied from the carrier oscillator 64 and having a phase different by π / 2 based on the bit sequence input from the difference conversion circuit 63. Output. The combining circuit 67 takes the algebraic sum of both outputs of the balanced modulation circuits 65 and 66, and outputs it as a QDPSK output 68, that is, a PCM audio signal.

Reference numeral 12 is a band pass filter (BPF). The digital signal is subjected to analog phase modulation by the QDPSK modulation circuit 11, and the output PCM audio signal 68 is set to 3 MHz ± 665 KHz by the BPF 12, and VHS which is multiplexed in another signal band, particularly in the next stage.
-It is made not to affect the FM audio signal band of HiFi.

Reference numeral 13 denotes an FM audio circuit, which is a conventional VHS
-Provided for compatibility with the HiFi method. The analog audio signal input to the input terminal 2 is supplied to the A / D converter 5 via the LPF 3 and
It is supplied to the M audio circuit 13. In the FM audio circuit 13, the input audio signal is 1.3M
Hz (L channel) and 1.7 MHz (R channel)
Are FM-modulated with a bandwidth of ± 150 KHz and output as FM-modulated signals. In addition, VHS-
Since the FM audio circuit 13 for HiFi is well known in the art, the circuit configuration and its detailed description are omitted.

Reference numeral 14 denotes a multiplexing circuit for audio signals. The multiplexing circuit 14 receives an 11-MHz AC bias signal output from an AC bias oscillator (not shown) from the QDPSK circuit 11 via the BPF 12 and outputs an S-VHS P-type signal.
CM audio signal and VHS input from FM audio circuit 13
The HiFi system FM audio signal is multiplexed and output as a multiplexed audio signal. As is well known, the AC bias signal is applied in accordance with the nonlinear characteristics of the electromagnetic conversion system in magnetic recording. The AC bias signal has a frequency three times or more the recording frequency, that is, 9 MHz (= 3 MHz ×
3) A higher frequency of 11 MHz.

Reference numeral 15 denotes a recording amplifier circuit, 16 denotes a two-head rotary head for recording audio, and 17 denotes a magnetic tape. The multiplexed audio signal output from the multiplexing circuit 14 is pre-emphasized for the high frequency component by the recording / amplifying circuit 15,
The current signal is supplied to the audio rotary head 16 and is recorded on the magnetic tape 17 in a deep layer. Next, a video signal is surface-recorded on the magnetic tape 17 by a video rotating head (not shown).

Next, the error correction code (ECC) adding circuit 7 in FIG. 4 will be described. As described above, the ECC adding circuit 7 corresponds to each subframe (FIG. 3). 648
Doubled Reed-Solomon codes C1 (31, 27, 5) and C2 (30, 24,
7) is calculated and added. Further, every time the addition of the C1 and C2 codes to each data block is completed, intra-block interleaving is performed.

In the recording format, generator polynomials Gp (x) and Gq for parity codes C1 and C2
(X) is defined as follows.

[0037]

(Equation 1)

[0038]

FIG. 6 is a detailed block diagram of the ECC adding circuit 7.

The digital audio signals of the L and R channels supplied via the input selector 6 (FIG. 4) are 1 TV
Read / write memory (RAM) 71L, 71R or 7 via selectors S71L, S71R for each frame period
2L and 72R are written alternately.

The digital audio signal input during one TV frame period is 1620 samples (16 bits) for each channel, and each sample is composed of upper 8 bits (u) and lower 8 bits (u).
Written as two symbols of bit (l). That is, 6480 symbols for one TV frame are divided into blocks D0, D1,..., D9 in units of 648 symbols, and the RAMs 71L, 71R or 72L, 72
R stores five blocks of L and R channels, respectively.

Of the total 10 blocks of both channels,
One block of L channel, ie, RAM 71L or 72
FIG. 7 shows the arrangement of 648 symbols for one block stored in L.

The ECC addition circuit 7 calculates a C2 parity (Q) of 162 symbols and a C1 parity (P) of 120 symbols for each of the five blocks of each of the L and R channels in block units, and adds them as shown in FIG. Things. Since these calculations and additional processing are performed in common and in parallel for the L and R channels, the following description will be given of processing for one block of the L channel.

First, calculation and addition of C2 parity are performed. In FIG. 6, for example, the selector S
24 symbols via 73L, for example, L000u, L0
001, L001u,..., L0111 (see FIG. 7)
Are sequentially read. Here, this reading is performed at six times the speed of writing. Each symbol (for example, L002
u) is converted by the data / α data conversion ROM 73L into an exponent of exponentiation and supplied to the adder 75L.

The C2 matrix coefficient of each of the six symbols for each symbol (L002u) is calculated by the α coefficient ROM 74.
Are sequentially supplied to the adder 75L. Therefore, the α coefficient R
Reading of the C2 matrix coefficient from the OM 74 is performed at a speed six times as fast as reading each symbol (L002u), that is, 36 times as fast as writing.

The result of adding each of the six symbols to each symbol (L002u) is calculated by the adder 75L from the α coefficient /
The data is supplied to the data conversion ROM 76L and output to the exclusive OR (XOR) circuit 77L as a result of multiplication of 6 symbols. That is, the above-described data / α coefficient conversion ROM 73L,
α coefficient ROM 74L, α coefficient / data conversion ROM 76L
Is performed, for example, as follows. For example, for the data symbol “α ⁶⁴ ”, the data / α data conversion R
The OM 73L outputs “64”. α coefficient ROM74L
Outputs, for example, “3” for the C2 matrix coefficient “α ³ ”. The adder 75L adds "64" and "3" and outputs an addition result "67". α coefficient / data conversion ROM
76L converts the addition result “67” into a multiplication result “α ⁶⁷ ” and outputs the result to the XOR circuit 77L.

The XOR circuit 77L outputs a symbol corresponding to the result of the multiplication of the six symbols (the result of multiplication of the symbol L002u by the six symbols in this example) and the symbol obtained by multiplying the symbol immediately before (the symbol L001l in this example) by the six symbols. XOR with 6 symbols XO
The R result is output as C00 to C05.

The above operation is performed for 24 symbols L000.
, L0111 are sequentially repeated, and the finally obtained C00 to C05 are converted into C2 parities LQ000, LQ001,..., LQ0 of 6 symbols.
05 (see FIG. 7), and RA
Write to a predetermined area of M71L (see FIG. 7).

By repeating the above calculation and writing process for each of 27 sets (1 set = 24 symbols), the 162 (= 6 × 27) symbol C for one block is obtained.
The addition of two parities is completed.

Next, calculation and addition of the C1 parity are performed.

For example, from the RAM 71L, the selector S7
27 symbols via 3L, for example, L000u, L01
, L312u (see FIG. 7) are sequentially read. .. Or L312u for each symbol L000u, L012u,.
L, α coefficient ROM 74, adder 75L, α coefficient / data conversion ROM 76L, and XOR circuit 77L calculate α
Except that the coefficient ROM 74 outputs C1 matrix coefficients of 6 symbols, the operation is exactly the same as that of the C2 parity. Such an operation is represented by 27 symbols L000u, L0.
12u,..., L312u are sequentially repeated, and the XOR results C00 to C05 of the six symbols finally obtained.
Of these, C00 to C03 are C1 parity LP000, LP1
As 00, LP200, and LP300 (see FIG. 7), data is written in a predetermined area of the RAM 71L via the selector S72L.

Here, the four-symbol C1 parity C00-
To obtain C03, the XOR results C00 to C05 of six symbols are obtained as in the case of the C2 parity, and two symbols C0 are obtained.
4. The reason why C05 is discarded is that the circuit scale of the ECC adding circuit 7 can be significantly reduced by enabling calculation of C1 parity with a common circuit configuration and common timing (clock) with C2 parity.

The above calculation and write processing are performed for 30 sets (1 set = 27 symbols) including the C2 parity area.
By repeating each, 120 for one block
(= 4 × 30) The addition of the C1 parity of the symbol is completed.

The addition of the C1 and C2 parities is as follows.
Regarding the corresponding block stored in the RAM 71R,
As in the case of AM71L, the processing is performed simultaneously and in parallel.

C1 and C1 for one block of 648 symbols for each channel by such an ECC adding circuit 7
2 each time the addition of parity is completed,
Block, that is, 2 channels x 930 symbols (however,
930 = 648 + 162 + 120), the interleaving circuit 8 (see FIG. 4) performs inter-block interleaving processing. The intra-block interleave processing will be described later.

The above-described addition of C1 and C2 to each block of both channels and the interleave processing within the block are sequentially repeated for five blocks of each channel, so that one TV frame stored in the RAMs 71L and 71R corresponds to 3240 symbols of each channel. Is completed, and in the next 1TV frame period, the RAM 7
Processing is performed on 3240 symbols of each channel for one TV frame stored in 2L and 72R.

FIG. 8A shows the above-described RAMs 71L and 71L.
The relationship between the read / write period of the digital audio signal of 1R or 72L and 72R and the addition of the C1 and C2 parity and the interleave period in the block for the five blocks in the read period is shown. FIG.
(B) shows the timing of adding the C1 and C2 parity and the interleaving in the block in the above-described block unit. FIG. 9 shows the above-described C1 and C2 parity calculation timing.

Next, the interleave circuit 8 in FIG. 4 will be described. FIG. 10 is a block diagram of the interleave circuit 8, and FIG. 11 is a timing chart over the ECC addition circuit 7 and the interleave circuit 8.

As described above, each time the addition of the C1 and C2 parities to one block of each of the L and R channels is completed by the ECC addition circuit 7, the RAM of the ECC addition circuit 7
The selectors S81E, S810, or S82E, S shown in FIG.
RAM 81E, 81O or 82E, 8 via 82O
Each block in 020 (930 symbols as shown in Fig. 7)
Is transferred and stored. That is, the symbols of each block of the L and R channels are selected by the selectors S81E and S810.
Alternatively, the symbols are classified into even-numbered symbols and odd-numbered symbols by S82E and S82O,
E, 82O show even / odd subframes E as shown in the figure.
00 to E04 and O00 to O04.

Accordingly, at each of the times t0 to t3 shown in FIG. 11, each of the subframes E00 to E34 of 930 symbols stored in the RAM 81E, 81O or 82E, 82O,
The arrangement of O00 to O34 is as shown in FIG.

Next, the interleaving between blocks will be described. The inter-block interleaving means that the sub-frames E00, O00, E01,..., O34,.
Are interleaved in subframe units corresponding to the track pattern shown in FIG. In other words, by transferring each sub-frame stored in the RAM 81 or 82 in the arrangement shown in FIG.
AM 84 and RAM 85 as first and second memories,
The sub-frame arrangement corresponding to the track pattern is obtained on 86.

The track patterns shown in FIG. 2B, for example, output patterns E01, O00, E02, O01, E03, O02, E04, O03, E of ten subframes for one TV frame.
As is clear from 10, O04, the odd-numbered subframe O00-
Since O04 is output with a delay with respect to the even subframes E01 to E10, the even subframe E10 belonging to the next TV frame is mixed. Conventionally, such two TVs
In the interleaving of the subframes over the frames, that is, the interleaving between the blocks, the RAMs 85 and 86 are used to store the subframes of two TV frames.
A memory capacity for a total of 40 frames was required for each of 20 subframes.

Therefore, in the present invention, an inter-block address conversion circuit 83 and an auxiliary RAM 84 for one subframe are provided as shown in FIG.
The memory capacity of each of the sub-frames 86 is set to nine sub-frames, which is one less than one TV frame, and a memory capacity of a total of 19 sub-frames, that is, a memory capacity of half or less (19/40) in this embodiment. Interleaving between blocks was enabled.

FIG. 15 shows an inter-block address conversion circuit 8.
3, the sub-frame E stored in the RAM 81, 82
00-E04, O00-O04, etc. are auxiliary RAM84, RAM8
FIG. 5 is a timing chart for explaining to which area 5, 86 the data is transferred, how it is read, and output in the order according to the track pattern shown in FIG.

First, the write cycle period t of the RAM 85
From 0 to t1, the 10 sub-frames E00, O00, E01, O01,..., E04, O04 stored in the RAM 81 are read out in this order. Inter-block address conversion circuit 8
3 controls the storage destination of each output sub-block as follows.

As shown in FIG. 15, the sub-frame E00 read from the RAM 81 is written to the auxiliary RAM 84 as the area 9 between times t0 and t01. Time t01
During the period from to t02, the subframe O00 is written to the area 2 of the RAM 85. Thereafter, subframes O01, E02,..., O04 are written in the RAM 85 as shown in FIG.
At 1, the RAM 85 enters a read cycle.

Read cycle period t1 to t2 of RAM 85
At 1, the 1 stored in the RAM 85 and the auxiliary RAM 84
The 0 subframes are sequentially read out in the order of the area numbers, and output to the synchronization / subcode adding circuit 87 via the selector S83. The order of the output subframes follows the track pattern as shown.

On the other hand, read cycle period t of RAM 85
From 1 to t2, the RAM 86 and the auxiliary RAM 80 which are in a write cycle have 10 sub-frames E10 for one TV frame stored in the RAM 82,
O10, E11,..., O14 are written as shown, and at time t2, the RAM 86 enters a read cycle.

Read cycle period t2 to t3 of RAM 86
, The 10 subframes E11, O10, E12,..., E20, O14 are output to the synchronization / subcode adding circuit 87 via the selector S83 in the order conforming to the track pattern.

Here, the writing of the sub-frame to the auxiliary RAM 84, for example, the writing of the sub-frame E10 is performed in the period t1 to t01, and the reading is performed in the period t18 to t19. As shown in the figure, the next writing, that is, writing of the subframe E20 is performed in the period t2 to t01, so that no inconvenience occurs.

Next, the mirror-scared (M ² ) conversion circuit 9 in FIG. 4 will be described. FIG. 16 is a block diagram showing the M ² conversion circuit 9, and FIG. 17 is a block diagram showing its operation. Hereinafter, FIG. 16 will be described with reference to FIG.

In FIG. 16, the latch pulse SubF
D, BLAD, 3-bit subframe address Sub
F2, SubF1, SubF0, and a 5-bit block address Block Add4, Block Ad
d3, Block Add2, Block Add1,
Block Add0 is a signal generated by dividing the bit clock BCK by a counter (not shown).

The register 91 has 3-bit subframe addresses (0 to 4) SubF2, SubF1, and SubF
0 is input, captured by the latch pulse SubFD, and output to the logical sum (OR) circuit 93. The register 92 has a 5-bit block address (0 to 29).
Block Add4 to Block Add0 are input, captured by the latch pulse BLAD, and output to the OR circuit 93. Therefore, the 8-bit output of the OR circuit 93 corresponds to the address subcode W1 of each block (each block composed of 35 symbols (280 bits) shown in FIG. 3) input from the interleave circuit 8.

The 8-bit outputs W10 to W17 and the two bits of the logic level "1" are supplied to the input A of the data selector 94 as initial values. An M-sequence generation circuit 9 including D flip-flops (DFF) D91 to D100
XOR of the output of DFF D97 and the output of DFF D100, and DFF D91 to D99
Output, that is, 10-bit data is supplied to the data selector 94.
Is supplied to the input B.

Therefore, if the data selector 94 is controlled so as to select the input A, an M ² data output corresponding to the initial value W 1 is output from the M sequence generation circuit 95. Also,
By controlling the data selector 94 to select the input B, M-sequence signal from the M-sequence generation circuit 95, i.e. the pseudo random number sequence is supplied to the XOR circuit 96 as M ² data output.

The control of the data selector 94 is as follows.
This is performed by the control signals SELA and SELB, and FIG.
As shown in, for the first data symbol D0 M ² conversion by the initial value W1 is, M ² conversion is performed by the M-sequence signal for the other 30 data symbols D1～D30. Here, M ² conversion output is the output of the interleave circuit 8 XOR circuit 96 which receives the signal and M ² data output to the input (FIG. 4).

The control signal SELA is generated by dividing the bit clock BCK by a counter C91, and the control signal SELB is generated by dividing the bit clock BCK by a counter C92. A signal I obtained by dividing the bit clock BCK by the counter C94 is
The output of the AND gate A92 using SHI1 as the gate signal is M during the period during which the data symbols D0 to D30 are input.
The bit clock BCK is supplied to the sequence generation circuit 95.
That is, of the 35 symbols in each block, the synchronization code S,
Subcode W1, W2, parity codes P are not converted M ^2, only the remaining 31 symbols D0~D30 is converted M ^2, are output from the XOR circuit 96. A signal IS obtained by dividing the bit clock BCK by the counter C93
HI4 is connected to DFFs D91 to D91 via AND gate A91.
D100 is supplied to each reset terminal, and during the input period of the synchronization symbol S, which is the first symbol of each block, DFFD
Initialize 91 to D100. This is to correctly set the initial values W10 to W17 in the M-sequence generation circuit 95 for each block.

As described above, the embodiment of the PCM audio recording apparatus according to the present invention has been described for the 48k-mode of the S-VHS system. However, the present invention is not limited to this, and other than the S-VHS system, For example, 8mm video system,
Other than 48k-mode, for example 32k-mode, and N
It is apparent that the present invention can be applied to a PCM audio recording device for a video tape recorder of a PAL system or the like other than the TSC system or a single PCM signal recording device.

[0079]

According to the interleave circuit of the present invention, the interleave between blocks for 20 subframes for 2 TV frames is controlled by the interblock address conversion circuit 83 to the RAMs 85 and 86 each having a memory capacity corresponding to 9 subframes. , Using the auxiliary RAM 84 having a memory capacity equivalent to one subframe shared by the RAMs 85 and 86. That is,
Since inter-block interleaving is performed with a memory capacity that is less than half of that in the related art, it is possible to reduce the circuit scale and achieve high-speed interleaving processing.

[Brief description of the drawings]

FIG. 1 is a diagram showing the specifications of a PCM audio recording format of S-VHS.

FIG. 2 is a diagram showing a track pattern in an S-VHS PCM audio recording format.

FIG. 3 is a diagram showing a data configuration in the same format.

FIG. 4 is a block diagram showing one embodiment of the present invention.

FIG. 5 shows four-phase differential phase modulation (QDPSK) in FIG.
It is a block diagram showing a circuit.

FIG. 6 is a block diagram showing an error correction code (ECC) adding circuit in FIG. 4;

FIG. 7 is a diagram showing a symbol arrangement of each block in the same format.

FIG. 8 is a timing chart of ECC addition and intra-block interleaving.

FIG. 9 is a timing chart of an ECC calculation.

FIG. 10 is a block diagram showing an interleave circuit in FIG. 4;

FIG. 11 is a timing chart of ECC addition and interleaving.

FIG. 12 is a diagram illustrating a subframe configuration in an ECC addition and interleave format.

FIG. 13 is a subframe arrangement diagram for each television frame.

FIG. 14 is a timing chart of interleaving between blocks.

FIG. 15 is a detailed timing chart of interleaving between blocks.

FIG. 16 is a block diagram showing a mirror-scared (M ² ) conversion circuit in FIG. 4;

FIG. 17 is a timing chart of the Miller Scared (M ² ) conversion circuit in FIG. 4;

[Explanation of symbols]

7 Error Correction Code (ECC) Addition Circuit 8 Interleave Circuit 9 Miller Scared (M ² ) Conversion Circuit 10 Pre / Postamble Addition Circuit 11 4-Phase Differential Phase Modulation (QDPSK) Circuit 13 FM Audio Circuit 14 Multiplexing Circuit 62 Serial / Parallel Conversion Circuit 63 Difference conversion circuit 64 Carrier oscillator 65, 66 Balanced modulation circuit 67 Synthesis circuit S71L, S71R, S72L, S72R, S73L,
S73R Selector 71L, 71R, 72L, 72R RAM 73L, 73R Data / α data conversion ROM 74 α coefficient ROM 75L, 75R Adder 76L, 76R α coefficient / data conversion ROM 77L, 77R Exclusive OR (XOR) circuit S81O, S81E, S82O, S82E, S83 Selectors 81, 81O, 81E, 82, 82O, 82E, 85,
86 RAM 83 Inter-block address conversion circuit 84 Auxiliary RAM 87 Synchronization / subcode addition circuit A91, A92 AND gate C91-C94 Counter D91-D100 D flip-flop 91, 92 Register 93 OR circuit 94 Data selector 95 M-sequence generation circuit 96 Exclusive Logical OR (XOR) gate

Claims (1)

(57) [Claims] 1. A PCM audio recording / reproducing apparatus for magnetically recording and reproducing an audio signal by a PCM method, wherein a predetermined number of subframe signals are generated from a digital audio signal for one TV frame for error detection and correction. Further comprising interleaving means for interleaving a signal having a number of subframe units one less than that for one TV frame in a frame and interleaving a signal for one subframe unit between frames, wherein said interleaving means is provided for said one TV frame. A first and a second memory for storing a signal of one less subframe unit, a third memory for storing a signal of one subframe unit, and a signal writing / reading of the first to third memories An address conversion circuit for controlling processing, wherein the address conversion circuit The interleaving in a frame is performed by storing a signal in a subframe unit to be releasable in the first or second memory and reading the stored signal from the other memory, and controlling the write / read position and timing of the signal. In addition to performing the processing, the sub-frame unit signal for performing the interleaving between the frames is written to the third memory, and the interleaving between the frames is controlled by controlling the read timing of the signal written to the third memory. A PCM audio recording device for performing processing.