JP3042209B2 - Self-diagnosis device for semiconductor memory failure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random logic IC tester equipped with an IC
The present invention relates to a failure self-diagnosis device for a semiconductor memory in an IC tester equipped with a large-capacity memory.

[0002]

2. Description of the Related Art The configuration of a conventional semiconductor memory failure self-diagnosis apparatus will be described with reference to FIG. 7 is CP
U, 2 is a data generation circuit, 3 is an address generation circuit, 4 is a comparator, 5 is a memory, 6 is a clock generation circuit, 7 is a test end detection circuit, 8 is a switching circuit, and 9 is a flip-flop (hereinafter referred to as FF). ). In FIG. 7, before testing the memory 5, the conditions of each unit are set. CPU 1 of FIG.
To the address generating circuit 3 from the input data 1A. Similarly, the range of the address to be tested by the input data 1A is given to the test end detection circuit 7.

Next, conditions for testing the memory 5 are set in the address generation circuit 3 and the test end detection circuit 7. The data generation circuit 2 gives test data according to the input data 1A of the CPU 1. After setting the above conditions, the write / read mode signal 1B is supplied from the CPU 1 to the switching circuit 8, and the switching circuit 8 outputs the output data of the data generation circuit 2 to the output 8A, and supplies the output data to the data input of the memory 5. Thus, the start address is given from the address generation circuit 3 to the memory 5, and the test data is given from the output 8 A of the switching circuit 8 from the data generation circuit 2.

When the test start signal 1C is output from the CPU 1, the FF 9 is reset, the clock generation circuit 6 is started, and the output clock 6B is supplied to the WE of the memory 5 to write data to the memory 5. The output clock 6A is supplied as a clock to the address generation circuit 3, the data generation circuit 2, and the test end detection circuit 7, and sets the address to +1 or -1 and holds the data at +1 or -1 or the previous state.

The test data is written in the memory 5 by hardware in the cycle of the output clocks 6A and 6B. At the same time, the test end detecting circuit 7 counts down by the output clock 6A. , And outputs a test end signal to the clock generation circuit 6. When the clock generation circuit 6 receives the test end signal, it stops generating the clock, and the test data is written in the memory 5 at the address to be tested.

Next, conditions are set before execution of the memory read mode. This condition setting is the same as before the execution of the write / read mode signal. Once the conditions are set, CP
U1 sets the write / read mode signal 1B to "0" and outputs it, and the switching circuit 8 is set to the output 8B side,
The output of the data generation circuit 2 is provided to the comparator 4 as expected data.

When the test start signal 1C is output from the CPU 1, the FF 9 is reset, and the clock generation circuit 6 is reset.
Start The clock generation circuit 6 outputs the clock 6A and outputs the clock 6B, but the output 1B of the CPU 1 is "0".
Therefore, “1” is always given to the WE of the memory 5.
Therefore, since the memory 5 is in the read cycle, data is read from the memory 5 by the output address of the address generation circuit 3 and is supplied to the comparator 4. The comparator 4 compares the read data of the memory 5 with the output 8B of the switching circuit 8 and detects a match or a mismatch. When there is a mismatch, the comparator 4 outputs a mismatch signal 4A, which is applied to the set input of the FF 9, and the FF 9 is set and outputs a fault signal 10.

Since the clock generating circuit 6 generates the clock 6A in the same manner as in the memory writing, the address generating circuit 3 and the data generating circuit 2 output the same address and data as in the memory writing. This technique is described in Japanese Patent Application No. 2-307640.

[0009]

In the conventional apparatus shown in FIG.
When self-determining a memory failure, a method of writing "1" or "0" to all addresses and then reading "1" or "0" from all addresses, that is, read / write
Since the scan was performed, the failure detection rate was low. The present invention differs from the conventional device shown in FIG.
0, 11, 12, 13, 14, selectors 15, 16, 1,
By adding 7, it becomes possible to perform marching and a checkerboard at the time of failure self-diagnosis, and to increase the failure detection rate of the memory.

[0010]

According to the present invention, a diagnostic sequence program is written and a write / read mode signal 1B, a test start signal 1C, and a marching / checkerboard mode signal 1D are output. A data generating circuit 2 for generating data to be added to the memory 5 when the CPU 1 is in the write mode, and a data generating circuit 2 for generating expected data when the CPU 1 is in the write mode.
To the address of the memory 5, and
When U1 is in the read mode, it is started by an address generation circuit 3 for giving an address to be read from the memory 5 to an address input of the memory 5 and a test start signal 1C of the CPU 1, and generates clocks 6A, 6B, 6C, 6D and 6E. A clock generating circuit 6; a frequency dividing circuit 11 for dividing the output clock 6A of the clock generating circuit 6; and a selector 15 for selecting the output 11A of the frequency dividing circuit 11 and the output clock 6A according to the mode of the write / read mode signal 1B. , A test end detecting circuit 7 for detecting a test end and generating a stop signal for stopping the operation of the clock generating circuit 6 by an output of the selector 15, an inverted signal of the write / read mode signal 1B and a marching / checkerboard mode signal 1
An AND gate 22 having D as an input, a frequency dividing circuit 12 for dividing the output clock 6B of the clock generating circuit 6, and a frequency dividing circuit 14 for further dividing the output 12A of the frequency dividing circuit 12.
A selector 16 for selecting the output 14A and the output 12A of the frequency dividing circuit 14 by the output of the AND gate 22, a NAND gate 23 for inputting the output clock 6C of the clock generating circuit 6 and the output 12A of the frequency dividing circuit 12, A selector 17 for selecting an inverted signal of the output 23A of the gate 23 and the output clock 6C by the output of the write / read mode signal 1B, and an output clock 6 of the clock generating circuit 6
A frequency dividing circuit 13 for frequency dividing D; a frequency dividing circuit 10 for frequency dividing the output clock 6E of the clock generating circuit 6;
OR gate 1 that receives an inverted signal of read mode signal 1B and marching / checkerboard mode signal 1D as inputs
9, an AND gate 20 receiving the output 16A of the selector 16 and the output of the OR gate 19 as inputs, and a data generation circuit 2
And an output of the AND gate 20, and an inverting circuit 18 for outputting through data or inverted data; a write / read mode signal 1B and an output 10 of the frequency dividing circuit 10;
An OR gate 21 having A as an input, and an output 18A of the inverting circuit 18 as an input, and a switching circuit 8 for switching between inputting the output 8A to the memory 5 and inputting the output 8B to the comparator 4 according to the output 21A of the gate 21. And the inverted signal of the write / read mode signal 1B and the output 13 of the frequency divider 13
An AND gate 24 having A as an input, read data of the memory 5 as a first input, an output 8B of the switching circuit 8 as a second input, and output data of the memory 5 and expected data of the data generation circuit 2 Whether the comparison is performed or not is controlled by the output of the NAND gate 24. At the time of comparison, the comparator 4 detects whether the expected data matches the output data of the memory 5 and determines whether the memory 5 is good or not. The output of the tester 4 is used as a set signal, and the test start signal 1C
Is a reset signal.

[0011]

Next, the configuration of a memory failure self-diagnosis device according to the present invention will be described with reference to FIG. In FIG. 1, reference numerals 10 to 14 denote frequency divider circuits, reference numerals 15 to 17 denote selectors, and reference numeral 18 denotes an inverting circuit. In FIG. 1, the output 1B of the CPU 1 is shown.
Outputs "H" in the write mode and "L" in the read mode. The output 1D outputs “H” in the checkerboard mode, and outputs “L” in the marching mode.

An output 1C from the CPU 1 is input to a frequency dividing circuit 10 and frequency-divides a clock 6E of a clock generating circuit 6. The frequency dividing circuit 11 receives the clock 6A of the clock generating circuit 6.
Is divided. The frequency dividing circuit 12 divides the frequency of the clock 6B of the clock generating circuit 6. The frequency divider 13 divides the frequency of the clock 6D of the clock generator 6. The frequency divider 14 divides the output of the frequency divider 12. The selector 15 receives the clock 6A of the clock generator 6 and the output of the frequency divider 11 as inputs,
When the output 1B of the CPU 1 is "H", the output clock 6A
Is selected, and when "L", the output 11A of the frequency dividing circuit 11 is selected. The selector 16 receives the output of the frequency divider 12 and the output of the frequency divider 14 as inputs, and selects the output 14A of the frequency divider 14 when the output of the AND gate 22 is "H".
When "L", the output 12A of the frequency dividing circuit 12 is selected.

The selector 17 receives the inverted signal of the clock 6C of the clock generation circuit 6 and the output of the gate 23 as inputs,
When output 1B of PU1 is "H", output 23 of gate 23
A is selected, and when "L", the output clock 6C is selected. The inverting circuit 18 receives the output of the data generating circuit 2 and the output of the AND gate 20 as inputs, and supplies data to the input of the switching circuit 8.

The memory 5 inputs the output 8A of the switching circuit 8 as data, and writes data at the output timing of the selector 17. The comparator 4 receives the data of the output of the memory 5 and the data of the output 8B of the switching circuit 8 and outputs the output 4A at the timing of the NAND gate 24. The NAND gate 24
The output 13A of the frequency divider 13 and the inverted output of the output 1B of the CPU 1 are input.

Next, the operation of FIG. 1 will be described. Before testing the memory 5, the conditions of each unit in FIG. 1 are set. CPU1
To the address generating circuit 3 from the input data 1A. Similarly, the range of the address to be tested by the input data 1A is given to the test end detection circuit 7.

Next, examples of conditions for testing the memory 5 having a capacity of 64 KW will be described with reference to FIGS.
In FIG. 2, when testing from address 0 to address 99 out of 64 KW, "0" is set in the address generation circuit 3 and (99-0 + 1) = 10 is set in the test end detection circuit 7.
Give 0. The data generation circuit 2 gives test data according to the input data 1A of the CPU 1.

Next, the case of marching will be described with reference to FIG. Marching means that "0" is written to all the cells of the memory, and then reading and writing are repeated bit by bit, and then the same sequence is repeated for the inverted data, thereby almost completely fixing the address system. It can be completely detected.

First, "1" or "0" is assigned to all addresses.
And check whether the value can be written. First, after setting the above conditions, when the write / read mode signal 1B of the CPU 1 is "H" and the checker / marching mode output 1D is "L", the selector 15 is set to "H" and the CPU 1 outputs the start signal 1C. Is supplied to a clock generation circuit 6, an output clock 6A is output, and data is set in an address generation circuit 3, a data generation circuit 2, and a test end detection circuit 7.

At this time, the OR gate 19 outputs "L", the AND gate 22 outputs "L", and the selector 16 is set to "L". Output 12 of frequency divider circuit 12
A is the input of the AND gate 20 (the output of the OR gate 19)
Is given "L", the output is "L" constant. Therefore, the output 18A of the inverting circuit 18 outputs data in a through state and is applied to the input of the switching circuit 8. Then, the output 10A of the frequency dividing circuit 10 and the output of the write / read mode signal 1B are given to the input of the OR gate 21. At this time, the output is in the “H” state. Therefore, the switching circuit 8
Is output to the 8A side. At this time, the selector 17
Is applied to the WE of the memory 5 by applying the output clock 6C of the clock generation circuit 6 to write data to the memory for each address.

Next, reading of marching will be described. When the write / read mode signal 1B of the CPU 1 is "L" and the checker / marching mode output 1D is "L", "L" is set in the selector 15,
The output 11A of the frequency divider 11 is provided to the address generator 3, the data generator 2, and the test end detector 7. At that time, the OR gate 19 outputs “H”, the AND gate 22 outputs “L”, and the selector 16
The second output 12A is output.

As a result, the output of the AND gate 20 is supplied from the output of the frequency dividing circuit 12 to the inverting circuit 18, the data is repeatedly output through / inverted, and supplied to the input of the switching circuit 8. When the output of the output 10A of the frequency dividing circuit 10 is given and output to the 8B side, inverted data is output when outputting to the through data 8A side. When the WE of the memory 5 is “L”, the output of the NAND gate 23 is output to the selector 17, and the inverted data written in the memory 5 is written in the address by the output of the address generation circuit 3.

When WE of the memory 5 is "H", data is read from the memory 5 by the output of the address generating circuit 3 in a read state, and is supplied to the comparator 4. Comparator 4
Is the read data of the memory 5 and the output of the switching circuit 8. In this case, the WE of the memory 5 controls the output data of READ by enabling, compares, and detects a match or mismatch. When there is a mismatch, the comparator 4 outputs a mismatch signal 4A, which is supplied to the set input of the FF 9, and the FF 9 is set and outputs the failure signal 31.

Next, the writing of the checkerboard will be described. The checkerboard writes "H" and "L" alternately in all the cells of the memory in a checkered pattern, then reads out and compares them, and detects cell failures as well as data interference between cells and the lowest address. It is possible to detect a multiple selection failure of bits. When the memory write mode output 1B of the CPU 1 is “H” and the checker / marching mode output 1D is “H”, the selector 15
Is set to H, and the output clock 6A of the clock generation circuit 6 is output and supplied to the address generation circuit 3, the data generation circuit 2, and the test end detection circuit 7.

At that time, the OR gate 19 outputs "H", the AND gate 22 outputs "L", and the selector 1
Set to 6. Since the output of the OR gate 19 is "H", the output of the AND gate 20 is the output 12A of the frequency dividing circuit 12. Therefore, the inversion circuit output 8A outputs a through / inverted value for each address, and since an "H" signal is input to the OR gate 21, the "H" value is given to the switching circuit 8, and the output is Output to 8A side.

At this time, the output of the selector 17 is obtained by applying the output clock 6C of the clock generation circuit 6 to the WE of the memory 5 so that the data is changed from "H" to "L" to "address".
The data is written into the memory 5 while inverting from “H” to “L”.

Next, the read mode of the checker board will be described. Write / read mode signal 1B of CPU 1 is L, checker / marching mode output 1
When D is “H”, “L” is set in the selector 15, an output 11 A of the frequency divider 11 is output, and is supplied to the address generator 3, the data generator 2, and the test end detector 7. At that time, the OR gate 19 outputs “H”, and the first input of the AND gate 22 is set to “H”.

The selector 16 outputs the output 14A of the frequency dividing circuit 14. For this reason, the output of the AND gate 20 is supplied to the inverting circuit 18 from the output of the frequency dividing circuit 1A, the data is repeatedly output through-inversion, and supplied to the input of the switching circuit 8. Then, the output 10A of the frequency dividing circuit 10
Is output to the switching circuit 8, which outputs through data when outputting to the 8B side and inverts data when outputting to the 8A side. Hereinafter, the same operation as the reading of marching is performed.

The selector 15 selects either the output 11A of the frequency divider 11 or the output clock 6A of the clock generator 6, sets the address of the address generator 3 to +1 or -1, and sets the address of the data generator 2 to +1 or -1. +1 data
Or, keep -1 or the previous state. At the same time, the test end detection circuit 7 counts down according to the output of the selector 15, and when the count becomes “0”, considers that the test has ended, issues a test end signal, and provides the clock generation circuit 6. The clock generation circuit 6 stops the clock generation when receiving the test end signal. Thus, in the memory diagnosis according to the present invention, the output clock 6 of the clock generation circuit 6
Self-diagnosis can be performed in cycles A, 6B, 6C, 6D, and 6E.

[0029]

FIG. 3 is a timing chart of the writing mode and the reading mode of the marching according to the configuration of FIG. FIG. 3A shows the waveform of the output 15A of the selector 15, and since the output 1B of the CPU 1 is at the "H" level, the selector 15 selects the output clock 6A of the clock generation circuit 6. A is the output of the address generation circuit 3 and FIG.
Address is generated in synchronization with the address. C is data input from the CPU 1 to the data generation circuit 2 and is constant at the H level. D is the output of the AND gate 20 and is constant at the L level. 3A shows the output 18A of the inverting circuit 18, which becomes constant at the H level according to FIGS. 3C and 3D, and the switching circuit 8 selects the output 8A. F is the output of the selector 17 and CP
Since the output 1B of U1 is at the "H" level, the output of the gate 23A is selected and output. "G" is a waveform of data written to the memory 5, and "H" is written to all addresses. 3A to 3C are time charts in the write mode.

FIG. 3C shows the output waveform of the selector 15. Since the output 1B of the CPU 1 is at the "L" level, the selector 15 selects the output 11A obtained by dividing the output clock 6A of the clock generation circuit 6. Numeral is an output waveform of the address generating circuit 3, and generates an address in synchronization with FIG.コ is data input from the CPU 1 to the data generation circuit 2 and is constant at the H level. SA is AND gate 2
It is an output of 0, and receives the output of the gate 19 and the output of the selector 16 as inputs, and repeats inversion and through. Reference numeral denotes an output of the inverting circuit 18, and data is output alternately in synchronization with FIG. Is the output of the frequency dividing circuit 10 and the OR gate 2
1 to the switching circuit 8, and the switching circuit 8 outputs 8A
And the output 8B are output at the timing of the frequency dividing circuit 10. The output from the gate 17 is input to the memory 5 because the output 1B of the CPU 1 is "H".
S is the output of the NAND gate 24. 3C to 3C are time charts in the reading mode.

Next, FIG. 4 shows a time chart of the write mode and the read mode of the checker board. 4 are the same as those in FIG. D is the output of the AND gate 20, the output 1B of the CPU 1 is "H",
Since the output 1D is “H”, the AND gate 22 becomes “H”, and the selector 16 selects the output 14A of the frequency dividing circuit 14 and sets it as the output 16A. Therefore, the output of the AND gate 20 repeats inversion and through. 4A is the output of the inverting circuit 18 and inputs "H" and "L" to the switching circuit 8 at the timing of FIG. F is the output of the selector 17,
It is the same as FIG. Keys are data in the memory 5, and data is written at the timing shown in FIG. 4A to 4C are time charts in the write mode.

FIGS. 4C to U are the same as FIGS. Is the output of the AND gate 20, the output of the gate 19 is "H", and the gate 22 is "H".
The selector 16 selects the output 14A of No. 4 and inputs it to the AND gate 20 as the output 16A, and repeats inversion and through. Reference numeral denotes an output of the inverting circuit 18, and data is input to the switching circuit 8 at the timing of the output 14A of the frequency dividing circuit 14. Is the output of the switching circuit 8, and the output 1B of the CPU 1 is "L". Therefore, the output 8A and 8B of the switching circuit are switched at the timing of the output 10B of the frequency dividing circuit 10.
Se and Soe are the same as FIG.

Next, a circuit diagram of the embodiment of FIG. 1 will be described with reference to FIG. In FIG. 5, the data generation circuit 2 and the address generation circuit 3 use an up counter, and the test end detection circuit 7 uses a down counter. Input data 25
Is connected to the inputs of the up counters 2 and 3 and the down counter 7, and the output of the up counter 3 is connected to the address of the memory 5. The test mode 27 is connected to the up-counter 2 and this signal causes the up-counter 2
Switches to the up-count or data hold mode. The output of the up counter 2 is connected to the inverting circuit 18.

The OR gate 19 receives the checker / march mode 26 and the write mode 28 as input and outputs the same as an input to the AND gate 20. When the output of the selector 16 is "L", the inverting circuit 8 passes the data. When the output of the OR gate 21 is "H", the signal is output to 8A, when the output is "L", the signal is output to 8B. 5 and the comparator 4. The test start signal connects the FF 9 to the reset input and is connected to the clock generating circuit 6 and the frequency dividing circuits 10, 11, 12, 13, and 14.

The output clock 6 A of the clock generator 6 and the output of the frequency divider 11 are connected to the selector 15, and the output of the selector 15 is connected to the up counters 2 and 3 and the down counter 7. The output clock 6B is connected to the frequency dividing circuit 12, and its output is connected to the selector 16 and the frequency dividing circuit 14. The output of the selector 16 is connected to the AND gate 20, and outputs through or inverted data. The output clock 6C and the output of the frequency divider 12 are applied to the input of the NAND gate 23 and output, and input to one of the selectors 17,
On the other hand, the output clock 6C is input, and
To WE.

The output clock 6E is input to the frequency dividing circuit 10, the frequency-divided output is input to the OR gate 21, and the switching circuit 8 is controlled by the write mode 28. The output clock 6D is input to the frequency dividing circuit 13, and its output and the output of the write mode 28 are input to the NAND gate 24, and are output to enable the comparator 4.

The output of the comparator 4 is connected to the set input of the FF 9, and the FF 9 is set only when it is defective. The output of the down counter 7A is connected to the zero coincidence circuit 7B, and the zero coincidence detection circuit 7B detects that the output of the down counter 7A becomes "0", and is connected to the OR gate 32. The failure stop mode 15 is connected to the AND gate 33, the output of the AND gate 33 is connected to the OR gate 32, and the output of the OR gate 32 is connected to the clock generation circuit 6.

Since the OR gate 32 performs an OR operation on the output of the zero coincidence detection circuit 7B and the output of the AND gate 33, when either signal is "H", it outputs the signal to the clock generation circuit 6 and terminates the test. When the failure stop mode 30 is “H”, the AND gate 33 performs an OR operation on the failure data of the FF 9.
Output to the gate 32. When the test is to be terminated with the first failure in this way, the failure generation mode 15 is set to "H", the clock generation circuit 6 is stopped by the first failure, and the output clocks 6A, 6B, 6C of the clock generation circuit 6 are stopped. , 6
D and 6E stop. Here, the defective address can be known by checking the value of the up counter 3. Also,
After executing the test in all the address areas, the state of the FF 9 can be seen to find out the defective memory 5 and the defective bit.

In this case, the test pattern of the IC tester usually has multi-bit data. In this case, it is only necessary to add the comparator 4 and the FF 9 for the number of bits and one OR gate 34. The output of the data generation circuit 2 may have the number of bits, but when writing the same data, only one bit may be used. FIG. 6 is a circuit diagram of an embodiment when FIG. 5 has 4 bits.

[0040]

According to the present invention, since the inverting circuit and the frequency dividing circuit are provided, a marching / checker board can be formed as compared with the self-diagnosis of the memory of the conventional device, so that a high fault detection rate can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory failure self-diagnosis device according to the present invention.

FIG. 2 is a diagram showing an example of conditions when testing a memory 5 having a capacity of 64 KW.

FIG. 3 is a time chart of a marching write / read test.

FIG. 4 is a time chart of a write / read test of a checker board.

FIG. 5 is a circuit diagram of the embodiment of FIG. 1;

FIG. 6 is a circuit diagram of an embodiment when FIG. 5 has 4 bits.

FIG. 7 is a configuration diagram of a failure self-diagnosis device for a semiconductor memory according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Data generation circuit 3 Address generation circuit 4 Comparator 5 Memory 6 Clock generation circuit 7 Test end detection circuit 8 Switching circuit 9 FF 10-14 Divider circuit 15-17 Selector 18 Inverter circuit 19-24 Gate

Claims (1)

(57) [Claims] 1. A diagnostic sequence program is written, a write / read mode signal (1B), a test start signal (1C), and a marching / checkerboard mode signal.
A CPU (1) that outputs (1D) and a data generation circuit (2) that generates data to be added to the memory (5) when the CPU (1) is in the write mode and generates expected data when the CPU (1) is in the read mode. ) And when the CPU (1) is in the write mode, the address to be written to the memory (5) is given to the address of the memory (5),
When (1) is in the read mode, it is started by the address generation circuit (3) that gives the address to be read from the memory (5) to the address input of the memory (5) and the test start signal (1C) of the CPU (1), Clock generation circuit (6) for generating clocks (6A, 6B, 6C, 6D, 6E)
A frequency divider (11) for dividing the output clock (6A) of the clock generator (6), and an output (11A) and an output clock (6A) of the frequency divider (11) are written / read mode signal ( A selector (15) selected according to the mode of 1B) and a test end detection circuit (7) that detects the end of the test and generates a stop signal at the output of the selector (15) to stop the operation of the clock generation circuit (6). A which receives an inverted signal of the write / read mode signal (1B) and a marching / checkerboard mode signal (1D)
An ND gate (22), a frequency divider (12) for dividing the output clock (6B) of the clock generator (6), and a frequency divider for further dividing the output (12A) of the frequency divider (12) (1
4) AND the output (14A) and output (12A) of the frequency divider (14) with an AND gate
The selector (16) selected by the output of (22), the output clock (6C) of the clock generator (6) and the frequency divider (1
The NAND gate (23) to which the output (12A) of (2) is input, and the output (23A) of the NAND gate (23) and the inverted signal of the output clock (6C) are selected by the output of the write / read mode signal (1B). A selector (17), a frequency dividing circuit (13) for dividing the output clock (6D) of the clock generating circuit (6), and a frequency dividing circuit for dividing the output clock (6E) of the clock generating circuit (6) ( 10) and an O which receives an inverted signal of the write / read mode signal (1B) and a marching / checkerboard mode signal (1D) as inputs.
An R gate (19), an AND gate (20) that receives the output (16A) of the selector (16) and the output of the OR gate (19) as inputs, an output of the data generation circuit (2) and an AND gate (20). An inverting circuit (18) that receives an output and outputs through data or inverted data; and an OR gate (21) that receives a write / read mode signal (1B) and an output (10A) of a frequency divider (10) as inputs. The output (18A) of the inverting circuit (18) is input, and the output (8A) is input to the memory (5) or the output (8B) is input to the comparator (4) by the output (21A) of the gate (21). Switching circuit to switch between
(8), an AND gate (24) that receives an inverted signal of the write / read mode signal (1B) and the output (13A) of the frequency divider (13) as inputs, and reads data read from the memory (5) into the first The output (8B) of the switching circuit (8) is used as the second input, and the output data of the memory (5) is compared with the expected data of the data generation circuit (2) by enabling the AND gate (24). The comparator (4) determines whether the expected data and the output data of the memory (5) match or not, and determines whether the memory (5) is good or not. ) As a set signal, and a flip-flop (9) using the test start signal (1C) of the CPU (1) as a reset signal.