JP3041886B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device having a bipolar transistor having a thin base region.

[Conventional technology]

Bipolar transistors are superior to MOS transistors in their high speed and high driving capability. Although high speed of bipolar transistors is represented by the cut-off frequency f _T, or to increase the f _T can thin much the width W _B of the base region is a major point.

In order to form such a thin base region, a conventional bipolar transistor is shown in FIGS. 3 (a) and 3 (b).
It is manufactured by the manufacturing method shown in FIG.

That is, as shown in FIG. (A), P ^- type silicon substrate 20
After forming an N ⁺ type buried region 202 and an N ⁻ type epitaxial layer 203 in 1, an element region is defined by an element isolation oxide film 204. Next, arsenic ions are selectively implanted into the element region to form an N ⁺ -type emitter region 205. At the time of arsenic ion implantation, high-concentration arsenic ion implantation is performed, for example, at an acceleration energy of 70 KeV and a dose of about 1 × 10 ¹⁶ cm ⁻² . At this time, the epitaxial region 203 of the emitter region 205
Becomes amorphous.

Next, as shown in FIG. 2B, boron is ion-implanted into the element region, for example, at an acceleration energy of 40 to 60 KeV and a dose of about 1 to 5 × 10 ¹³ cm ⁻² to form a base region 206.

In the bipolar transistor manufactured by this method, in the base region 206 immediately below the emitter region 205, ions are implanted through the amorphized emitter region 205, so that the tail due to channeling of the ion implantation can be suppressed. As a result, the base width can be formed thin.

FIG. 4 shows an impurity profile of the bipolar transistor manufactured by such a method.

Note that as another method, there is a method of forming a shallow base region using heavy ions such as BF ₂ ⁺ .

[Problems to be solved by the invention]

In the method of manufacturing a bipolar transistor having a conventional thin base region 206 described above, the thin base region 206 of the impurity profile of boron, for forming by using a portion far from the peak portion, the width W of the base region 206 _B
When the emitter region 205 is formed deeper to further reduce the thickness, the total amount of impurities in the base region 206 is drastically reduced,
There is a problem that the emitter-collector breakdown voltage is reduced by punch-through.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a drop due to such punch-through is prevented and a cutoff frequency is increased.

[Means for solving the problem]

The method of manufacturing a semiconductor device according to the present invention includes a step of forming an epitaxial layer of one conductivity type as a collector region, and a step of forming an amorphous silicon layer containing a high concentration of impurities of the opposite conductivity type on the epitaxial layer. A step of forming a thin solid phase epitaxial growth layer in a part of the thickness direction in contact with the amorphous silicon layer by using the epitaxial layer as a seed crystal by performing a high-temperature short-time heat treatment, and removing the remaining amorphous silicon layer; Forming an insulating film on the surface of the solid-phase epitaxial growth layer; and forming an emitter region by forming a one-conductivity-type polycrystalline silicon layer through a window formed in the insulating film.

[Action]

According to this configuration, the base region can be formed thinly with a high impurity concentration, and a bipolar transistor having a high cutoff frequency and good high frequency characteristics can be configured.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are sectional views showing one embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1 (a), a P ^- type silicon substrate
After forming an N ⁺ type buried layer 102 in a region corresponding to the device region 101,
An N ⁻ -type epitaxial layer 103 having an impurity concentration of about 1 to 5 × 10 ¹⁵ cm ⁻³ is grown on the entire surface. In addition, this epitaxial layer 1
A surface / element isolation oxide film 104 is formed on the surface of 03 to define an element region.

Next, as shown in FIG. 1 (b), the surface / element isolation oxide film 104 in a region where a base is to be formed is selectively etched away, and the N ⁻ -type epitaxial layer 10 in this region is removed.
Expose the surface of 4. Thereafter, an amorphous silicon layer 105 is grown on the entire surface to a thickness of about 0.5 to 1.0 μm. Then, boron ions having an acceleration energy of about 10 to 30 KeV and a dose of about 1 × 10 ¹⁶ cm ⁻² or more are implanted into the amorphous silicon layer 105. At this time, the depth of the impurity profile of boron by ion implantation is set not to be larger than the thickness of the amorphous silicon layer 105. Next, heat treatment at a low temperature of 700 ° C. or less is performed. At this time,
By utilizing the difference in the diffusion coefficient of boron between amorphous silicon and epitaxial silicon, the impurity concentration in the amorphous silicon layer 105 is made almost uniform, and diffusion of boron into the N ⁻ -type epitaxial layer 103 is reduced as much as possible. Set the heat treatment time.

Next, as shown in FIG. 1 (c), high-temperature and short-time heat treatment such as lamp annealing or laser annealing is performed.
Solid phase epitaxial growth is performed on a part of the amorphous silicon layer 105 using the N ⁻ type epitaxial layer 103 as a seed crystal, and a P ⁺ type base region 106 is grown to about 0.3 μm. After that, the remaining amorphous silicon layer 105 is removed by etching.

Next, as shown in FIG. 1 (d), P ⁺ -type base region
After forming an oxide film 107 on the surface of 106 and opening a window in the oxide film 107 in a region corresponding to the emitter region, a polycrystalline silicon film is formed on the entire surface, impurities such as arsenic are introduced into this, and P ⁺ type emitter region 108 is formed by selective etching.

After that, an interlayer insulating film 109 is formed, a contact hole is opened, and then a metal wiring 110 of an emitter, a base, and a collector is formed. Thus, a bipolar transistor is completed.

In the bipolar transistor thus formed,
Highly doped amorphous silicon layer 105
The epitaxial layer 10
Since the solid-phase epitaxial growth layer 106 is formed on the surface of 3 and the solid-phase epitaxial growth layer 106 is configured as a base region, a high-concentration thin base region is formed. As a result, a bipolar transistor having a large cutoff frequency and good high-frequency characteristics can be configured.

Also, in this method of manufacturing a bipolar transistor,
Since a part of the conventional bipolar transistor manufacturing process only includes the growth process of the amorphous silicon layer 105 and the growth process of the solid-phase epitaxial growth layer 106, it is possible to easily manufacture the bipolar transistor.

FIG. 2 is a sectional view showing a part of another manufacturing method of the present invention. In this embodiment, boron is added to the amorphous silicon layer 105 by ion implantation in the above embodiment using boron silica glass (BSG).

That is, as shown in FIG. 2, after the amorphous silicon layer 105 is grown, the boron silica glass layer 111 is formed thereon.
To form Thereby, this boron silica glass layer 11
Since the formation of 1 and the diffusion of boron into the amorphous silicon layer 105 are performed at the same time, the number of steps can be reduced as compared with the first embodiment.

〔The invention's effect〕

As described above, according to the present invention, after forming an amorphous silicon layer, a thin base region can be formed by performing a high-temperature short-time heat treatment to perform solid phase epitaxial growth on a part of the amorphous silicon layer in the thickness direction. As a result, a bipolar transistor having a high cutoff frequency and good high-frequency characteristics can be manufactured.

[Brief description of the drawings]

1 (a) to 1 (d) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a cross-sectional view showing a part of steps of another manufacturing method of the present invention, and FIG. 4A and 4B are cross-sectional views showing a conventional bipolar transistor manufacturing method in the order of steps, and FIG. 4 is a view showing an impurity profile in a conventional bipolar transistor. 101 …… P ^- silicon substrate, 102 …… N ⁺ type buried region, 103…
... N ^- -type epitaxial layer, 104 ...... surface-field isolation oxide, 105 ...... amorphous silicon layer, 106 ...... P ⁺ -type solid-phase epitaxial growth layer, 107 ...... oxide film, 108 ...... N ⁺ -type emitter region , 109 ... interlayer insulating film, 110 ... metal wiring,
111: Boron silica glass, 201: P ^- type silicon substrate, 202: N ⁺ type buried region, 203: N ^- type epitaxial layer, 204: Surface / element isolation oxide film, 205: N ⁺ Type emitter region, 206: P type base region.

Claims (2)

(57) [Claims] A step of forming an epitaxial layer of one conductivity type as a collector region, a step of forming an amorphous silicon layer containing a high concentration of an impurity of the opposite conductivity type on the epitaxial layer, and a heat treatment at a high temperature for a short time. Forming a thin solid phase epitaxial growth layer in a part of the thickness direction in contact with the amorphous silicon layer by using the epitaxial layer as a seed crystal, and removing the remaining amorphous silicon layer to form the solid phase epitaxial growth layer. Forming an insulating film on the surface of the semiconductor device, and forming an emitter region by forming a polycrystalline silicon layer of one conductivity type through a window opened in the insulating film. . 2. The method according to claim 1, wherein said heat treatment at a high temperature for a short time is performed by lamp annealing or laser annealing.