JP3036417B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing digital signal processing on data input as a digital signal by executing a program supplied by selectively switching from a plurality of types of microprograms. In particular, the present invention relates to a technique for reducing the time required for switching programs.

[0002]

2. Description of the Related Art In recent years, a program arbitrarily selected by a user among a plurality of types of microprograms describing numerical calculation processing and delay processing for different acoustic effects is supplied to an arithmetic unit of a DSP (digital signal processor). A signal processing device in which a sound effect is given to a musical tone by causing the arithmetic unit to execute the program has been adopted in electronic musical instruments and other musical sound generating devices. Generally, a DSP of such a signal processing device is provided with a delay RAM for performing delay processing.

In such an electronic musical instrument or the like, if a user newly selects another type of program in place of a certain type of program while the program is being executed,
Conventionally, the delay R
To prevent the tone waveform data written in the AM from being output from the DSP after switching the program, all tone waveform data in the delay RAM are cleared, and then the delay RAM is executed by executing the switched program.
To start writing musical tone waveform data in the memory.

An example of such a conventional program switching method is disclosed in Japanese Patent Application Laid-Open No. Hei 6-259249 filed by the present applicant.
No. 6,009,045. FIG. 10 shows the contents of the program switching process according to the method together with the output level of the musical tone waveform data along time.
7 conceptually shows a change in data stored in the delay RAM due to the processing. When the user selects the symphonic program, the arithmetic unit of the DSP executes this program, so that the tone waveform data subjected to the symphonic processing is written into the delay RAM. Then, the musical tone waveform data read out from the delay RAM with a delay is output from the DSP and transmitted to a digital / analog converter (time T in FIG. 10).
0 to T1 and FIG. 11 (a)). During execution of this symphonic program, if the user selects a new pitch change program instead of this program, the CPU of the electronic musical instrument first instructs the DSP to mute the tone waveform data read from the delay RAM. (Time T1 in FIG. 10). As a result, the output level of the musical sound waveform data subjected to the symphonic processing from the DSP gradually decreases (from time T1 to T2 in FIG. 10).

[0005] When the output level becomes zero, the CPU instructs the DS to clear the tone waveform data in the delay RAM.
P is instructed (time T2 in FIG. 10). As a result, the musical sound waveform data on which the symphonic processing has been performed
It is cleared from M (FIG. 11B). Then CP
U switches the program supplied to the arithmetic unit of the DSP from the program for symphonic to the program for pitch change (time T3 in FIG. 10). The CPU determines whether or not the clearing of the tone waveform data in the delay RAM has been completed, and upon completion (time T4 in FIG. 10 and time T4 in FIG. 1).
1 (c)), the mute is instructed to the DSP (time T5 in FIG. 10). When the clearing of the tone waveform data in the delay RAM is completed, the tone waveform data subjected to the pitch change processing is written into the delay RAM by the execution unit of the DSP executing the pitch change program. (FIG. 11D). As a result, the musical tone waveform data read out from the delay RAM with a delay is output from the DSP to
It is transmitted to an analog converter and the like.

[0006]

In such a conventional program switching method, in order to start writing the tone waveform data into the delay RAM by executing the program after the switching, the program before the switching must be executed. It is necessary to wait for the tone waveform data written in the delay RAM to be cleared. However, the time required for this clearing (from time T2 to T4 in FIG. 10)
Is usually the time during which the musical tone waveform data can be delayed by the delay RAM (for example, 100 to 2
(Approximately 00 milliseconds). Also, Japanese Patent Application Laid-Open No. Hei 6-259249 mentioned above proposes a method of performing this clearing at a high speed, but it still inevitably takes some time. Therefore, when the program is switched, a state in which the sound effect is not given to the musical tone continues for a considerable time, and there is a possibility that the performance with the electronic musical instrument may be disturbed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is directed to a signal processing device including such a DSP, or generally, by executing a microprogram on data input as a digital signal. An arithmetic unit for performing signal processing, a storage unit for writing and reading data in the course of executing the program, and selectively switching any one of a plurality of types of microprograms to supply the arithmetic unit It is an object of the present invention to provide a signal processing device provided with a program supply means for reducing the time required for switching microprograms.

[0008]

A signal processing apparatus according to the present invention is a signal processing apparatus comprising the above-mentioned arithmetic means, storage means and program supply means, wherein a program supplied from the program supply means is different. Identification information supply means for supplying identification information whose value changes each time the program is switched to a program of the type, and when the data is written to the storage means, supplied from the identification information supply means in accordance with the program currently being executed. An identification information writing unit that writes the identification information together with the identification information, and a process for the data read from the storage unit in accordance with the value of the identification information read together with the data from the storage unit And control means for controlling the

[0009]

When data is written to the storage means by executing a certain type of program, the identification information of a certain value supplied from the identification information supply means in accordance with the program is:
The data is written together with the data into the storage means by the identification information writing means. Thereafter, when the program supplied from the program supply unit is switched to another type of program, the value of the identification information supplied from the identification information supply unit changes, and the changed identification information is used to execute the program after switching. When writing data to storage means by
The data is written in the storage means together with the data. That is,
Before and after the switching of the program, identification information having different values is written to the storage means together with the data. Thus, whether the data read from the storage means has been written to the storage means by executing the program before switching or the data written to the storage means by executing the program after switching can be determined by the storage means. Can be identified by the value of the identification information read out together with the data.

The control means controls the processing for the data in accordance with the value of the identification information (ie, according to the identification result). Although the content of the processing to be controlled by the control means may be various,
When applied to a signal processing device including P, it is of course preferable to control the output processing of the data from the device. As a specific example of such control of the output processing, while the value of the identification information is not a value corresponding to the program currently being executed (that is, the data read from the storage means is stored in the storage means by executing the program before switching). While the data is written, the output of the data from the device is restricted, and when the value of the identification information becomes a value corresponding to the program currently being executed (that is, stored by executing the program after switching). When the data written in the means is read from the storage means), it is possible to cancel the restriction.

As described above, whether the data read from the storage means is written in the storage means by executing the program before switching or is written in the storage means by executing the program after switching. Can be identified, and the output processing of the data from the device can be controlled by the identification result. Therefore,
Even if the data in the storage means is immediately started to be written by executing the program after the switching without clearing the data in the storage means as in the related art, the data written in the storage means by the execution of the program before the switching is used to switch the program. Output from the device later can be prevented. As a result, the time required for such clearing (the time corresponding to the time T2 to T4 in FIG. 10 described above) becomes unnecessary, and the time required for switching the program is reduced.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing the overall configuration of an electronic musical instrument employing a signal processing device according to one embodiment of the present invention. This electronic musical instrument is provided with a CPU 1 for controlling various units and executing various processes.
The RAM 3, keyboard 4, display 5, operator group 6, tone generator 7 and DSP 8 are connected to the CPU 1 via a data and address bus 9. The tone waveform data generated from the tone generator 7 is input to the DSP 8. The DSP 8 performs a numerical calculation process and a delay process for adding sound to the musical tone waveform data, and is provided with a delay RAM 10 externally. The tone waveform data that has been processed by the DSP 8 is D /
It is sent to a sound system (not shown) via an A (digital / analog) converter (not shown).

FIG. 2 is a block diagram showing an example of the configuration of the DSP 8. The microprogram generation unit 11 has a CP
Under the control of U1, a plurality of types of microprograms (for example, a total of 11 types of programs such as reverb, chorus, symphonic, and pitch change) describing numerical calculation processing and delay processing for sound effects. The program selected by the user through the operation of the operator group 6 is supplied to the arithmetic unit 12. Further, the microprogram generator 11 supplies a control code W / R for instructing writing or reading of data among the control codes of the program to the write enable pin WE of the delay RAM 10.

As an example, a microprogram generator 11
Is a program memory (ROM) storing the above 11 types of microprograms, an address register storing head address data (data indicating a head address of the selected program in the program memory) provided from the CPU 1, and an address register. An address counter that starts counting from the read head address and supplies the count value to the program memory as read address data. The program read from the program memory according to the read address data is supplied to the arithmetic unit 12. You. However, as another example,
RO of electronic musical instrument instead of microprogram generator 11
The M11 may store the above 11 types of microprograms, and the microprogram generator 11 may be provided with a RAM for writing a program selected by the user among them.

The arithmetic unit 12 converts the tone waveform data input from the tone generator 7 via the multiplier 17 into C
Using data such as coefficient data given from PU1,
The program supplied from the micro program generator 11 is executed. The delay address generating unit 13
Based on the delay address data supplied from the CPU, address data designating an address at which the tone waveform data is to be written or read is generated and supplied to the address pin A of the delay RAM 10. Specifically, the write address data is data that is sequentially counted down from the last address of the delay RAM 10 toward the head address. When the head address is reached, the write address data returns to the last address and counts down again.

In the delay RAM 10, the control code W
In accordance with / R, the musical tone waveform data given from the arithmetic unit 12 is written to the address specified by the address data, or the musical tone waveform data is read from the address specified by the address data, and is sent to the arithmetic unit 12. By sending the data, the tone waveform data is subjected to delay processing. As an example, one address of the delay RAM 10 is 16
Although one word of musical tone waveform data is 24 bits, one word of musical tone waveform data is stored in two addresses. Therefore, in the delay RAM 10, 3 of two adjacent addresses
Of the 2-bit area, only the 24-bit area is used for delay processing. The tone waveform data that has been subjected to the delay processing in this manner is added to the tone waveform data that has not been subjected to the delay processing in the arithmetic unit 12 and sent from the arithmetic unit 12 via the multiplier 18 to the above-described D / A converter. .

The multipliers 17 and 18 multiply the interpolated signal from the interpolator 16 by the musical tone waveform data. When the program supplied from the microprogram generator 11 to the calculator 12 is switched, As will be described later, the interpolation section 16 is used to mute the musical tone waveform data and cancel the mute. However,
As another example, if the tone generator 7 mutes or cancels the mute of the tone waveform data to be supplied to the DSP 8 at the time of switching the program, it is not necessary to provide the interpolation unit 16 in the DSP 8. Absent.

As disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 6-259249, the DSP 8 is formed by assembling a predetermined number of blocks each of which independently performs processing for imparting an acoustic effect. Is also good. That is, the microprogram generation unit 11 supplies a predetermined number (for example, five) of the above-mentioned 11 types of programs to the arithmetic unit 12 in a time-division manner, and the arithmetic unit 12 subjects the predetermined number of programs to the time-division The delay address generator 13 may divide the delay RAM 10 into the predetermined number of areas corresponding to each block and generate address data for each area in a time-division manner. In such a case, a predetermined number of types of sound effect imparting processes arbitrarily selected by the user from the above-described 11 types of sound effects can be applied to the tone waveform data in each block simultaneously and in parallel.

As a feature of the present invention, the DSP 8
A control unit 14 and a 1-bit flag register 15 are provided to control the output of the musical tone waveform data to the A converter under an instruction from the CPU 1. The control code W / R output from the microprogram generator 11 is
The control unit 14 is also provided.

The flag register 15 is a register for holding a 1-bit flag ('0' or '1') based on a signal supplied from the control unit 14, and as an example, a flip-flop in which the flag is inverted by a toggle method. Consists of The flag from the flag register 15 is stored in the control unit 1
4, and is input to a predetermined 1-bit pin (for example, a 16-bit (most significant bit) pin) of the 16-bit data input pins DI of the delay RAM 10. On the other hand, the tone waveform data (24 bits as described above) of each word sent from the arithmetic section 12 to the delay RAM 10 is a pin (12 bits) other than the predetermined pin among the data input pins DI. For example, pins from the 4th bit to the 15th bit are input twice. Therefore, when the control code W / R indicates write, as shown in FIG. 3, the most significant bit of the address specified by the address data from the delay address generator 13 is transmitted from the flag register 15 to the uppermost bit. A flag ('0' or '1') is written, and 1 is set from the fourth bit of the address.
The musical tone waveform data is written by the fifth bit.

The data output from the most significant bit of the 16-bit data output pins DO of the delay RAM 10 is input to the control unit 14, and is output from the fourth bit to the 15th bit.
The data output from the pins up to the bit is
Is input to Therefore, when the control code W / R indicates the reading, the flag ('0' or '1') read from the most significant bit of the address specified by the address data from the delay address generating unit 13 ') Is input to the control unit 14, and the musical tone waveform data read from the 4th to 15th bits of the address is input to the arithmetic unit 12.

The interpolator 16 is supplied with a signal for instructing mute or cancellation of mute (and a signal for instructing interpolation speed) from the controller 14. When the mute is instructed in the state where the cancellation of the mute is instructed, the interpolating unit 16 supplies the multipliers 17 and 18 with the interpolation signal that gradually decreases from “1” to “0” at the instructed speed. give. The multipliers 17 and 18 multiply the interpolation signal by the musical tone waveform data. As a result, the level of the tone waveform data supplied from the tone generator 7 to the arithmetic unit 12 and the level of the tone waveform data transmitted from the arithmetic unit 12 to the D / A converter gradually decrease to zero. Thereafter, when an instruction to cancel muting is given, the interpolating unit 16 supplies the multipliers 17 and 18 with interpolation signals that gradually increase from '0' to '1' at the designated speed. Multiplier 17
In steps (18) and (18), the interpolation signal is multiplied by the musical tone waveform data, whereby the level of the musical tone waveform data is restored to the original level even if the level gradually increases from zero.

Next, among the processing executed by the CPU 1, the program switching processing related to the present invention and the processing executed by the control unit 14 of the DSP 8 will be described with reference to FIGS. In the following, for the sake of convenience, the description will be made assuming that the DSP 8 is not a set of a predetermined number of blocks as described above, and therefore performs only one type of sound effect imparting process on musical tone waveform data at a time. I will. However, even when the DSP 8 performs a predetermined number of types of processing for imparting sound effects to the musical tone waveform data in each block simultaneously and in parallel, any one or more of the blocks will be described below. Needless to say, the same processing for program switching as described above can be executed.

FIG. 4 is a flowchart showing an example of a main routine executed by the CPU 1. In the main routine, first, a predetermined initial setting (step 100) is performed, and then the microprogram generation unit 11 sends the calculation unit 12
A loop consisting of "program switching processing" for switching the program supplied to the electronic musical instrument (step 101) and other normal processing (key event processing, operation switch-on event processing, sound generation processing, etc.) for the electronic musical instrument (step 102). Repeat the process.

FIG. 5 is a flowchart showing an example of the program switching process. FIG. 6 is a flowchart illustrating an example of a process performed by the control unit 14. FIG. 7 is a diagram showing the contents of the processing of FIGS. 5 and 6 along with the output level of the musical tone waveform data over time, and FIG. 8 conceptually shows the change of the data stored in the delay RAM due to the processing. FIG. 9 is a diagram showing flags written in the delay RAM 10 by the processing.

A program before switching in the arithmetic unit 12 (as an example, a program for symphony)
Is executed, the sound waveform data subjected to the symphonic processing is written in the delay RAM 10, and the sound waveform data is read out from the delay RAM 10 and transmitted from the DSP 8 to the D / A converter. (Times T0 to T1 in FIG. 7 and FIG. 8A). At this time, the flag from the flag register 15 (eg, “1”) is written in the most significant bit of each address of the delay RAM 10 (FIG. 9A).

In this state, in the program switching process of FIG. 5, first, it is determined whether or not another type of program has been selected in place of the symphonic program (step 200). If not selected, the routine returns. On the other hand, if selected (for example, a program for pitch change is selected),
Whether a predetermined minimum time (for example, a time approximately equal to the delay time of the tone waveform data by the delay RAM 10) has elapsed from the time when the instruction to switch the program in the later-described step 202 was issued immediately before has elapsed. It is determined whether or not it is (step 201). If it has not passed, the process returns. On the other hand, if the time has elapsed, a signal instructing to mute the musical tone waveform data is generated and given to the control unit 14 (step 202).

Referring to FIG. 6, the control unit 14 determines whether or not the above signal has been given from the CPU 1 (step 300). When the above signal is given, the control unit 14 controls the interpolation unit 16 to control the tone waveform data. Mute (step 301,
Time T1 in FIG. 7). As a result, the supply level of the tone waveform data subjected to the symphonic processing to the D / A converter gradually decreases (from time T1 to T2 in FIG. 7).

Returning to FIG. 5, the CPU 1 determines that the level is
It is repeatedly determined whether or not the value has decreased to a predetermined value such that noise does not occur even when the program is switched (step 203). If the answer is yes, the program is switched (specifically, the program supplied from the microprogram generation unit 11 to the calculation unit 12 is switched from the symphonic program to the pitch change program, and the coefficient given to the calculation unit 12 is changed. Data such as data is rewritten to pitch change data) (step 204, time T2 in FIG. 7). Thereby, the operation unit 1
In 2, the execution of the pitch change program is started in place of the symphonic program. Subsequently, a signal for instructing the inversion of the flag of the flag register 15 is generated and given to the control unit 14 (step 205).

Referring to FIG. 6, the control unit 14 determines whether or not the above signal has been supplied from the CPU 1 (step 302).
The flag of No. 5 is inverted (step 303, time T3 in FIG. 7). As a result, when the flag “0” is input to the control unit 14 and the tone waveform data subjected to the pitch change processing is written to the delay RAM 10 (FIG. 8).
(B)) The flag '0' (that is, the flag inverted from before the program switching) is written in the most significant bit of the same address (FIG. 9 (b)).

Next, it is repeatedly determined based on the control code R / W whether or not the tone waveform data has begun to be read from the delay RAM 10 (step 304). The flag provided from the RAM 10 to the control unit 14 (that is, the flag read from the most significant bit of the address of the delay RAM 10)
It is determined whether or not the value matches the flag '0' given from the flag register 15 to the control unit 14 (step 30).
5). While the tone waveform data subjected to the symphonic processing is being read from the delay RAM 10, the delay R
Since the flag '1' is given from the AM 10 to the control unit 14, the two flags do not match. If they do not match, the process returns to step 304, and the processes of steps 304 and 305 are repeated. Thereafter, when all the tone waveform data subjected to the symphonic processing is read out from the delay RAM 10, the tone waveform data subjected to the pitch change processing is subsequently read out from the delay RAM 10 (FIG. 8 (c)). )), The flag '0' is input from the delay RAM 10 to the control unit 14, so that the two flags match. When the two flags match, the interpolation unit 16 is controlled to release the mute (step 306,
Time T4 in FIG. 7). As a result, the supply level of the tone waveform data subjected to the pitch change processing to the D / A converter gradually increases.

The reason why step 201 in FIG. 5 is provided is as follows. If, for example, reverb is selected before the symphonic is selected, after switching from the reverb to the symphonic, the pitch change is selected instead of the symphonic within a time shorter than the delay time by the delay RAM 10. In this case, if the switching is performed continuously, the control unit 1
4 continuously inverts the flag of the flag register 15 twice, so that the reverb flag and the current (pitch change) flag match.
For this reason, after switching to the pitch change, the tone waveform data subjected to the reverb processing may be output from the DSP 8. Therefore, by not switching within a time shorter than the above-mentioned delay time,
They tried to prevent such a situation. More specifically, the processing in step 201 includes a counter (not shown) that accumulates a constant value in accordance with a clock pulse.
This can be realized by resetting each time the program is switched in step 04 and determining in step 201 whether the count value is equal to or greater than the value corresponding to the minimum time. In the example of FIG. 5, the process returns when the determination in step 201 is “no”. However, as another example, when the determination in step 201 is “no”, step 201 is repeatedly executed to wait for the elapse of the delay time. After that, the process may proceed to step 202 to instruct the switching.

As described above, in this signal processing device, the flag is written in the delay RAM 10 together with the musical tone waveform data, and the flag is inverted when the program is switched. The flag read out together with the musical tone waveform data identifies whether the musical tone waveform data read from the delay RAM 10 is due to the execution of the program before switching or the program after switching. Based on the identification result, data written to the delay RAM 10 by the program before switching is prevented from being sent from the DSP to the D / A converter after switching of the program. Thus, as is clear from comparison between FIGS. 7 and 8 and FIGS. 10 and 11 of the conventional example, the time required to clear the data in the delay RAM 10 (FIG.
The time required for switching the program is reduced by the amount of time (time corresponding to time T2 to T4 at 0) being unnecessary.

In this embodiment, the flag is written in the most significant bit of each address of the delay RAM. However, the present invention is not limited to this, and the flag may be written in an appropriate bit position other than the most significant bit. The good thing is, of course. Further, in this embodiment, the identification information composed of the 1-bit flag held in the flag register is written into the delay RAM while being inverted every time the program is switched. However, the present invention is not limited to this. May be written to a predetermined bit position of two or more bits in the delay RAM while changing the value each time the program is switched. When the identification information has two or more bits as described above, the identification information has four or more types, and therefore, it may be possible to omit the processing in step 201 in FIG.
That is, if there are four or more pieces of identification information, as in the above-described example, an instruction to switch from reverb to symphonic is issued, and then, from the symphonic to the pitch change within a shorter time than the delay time by the delay RAM 10. Even if the switching instruction is continuously performed, since the identification information about the reverb and the identification information about the pitch change are different, the tone waveform data subjected to the reverb processing is output after the switching to the pitch change. Nothing happens.

In this embodiment, the present invention is applied to an electronic musical instrument provided with a DSP. However, the present invention is not limited to this.
The present invention may be applied to other tone generators provided with an SP. Further, the digital signal processing is performed by executing a microprogram on data input as a digital signal, such as an arithmetic unit of a DSP. Arithmetic means for applying, storage means for writing and reading data in the course of execution of a program, such as a RAM for delay, and a plurality of types of micro-program generation units for a CPU and a DSP of a musical tone generator. The present invention may be applied to any other appropriate signal processing device including a program supply unit that supplies any one of the microprograms to the arithmetic unit.

[0036]

As described above, according to the present invention, there is provided an arithmetic means for executing a program supplied by being selectively switched from a plurality of types of microprograms, and for writing and writing data in the course of executing the program. In a signal processing device (for example, a signal processing device including a DSP) having storage means for performing reading, the time required for program switching can be reduced, and therefore, the execution of the program after switching can be reduced. There is an excellent effect that writing of data to the storage means can be started quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an electronic musical instrument to which a signal processing device according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing an example of the configuration of the DSP shown in FIG. 1;

FIG. 3 is a diagram showing an example of data stored in a delay RAM.

FIG. 4 is a flowchart illustrating an example of a main routine executed by a CPU 1 of FIG. 1;

FIG. 5 is a flowchart illustrating an example of a process executed by a CPU 1 of FIG. 1;

FIG. 6 is a flowchart illustrating an example of a process executed by a control unit 14 of FIG. 2;

FIG. 7 is a diagram showing the content of processing for program switching according to the present invention over time.

FIG. 8 is a diagram showing a change in data stored in a delay RAM due to a program switching process according to the present invention.

FIG. 9 is a diagram showing flags written to a delay RAM by a process for switching programs according to the present invention.

FIG. 10 is a diagram showing the contents of processing for conventional program switching over time.

FIG. 11 is a diagram showing a change in data stored in a delay RAM due to a conventional program switching process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 4 Keyboard 5 Display 6 Operator group 7 Tone generator 8 DSP 9 Data and address bus 10 RAM for delay 11 Microprogram generation unit 12 Operation unit 13 Address generation unit for delay 14 Control unit 15 Flag register 16 Interpolator 17, 18 Multiplier

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-250418 (JP, A) Patent 2765470 (JP, B2) JP-B-63-36577 (JP, B2) JP-B-63-37970 (JP, A) B2) Japanese Patent Publication No. 63-37971 (JP, B2) Japanese Patent Publication No. 63-37972 (JP, B2) Japanese Patent Publication No. 63-37973 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) G10H 1/02 G06F 17/10 H03H 17/00-17/08

Claims (7)

(57) [Claims] An arithmetic unit for performing digital signal processing by executing a microprogram on data input as a digital signal, and a storage unit for writing and reading the data in the course of executing the program And a program supply unit for selectively switching any one of a plurality of types of microprograms and supplying the program to the arithmetic unit. In the signal processing device, the program supplied from the program supply unit is different. Identification information supply means for supplying identification information whose value changes each time the program is switched to a program of the type, and when data is written to the storage means, supplied from the identification information supply means in accordance with the program currently being executed. Identification information writing means for writing the identification information together into the storage means; Depending on the value of the identification information read out with the data from the storage means, the signal processing apparatus being characterized in that and control means for controlling the processing for the data read out from said memory means. 2. The control device according to claim 1, wherein the control unit is configured to read the value of the information read from the storage unit together with the data, and a value of the identification information supplied from the identification information supply unit in correspondence with a program currently being executed. 2. The signal processing device according to claim 1, wherein the signal processing device controls a process on the data based on a determination as to whether or not the data match. 3. The signal processing device according to claim 1, wherein the control unit controls an output process of the data read from the storage unit from the device. 4. The control means restricts output of the data from the device as long as the value of the identification information read out together with the data from the storage means is not a value corresponding to a program currently being executed. 4. The signal processing device according to claim 3, wherein the restriction is released when the value of the identification information becomes a value corresponding to the program currently being executed. 5. The identification information writing means, for each storage area of the storage means in which one word of data is written,
5. The signal processing device according to claim 1, wherein the identification information is written at a predetermined bit position. 6. The signal according to claim 1, wherein the identification information supply means supplies the identification information composed of a 1-bit flag with a value inverted each time a program is switched. Processing equipment. 7. The arithmetic means of the digital signal processor which performs a numerical calculation process and a delay process for imparting an acoustic effect to musical sound waveform data, and the storage means stores the musical sound waveform data into the musical sound waveform data. 7. The signal processing device according to claim 1, wherein the signal processing device is a delay RAM provided for performing a delay process.