JP3035263B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display using an active matrix substrate.

[0002]

2. Description of the Related Art In recent years, active matrix display devices using a liquid crystal or the like as a display medium have been actively studied. In particular, active matrix display devices using liquid crystals have been studied as flat displays, and the results have been steadily increasing. Such an active matrix type liquid crystal display device includes a pixel electrode, a thin film transistor (TF)
T) and the like, an active matrix substrate formed with a counter electrode, a counter substrate formed with a counter electrode, and a liquid crystal layer sealed between these substrates.

In particular, in an active matrix type liquid crystal display (LCD) designed to be small and high definition, the area of a picture element is small due to its design, so that it is formed between a picture element electrode and a counter electrode. The capacitance of the capacitor becomes smaller.

Therefore, there arises a problem that the video signal cannot be held for a required time. In addition, there is a problem that the potential of the bus wiring greatly varies with respect to the potential of the pixel electrode. Therefore, an additional capacitance is provided to compensate for the lack of capacitance between the pixel electrode and the counter electrode.

FIG. 4 is a plan view of one picture element of a conventional active matrix substrate having an additional capacitor, and FIG. 5 is a cross-sectional view taken along a TFT 25 of the active matrix substrate (BB 'in FIG. 4). FIG.

In this active matrix substrate, a semiconductor layer 30 made of polycrystalline silicon having channel layers 12a and 12b, a source electrode 23 and a drain electrode 24 is formed on an insulating substrate 11. The electrical resistance of the portion of the semiconductor layer 30 other than the channel layers 12a and 12b is reduced by doping by ion implantation.

On the substrate 11 covering the semiconductor layer 30,
A gate insulating film 13 is formed, and on this gate insulating film 13, gate electrodes 3a, 3b and additional capacitance electrode 6 made of either n ⁺ or p ⁺ polycrystalline Si are formed. The above-described doping is performed by the gate electrode 3a,
3b is used as a mask. The gate electrode 3a is shown in FIG.
As shown in (1), the gate bus line 1 is composed of a part of itself, and the gate electrode 3b is composed of a portion branched from the gate bus line 1. The additional capacitance electrode 6 is a part of a band-shaped additional capacitance common line 8 as shown in FIG. 1, and an additional capacitance is formed at a portion where the additional capacitance common line 8 and the pixel electrode 4 face each other.

Further, on the entire surface of the substrate 11 covering the gate electrodes 3a and 3b, a gate-source interlayer insulating film 14 is formed.
Are formed. In the gate-source interlayer insulating film 14, through holes 7a and 7b are provided. On the through hole 7a, a metal layer 10a branched from the source bus wiring 2 is formed. Further, there is a metal layer 10b formed simultaneously and separately from the branched metal layer 10a. The source bus line 2 is connected to the source electrode 23 of the TFT 25 via the through hole 7a. Here, the TFT 25 has a structure called a dual gate having gate electrodes 3a and 3b.

One contact hole 7b is provided in the TFT 2
In order to ensure electrical connection between the drain electrode 24 of No. 5 and the metal layer 10b, it is filled with a metal such as Al.

On top of this, a first interlayer insulating film 17, a light shielding film 15, a second interlayer insulating film 18, and a picture element electrode 4 are formed in this order. The light-shielding film 15 and the metal layer 10b are connected to the contact hole 9 provided in the first interlayer insulating film 17.
b. The light-shielding film 15 is formed of a Ti-W alloy or the like. This light-shielding film 15 is
It also plays a role of realizing an ohmic contact between a metal such as Al filling b and a pixel electrode 4 made of ITO or the like. The light-shielding film 15 and the pixel electrode 4 are connected via a contact hole 16b formed in the second interlayer insulating film 18.

[0011]

By the way, in this conventional substrate, after one of the gate bus lines 1 is turned on, the source bus line 2 which is first turned on is:
Since the time until the gate bus line 1 is turned off is sufficiently long, the video signal sent through the source bus line 2 is written into the picture element electrode 4 and the additional capacitance electrode 6 with a margin. However, in the source bus line 2 which is finally turned on, the time until the gate bus line 1 is turned off is short, so that there is a problem that the writing time of the video signal is restricted.

Furthermore, since the additional capacitance common wiring 8 is formed of n ⁺ polycrystalline Si, the resistance cannot be said to be sufficiently small. Therefore, the signal sent to the additional capacitance common line 8 is delayed, so that the video signal cannot be written within the above-mentioned limited writing time, and the potential written to the pixel electrode 4 fluctuates. is there. This problem will be described with reference to FIG.

FIG. 6 shows an equivalent circuit diagram of one picture element portion. A pixel electrode 33 connected to the drain electrode 32 of the TFT 31, in between the counter electrode 34 that the facing to the picture element electrode 33 and the counter electrode wiring is connected, the capacitance C _LC across the liquid crystal layer is formed Is done. The drain electrode 32 of the TFT31 is connected to the additional capacitor common line through an additional capacitor C _S. Further, a capacitance C _gd is formed between the gate electrode 35 and the drain electrode 32 of the TFT 31.

At this time, when a gate-on signal is sent to the gate bus wiring of the TFT, the TFT is turned on,
The video signal _Vd is written to the source bus wiring. Here, the additional capacitor common wires time constant of the signal transduction of tau _CS, when a signal writing time T _ON to the picture element electrode, when the condition of tau _CS << T _ON is not satisfied, to additional capacitance C _S Insufficient charging causes a problem that the potential of the pixel electrode fluctuates.

By the way, the TFT is turned off, and τ _CS
The potential V _d ′ of the pixel electrode corresponding to the actual display state after a sufficiently long time has elapsed is expressed by the following equation.

V _d ′ = V _d- ｛C _gd / (C _gd + C _LC + C _S ) △ {V _g } -a (1) where ΔV _g is the gate potential when the TFT is in the ON state. This is the difference from the gate potential in the off state. “a” represents a change in potential caused by insufficient charging of the additional capacitance within the writing time, and is represented by the following two equations.

A = V _d · exp (−T _on / τ _CS ) · {C _S / (C _gd + C _LC + C _S )} (2) The second term in the above equation (1) turns off the TFT. Therefore, the change in the potential of the pixel electrode due to the change in the voltage of the gate bus line is shown. In order to perform a faithful display by the written video signal, the value of the second term in Equation 1 and the value of a in Equation 2 must be reduced. In order to reduce the value of the second term of the equation (1), it is necessary that C _gd ≪C _LC + C _S (3) is satisfied. In a high-definition active matrix substrate, the picture element electrodes are small and the _CLC is small.
In order to satisfy the condition of Equation (3), a certain amount of additional capacitance C is required.
_S is required.

[0018] Since the need thus additional capacitance C _S is a degree of size, in order to reduce the value of _{a, T on «τ CS ... (4} ) it is necessary to hold. In particular, the driving circuit is TFT
With a small and high-definition active matrix substrate formed on the same substrate as the array, it is difficult to satisfy the above four conditions. The reason is as follows.

(1) The number of gate bus lines increases,
The time allotted per gate bus line is reduced.

(2) In the method of mounting the driver IC,
There is no problem because the video signal is output to all the source bus wirings at the same time. However, when the panel sample and hold method is adopted, the video signal is sequentially output to each source bus wiring, so that writing is performed last. The writing time in the source bus wiring is shortened.

(3) It is necessary to reduce the line width of the wiring in order to prevent a decrease in the aperture ratio due to the high definition of the display device. For this reason, the resistance of the additional capacitance common wiring increases, and τ _CS cannot be reduced.

(4) Even if the number of picture elements increases, the size of the additional capacitance common electrode per picture element cannot be reduced. Therefore, the sum of the additional capacitances connected to one additional capacitance common wiring increases, and τ _CS cannot be reduced.

As a solution to such a problem, it is conceivable to apply a voltage having the same potential as that of the counter electrode to both ends of the additional capacitance common wiring. However, this alone does not reduce the resistance of the additional capacitance common wiring sufficiently. Not a good solution.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide an active matrix substrate in which the resistance of wiring is reduced so that signal delay is less likely to occur.

[0025]

A liquid crystal display device according to the present invention comprises a thin film transistor having a gate electrode, a source electrode, and a drain electrode formed on a substrate, and a first interlayer insulating film over the thin film transistor. An active matrix substrate including the formed light-shielding film, a pixel electrode formed on the light-shielding film with a second interlayer insulating film interposed therebetween, an opposing substrate including an opposing electrode, In a liquid crystal display device constituted by a sealed liquid crystal layer, the light shielding film is formed of a metal material and formed over the thin film transistor,
It is characterized in that it has the same potential as that of the counter electrode formed on the counter substrate, thereby achieving the above object.

The light shielding film may be formed of W, Ti, Mo or Ti-W alloy.

Hereinafter, the operation of the present invention will be described.

In the present invention, since the light-shielding film for forming the additional capacitance is formed of a metal material and the resistance of the additional capacitance electrode is reduced, the problem of signal delay does not occur.

Further, since the light-shielding film is formed of a metal material, light leakage does not occur, for example, when polycrystalline silicon is used as the light-shielding film.

Further, since the light-shielding film has the same potential as the counter electrode, the capacitance formed between the light-shielding film and the pixel electrode also acts as an additional capacitance. It is also possible to double.

Since the light-shielding film also serves as an additional capacitance electrode, the area of the additional capacitance electrode other than the thin film transistor on the active matrix substrate can be reduced, so that the aperture ratio can be improved.

Further, by using W, Ti, Mo or Ti-W alloy as the light-shielding film, it can be easily used in the process and the resistance can be reduced, and the light applied to the thin film transistor can be effectively removed. Becomes possible.

[0033]

FIG. 3 is a schematic plan view of a liquid crystal display according to an embodiment of the present invention.

In this liquid crystal display device, a gate drive circuit 54, a source drive circuit 55, and a TFT array section 53 are formed on an insulating film substrate 11 made of glass or the like. In the TFT array section 53, a plurality of gate bus lines 1 as a number of parallel scanning lines extending from a gate drive circuit 54 are arranged.
From the source drive circuit 55, a number of source bus lines 2 as signal lines are arranged orthogonal to the gate bus lines 1. Further, an additional capacitance common line 8 is provided in parallel with the source bus line 2.

In a rectangular area between the two gate bus lines 1 and between the source bus line 2 and the additional capacitance common line 8, a TFT 25, a picture element 57 and an additional capacitance 27 are provided. . The gate electrode of the TFT 25 is connected to the gate bus line 1, and the source electrode is connected to the source bus line 2. The picture element 57 is configured such that liquid crystal is sealed between the picture element electrode connected to the drain electrode of the TFT 25 and the counter electrode on the counter substrate. Further, the additional capacitance common wiring 8 is connected to an electrode having the same potential as the counter electrode.

FIG. 1 is a plan view of one picture element on the active matrix substrate of the liquid crystal display device according to the present embodiment. FIG. 2 is a cross-sectional view along AA ′ in FIG. The configuration of this active matrix substrate will be described according to the manufacturing process.

First, for example, CVD is performed on the insulating substrate 11.
After patterning the semiconductor layer 30 made of polycrystalline Si by the method, an insulating film to be the gate insulating film 13 was formed on the entire surface of the substrate 11. This insulating film is formed, for example, by a CVD method,
It is formed by a sputtering method or a method in which the upper surface of the polycrystalline Si thin film 30 is thermally oxidized. Gate insulating film 13
Is about 100 nm, for example. The thickness of the semiconductor layer 30 is, for example, 40 to 80 nm.

Next, patterning was performed after low-resistance polycrystalline Si was deposited, thereby forming the gate bus wiring 1, the gate electrodes 3a and 3b, and the additional capacitance common wiring 8. The additional capacitance common wiring 8 includes the additional capacitance electrode 6 which is a protruding portion as shown in FIG. Then, using the gate electrodes 3a and 3b as a mask and a mask formed by photolithography, the semiconductor layer 3 is formed.
Ion implantation is performed on portions other than below the 0 gate electrode.
Thereby, the channel layers 12a and 12b are formed in the semiconductor layer 30.
Is formed.

Thereafter, a gate-source interlayer insulating film 14 having a thickness of, for example, 700 nm was formed on the entire surface of the substrate. Next, contact holes 7a and 7b and a contact hole 7c were formed in predetermined portions of the gate-source interlayer insulating film 14. Contact holes 7a, 7b, 7c
Are disposed on the source electrode 23, the drain electrode 24, and the additional capacitance common line 8, respectively.

Next, the source bus wiring 2 and the metal layer 10
a, 10b, 10c, etc. were simultaneously formed using a low resistance metal such as Al. At this time, the metal layers 10a, 10b, 1
0c is formed to fill the contact holes 7a, 7b, 7c, respectively, and is connected to the source electrode 23, the drain electrode 24, and the additional capacitance common wiring 8. Metal layer 10 projecting above gate-source interlayer insulating film 14
The layer thicknesses of a, 10b, and 10c are, for example, 600 nm. The metal layer 10a is a portion branched from the source bus line 2, and the source bus line 2 is connected to the source electrode 23 via the metal layer 10a and the contact hole 7a.

Next, a first interlayer insulating film 17 was formed on the entire surface of the substrate to a thickness of 600 nm by, for example, a CVD method. Next, contact holes 9b and 9c were formed in the first interlayer insulating film 17. This contact hole 9b
Is for connecting the drain electrode, and the contact hole 9c is for electrically connecting the light shielding film 15 and the additional capacitance common wiring 8. By connecting the light shielding film 15 and the additional capacitance common wiring 8, the light shielding film 1 is
5 has the same potential as the counter electrode.

Next, a light-shielding film 15 was formed so as to fill the contact holes 9b and 9c in addition to the upper portion of the TFT 25. The light shielding film 15 is made of a metal such as a Ti-W alloy, and has a thickness of, for example, 120 to 150 nm.
And The light shielding film 15 does not exist around the contact hole 9b. However, since the metal layer 10b is formed in this portion, light does not leak from a portion where the light shielding film 15 is not provided. The light-shielding film 15 can be made of a metal such as W, Ti, or Mo, in addition to the above-described Ti-W alloy. The light-shielding film 15 on the contact hole 9b is for obtaining an ohmic contact between the drain electrode 24 and a pixel electrode 4 described later.

After that, the second interlayer insulating film 18 is
m, the contact hole 16b is opened, and the pixel electrode 4 is formed.
Was formed.

Therefore, in the active matrix substrate of the liquid crystal display device according to the present embodiment thus configured, the light shielding film 15 and the additional capacitance common line 8 are formed in parallel, and the light shielding film 15 and the additional capacitance Common wiring 8
Are contact holes 7c, 9 provided in gate-source interlayer insulating film 14 and first interlayer insulating film 17, respectively.
c, the light-shielding film 1
5 has the same potential as the counter electrode, and has a circuit configuration in which the light-shielding film 15 and the additional capacitance common wiring 8 are connected in parallel, the resistance is reduced, and the occurrence of signal delay can be suppressed.

Further, since the light-shielding film 15 also serves as the additional capacitance common line 8, disconnection that occurs when the line width of the additional capacitance common line 8 is reduced to increase the aperture ratio can be prevented.

[0046]

As described above, in the liquid crystal display device of the present invention, the light-shielding film for forming the additional capacitance is formed of a metal material, and the resistance of the additional capacitance electrode is reduced. It will not happen.

Further, since the light-shielding film is formed of a metal material, light leakage does not occur, for example, when polycrystalline silicon is used as the light-shielding film.

Further, since the light-shielding film has the same potential as the counter electrode, the capacitance formed between the light-shielding film and the pixel electrode also acts as an additional capacitance. It is also possible to double.

Since the light-shielding film also serves as an additional capacitance electrode, the area of the additional capacitance electrode other than the thin film transistor on the active matrix substrate can be reduced, so that the aperture ratio can be improved.

Further, by using W, Ti, Mo or Ti-W alloy as the light-shielding film, it can be easily used in the process and the resistance can be reduced, and the light applied to the thin film transistor can be effectively removed. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a plan view showing one picture element on an active matrix substrate of a liquid crystal display device according to the present embodiment.

FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a schematic plan view showing an active matrix type liquid crystal display device including the active matrix substrate of FIG. 1;

FIG. 4 is a plan view showing one picture element on an active matrix substrate of a conventional liquid crystal display device.

FIG. 5 is a sectional view taken along the line BB ′ of FIG. 4;

FIG. 6 is an equivalent circuit diagram of one picture element portion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate bus wiring 2 Source bus wiring 3a, 3b Gate electrode 4 Pixel electrode 6 Additional capacitance electrode 7a, 7b, 7c Contact hole 8 Additional capacitance common electrode 9b, 9c Contact hole 10a, 10b, 10c Metal layer 11 Insulating substrate 12a , 12b channel layer 13 gate insulating film 14 gate-source interlayer insulating film 15 light shielding film 16b contact hole 17 first interlayer insulating film 18 second interlayer insulating film 23 source electrode 24 drain electrode 25 TFT 30 semiconductor layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-288824 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1335 500

Claims (2)

(57) [Claims] A thin-film transistor having a gate electrode, a source electrode, and a drain electrode formed on a substrate; a light-shielding film formed on the thin-film transistor via a first interlayer insulating film; A liquid crystal display comprising an active matrix substrate having picture element electrodes formed via a second interlayer insulating film, a counter substrate having a counter electrode, and a liquid crystal layer sealed between these two substrates. In the device, the light-shielding film is formed of a metal material and is formed so as to cover the thin-film transistor, and has the same potential as a counter electrode formed on the counter substrate. 2. The light-shielding film according to claim 1, wherein said light-shielding film is made of W, Ti, Mo, Ti-
The liquid crystal display device according to claim 1, comprising a W alloy.