JP3032040B2 - Automatic optical disc playback signal pulse correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing signals recorded on optical disks such as magneto-optical disks and phase-change optical disks, as well as write-once and read-only optical disks.

[0002]

2. Description of the Related Art Digital recording is generally used for optical disks such as magneto-optical disks and phase-change optical disks. However, in order to convert a simple PCM signal into a signal more suitable for optical disk recording, (1, 7) ) A signal subjected to modulation most suitable for the purpose among various modulation schemes such as RLL modulation and (2,7) RLL modulation is used. As a method of recording a code string composed of "0" and "1", a pit position recording method (recording method between marks) and a pit edge recording method (mark length recording method) are formed. is there. In order to increase the recording density, the pit edge recording method is more advantageous. Hereinafter, the magneto-optical disk will be mainly described, but the same applies to a phase change optical disk.

FIG. 14 is a waveform diagram for explaining the pit edge recording method. (I) is a data word obtained by PCM-modulating an audio signal or a video signal, T is a bit interval, and (m) is a code word obtained from the data word of the sequence (i) by (1,7) RLL modulation. In the waveform train, the arrow indicates a code word boundary. Discrimination window width Tw = 2T / 3, minimum magnetization reversal interval Tmi
n = 4T / 3, maximum magnetization reversal interval Tmax = 16T / 3
It is. (N) is a signal obtained by recording the pit / edge on the track of the magneto-optical disk by the signal (m). The original signal is detected by detecting both ends of the mark. (J) is a reproduced waveform of the (n) signal from the magneto-optical disk. In the pit edge recording method, the leading edge and the trailing edge of the recording mark are the positions of the pulses to be detected.
In this case, the waveform (j) may be sliced. More specifically, as described later, the original recorded waveform can be obtained by binarizing the reproduced signal by comparing it with an appropriate threshold value.

When recording on a magneto-optical disk with a laser beam, the recording power often deviates from an optimum value in a practical state. Further, the sensitivity of the recording medium may not be constant on the optical disc. For these reasons, the recording mark shape deviates from the regular shape.

FIG. 15 shows an example of an eye pattern when a (1, 7) RLL modulation code is recorded on a pit edge.
It goes without saying that the shorter the mark length at the time of recording, the smaller the amplitude, and the center level of the eye opening also fluctuates up and down with the fluctuation of the mark length. For this reason, when the reproduction signal (j) is sliced at the fixed slice level SL during reproduction to restore the original signal, the duty ratio of the pulse fluctuates, and thus a data error occurs.
In order to improve this, it can be seen that by appropriately selecting the above-mentioned slice level SL in accordance with the waveform of FIG. 14, the duty fluctuation of the reproduction signal pulse is reduced.

FIG. 16 shows an example of an amplitude detection type DSL (data slice level) circuit for automatically correcting a slice level (Trikeps Corporation white series).
No. 86, “Signal processing technology in optical recording”, Chapter 7). Data recording on a magneto-optical disk is usually performed in sector units. In the first part of each sector, a preamble area for setting the phase synchronization of the demodulation clock is approximately 10 bytes.
Bytes are prepared. Usually, the highest recording frequency is used as the preamble signal. The circuit of FIG. 16 automatically corrects the slice level SL using the preamble signal. The reproduction signal from the optical disk passes through the amplifier 3 and the waveform equalization circuit 4 from the input terminal 1 and enters the center value detection circuit 5 of the peak rectification system. In the center value detection circuit 5,
The center value of the upper and lower peaks of the input waveform is always output by a combination of a diode, a resistor and a capacitor connected in opposite directions, and is applied to the sample and hold circuit 6. On the other hand, the preamble gate signal enters the sample hold circuit 6 from the input terminal 2, samples and holds the output of the center value detection circuit 5, and enters one input of the comparator 7. Therefore, it is possible to obtain a pulse obtained by slicing the reproduction signal applied to the other input of the comparator 7 at the center value of the upper and lower peak values of the preamble signal.

It has been experimentally proved that when the threshold level of the comparator 7 shown in FIG. 16 is a fixed value, this value may be used as the center value of the minimum amplitude level of the reproduced signal. Since the preamble provided at the head of the normal sector is the reproduction signal having the minimum amplitude, in FIG. 16, the correction is performed for each sector using the slice level correction voltage obtained during the preamble period.

[0008]

The above-mentioned conventional system has the following disadvantages. (A) In the above-described amplitude detection type DSL circuit, since the slice level to be corrected is obtained by detecting the amplitude of the reproduced signal, the reproduced signal amplitude is compensated for the signal subjected to the waveform equalization by the waveform equalization. Since the amplitude becomes almost constant irrespective of the recording frequency, there is not much correction effect. (B) Since the correction voltage is detected only in the preamble area, the band to be corrected is determined by the sector frequency and cannot be arbitrarily selected. Also,
It is difficult to increase the bandwidth. (C) In the reproduced signal of the preamble area at the head of the sector, sag occurs due to DC cut by a capacitor or the like in the reproducing circuit, and the heat value of the laser fluctuates during recording, and the recording power and wavelength fluctuate in the middle of the sector. May be
If the DC component in that portion does not match the entire sector area, an error occurs in the correction voltage, and the correction may not operate normally. (D) an O-flop Nrupu control, control over the edge shift amount after binarization is not performed nothing.

The present invention eliminates the above-mentioned drawbacks of the prior art, so that even if the shape of a recording mark fluctuates due to fluctuations in the emission power of a semiconductor laser, fluctuations in the sensitivity of a recording medium on an optical disk, or the like, the reproduction signal can be reproduced. Minimizing the occurrence of data errors by keeping the duty ratio unchanged
It is another object of the present invention to provide an optical disk reproduction signal pulse automatic correction device capable of arbitrarily setting a correction frequency band .

[0010]

In order to solve this problem, an automatic optical disk reproduction signal pulse correcting apparatus according to the present invention compares an optical disk reproduction signal with a slice level.
A comparator for obtaining a binary output, from the comparator
The rising edge and rising edge of the mark length of the resulting binarized output
An edge for extracting the edge signal that detected the falling edge
A recovery clock from the edge signal and the edge signal.
The recovered clock and a rising edge of the edge signal;
Pump-up signal that detects the phase difference from the falling edge
A PLL circuit for taking out the No. and the pump-down signal, the
Binarized output, pump up signal and pump down
Proportional to the average value of the rising edge timing from the signal
To take out the first voltage to rise
Circuit, the binarized output, the pump-up signal and the
The falling edge timing from the pump down signal
Falling tie to extract the second voltage proportional to the average value
A averaging circuit, the first voltage and the second voltage
Signal generation circuit for extracting the difference voltage proportional to the difference
And the difference voltage is limited to a range between the upper limit and the lower limit.
Both of which are obtained by compensating the frequency characteristics of the differential voltage.
A voltage is generated and the slice level is supplied to the comparator.
Slice level control voltage generation as feedback
And a circuit . In addition,
The raw signal is compared with the slice level to obtain a binary output.
Comparator and the binarized output obtained from the comparator
The rising and falling edges of the mark length
An edge detection circuit for extracting the detected edge signal ;
A playback clock from the edge signal, and
The rising edge and falling edge of the edge signal
Pump-up signal and pump-down signal
A PLL circuit for extracting the signal and the binarized output and the port.
Rise from the pump-up signal and the pump-down signal
The first voltage that is proportional to the average
Rising timing averaging circuit, and the binarization
Output, the pump-up signal, and the pump-down signal.
The proportional to the average value of the rising under standing edge timing from
Fall timing averaging circuit for extracting the second voltage
And the first voltage and the second voltage or the first voltage
The difference voltage proportional to the difference between the voltage and the second voltage is calculated.
Selector, and the first voltage and the second voltage.
Alternatively, the difference voltage between the first voltage and the second voltage is converted to an analog voltage.
Means for converting and said rising and falling edges
The fluctuation amount of the timing from the normal value is within the allowable range
Means for determining whether or not the amount of variation is allowable
When it is within the range, the above AD
Generate slice level control voltage by converted voltage
Means that the amount of variation by the determination is outside the allowable range.
Perform the limiter operation and perform the
The slice level control voltage of the read signal pulse
Means for converting the slice level control voltage into a digital signal and inputting it.
Hand that feeds back to the force side as the slice level
And a step. In addition,
The frequency band of the feedback loop is
Configuration so that it is set to half or less of the frequency band
Can be.

[0011]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention.
A signal reproduced from the magneto-optical disk is applied to an input 8 of a comparator 10 through a preamplifier , an LPF for noise removal, an AGC circuit, and a waveform equalizing circuit , which are not shown. The other input 9 of the comparator 10
May input output or a fixed level of the center value detection circuit of peak rectification system as describes already reference to FIG. 16 in addition to the feedback input to be described later. The rising edge and the falling edge of the signal binarized by the comparator 10 are detected by an edge detection circuit 11 using a differentiating circuit. This edge signal is input to the phase comparator 13 of the PLL circuit 12 for clock recovery composed of the phase comparator 13, the charge pump 14, and the VCO 15, and the phase difference with the recovered clock is detected. This phase difference output is the pump up signal (b) and the pump down signal (c) shown in FIG. Using the pump-up signal (b) and the pump-down signal (c) and the above-described binarized signal, the leading edge timing averaging circuit 16 and the falling edge timing averaging circuit 17 advance the respective edges with respect to the reference. Alternatively, a delay amount is detected.

FIG. 2 shows an example of the edge averaging circuits 16 and 17 , and FIG. 3 shows an example of the waveform of each part. Phase comparator 13
The pump-up signal (b) and the pump-down signal (c) are selected by a rising edge (or falling edge) gate signal (a) generated from a comparator output signal obtained by binarizing an input signal. And
Further, the gate of the reproduction signal period is applied by the reproduction signal gate signal (d). The signals subjected to these gate processes are averaged by the diodes, resistors, and capacitors shown in the figure, and an averaged output (i) is obtained.

Further, a rising edge timing averaging circuit 16 and a falling edge timing averaging circuit 17
Each output A of the voltage difference (A-B) of B is generated by the difference signal generating circuit 22, so that this voltage does not exceed a value between upper and lower limits, a limiter circuit 24 and the frequency characteristics The signal is fed back to the input terminal 9 of the first stage comparator 10 through the slice level control voltage generation circuit 23 including the compensation circuit 25 for compensating.

In the present invention, the timing of the rising edge and the timing of the falling edge of the comparator output are individually controlled by the edge averaging circuits 16 and 17, respectively . Therefore, the frequency band of the feedback loop is the frequency band of the PLL. Is used in a band equal to or less than 1/2 of. If the band is wider than this, a malfunction may occur. Usually, the frequency band of the PLL is selected to be about 1/100 of the bit frequency. Therefore, the frequency band of the feedback loop in the present invention is selected to be 1/200 to 1/2000 of the bit frequency for the above-described reason.

FIGS. 4 and 5 show waveforms of respective parts for explaining the slice level in the present invention. FIG. 4 shows a waveform when the mark length on the recording medium is shorter than a normal value because the power of the laser light is small, and FIG. 5 shows a waveform when the mark length is long because the power of the laser light is large. In the drawing, a waveform shown by a dotted line is a waveform when the mark length is normal. In both figures,
(J) is the input of the comparator 10 , SL is the slice level, (k) is the output of the comparator 10 , (a-1) is the output of the edge detection circuit 11, and (a-2) is the waveform of (a-1). In this embodiment, the circuit is delayed by a period of a half cycle of the VCO clock shown in FIG. (B) is a pump up signal, and (c) is a pump down signal. (B-1), (c-1),
(A) shows the pump-up signal, the pump-down signal, and the output of the averaging circuit for the rising edge, respectively. (B-2), (c-2), and (B) show the pump-up signal, the pump-down signal, and the output of the averaging circuit for the falling edge, respectively. (AB) shows a difference signal between the (A) signal and the (B) signal. 4 and 5
It can be seen that the signal (AB) is different between positive and negative. The (A-B) signal is subjected to compensation such as frequency characteristics, and is fed back to the input terminal 9 of the comparator 10 as a slice level control voltage.

FIG. 6 illustrates the improvement of the edge shift by correcting the slice level, and illustrates the case where the mark length is short. (J-1), (k-
1), (a-3), for the case the slice level SL ₁ is the center value, the input of the comparator 10, respectively,
3 shows the output of the comparator 10 and the output of the edge detection circuit 11 . The waveform shown by the dotted line is when the mark length is normal.
(J-2), (k-2), and (a-4) show the case where the slice level is improved, and the comparator 1
0 input, output of comparator 10 , edge detection circuit 1
1 shows the output. The slice level SL ₁ is the case of the center value, while SL ₂ is the corrected slice level. By lowering the slice level from SL ₁ to SL _2, it can be seen that the output of the comparator 10 is returned to the normal timing.

FIG. 7 shows the non-linearity of the slice level and edge timing change. (J),
(K), (a-1)... (V) show the same waveforms as shown in FIGS. When than the normal slice level SL is lowered to the slice level, a limit point of state slice level SL is SL ₁ is normally detected. Further lowering the slice level from this state, when the slice level SL of the state of the SL _2, the phase will be inverted for the VCO clock. In FIG. 7, this condition is illustrated by the pump up and pump down signals. This is obviously not a correct state, and the above-described limiter circuit 23 is used to avoid this.

FIG. 9 explains that an error occurs when reproduction is performed without correcting the slice level SL according to the present invention when the recording power is small and the mark length is short, in comparison with FIG. FIG. (J-1), (k-
Waveforms such as 1), (a-5), and (v) are the same as those in FIGS. (P) is code data obtained by the (1,7) RLL modulation, and (q-1) shows a demodulated output when recording and reproduction are normally performed. (P) and (q-1) are exactly the same. (Q-2) shows the demodulation output for recording mark length which has not been performed is short despite the slice level correction than normal value, the network to the demodulation output (q-2)
This indicates a state in which an error has occurred, as indicated by shading.

FIG. 10 is a block diagram of a second embodiment of the present invention, and shows a case where the control in the first embodiment is performed by software. The difference voltage between the output voltage of the rising edge timing averaging circuit 16 and the output voltage of the falling edge timing averaging circuit 17 is taken into the software-controlled controller 27 via the A / D converter 26. Is calculated, and D / A
The signal is output from the converter 28 as a slice level control voltage, and the first stage comparator 1 is output in the same manner as in the first embodiment.
0 is fed back to the input terminal 9.

In FIG. 11, the outputs of the timing averaging circuits 16 and 17 at each edge are switched by a selector 29 and taken into a controller 27.

FIG. 12 is a block diagram showing a third embodiment of the present invention. Since the configuration shown in FIG. 1 and the configuration shown in FIG. 10 are combined, the control by hardware and software can be switched by the selector 29 as appropriate. 1 and FIG.
Needless to say, the above configuration may be combined.

FIG. 13 is a flowchart showing a control procedure by the controller 27 shown in FIG. It is determined whether or not the reproduced signal is from the signal recording area other than the gap area. If the reproduced signal is from the signal recording area, the average value of the rising edge timing and the average value of the falling edge timing of the reproduced signal waveform are calculated. A / D converter 2
6 to the controller 27. The controller 27 calculates a difference between the two average values, and if the amplitude of the difference voltage is within an allowable range, calculates a slice level control voltage according to the value. The slice level control voltage is applied so that the difference between the average value of the rising edge timing and the average value of the falling edge timing becomes small. The detected amount of timing shift is output as a positive or negative voltage with respect to the advance or delay of the phase. Therefore, the correction is performed in both the positive and negative directions accordingly.

When the voltage value of the difference calculation output when the average value of the rising edge timing and the average value of the falling edge timing are input exceeds the allowable range,
A limiter operation is performed to correct the slice level with a predetermined fixed value.

Regardless of whether the difference voltage value does not exceed the allowable range or not, the slice level is corrected by applying a control voltage corresponding to the correction amount obtained by the controller 27 to the comparator 10 via the D / A converter 28. Is performed by feeding back to the input terminal 9.

By performing the above-described operations from the measurement of the amount of shift in the edge timing to the correction of the slice level at regular intervals in the signal recording area other than the gap area, a dynamic response to the edge shift can be achieved. can do.

[0026]

As described in detail above, in controlling the slice level of the reproduction signal pulse from the optical disk, the conventional method is open-loop control,
In the method according to the present invention, since a final edge shift amount is detected and corrected by a feedback loop including a VCO, more accurate correction is performed. Therefore, it is possible to prevent a data error from occurring due to a change in the duty ratio of the reproduction pulse.

In addition, since this method operates on the entire region including the preamble, it has a sufficient correction effect on the reproduced signal subjected to waveform equalization, and the correction frequency band can be arbitrarily selected. Broadband is easy. further,
In the preamble area at the head of the sector, sag occurs due to DC cut by a capacitor in the reproducing circuit, etc., and the heat value of the laser fluctuates during recording, and the recording power and wavelength may fluctuate in the middle of the sector. Even when the DC component does not coincide with the entire area of the sector, no error occurs in the correction voltage, and accurate correction control can be performed.

As described above, only by applying the present invention, the pit / edge recording method of the optical disk can be put to practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an edge detection circuit used in the present invention.

FIG. 3 is an operation waveform diagram of each part of the edge detection circuit.

FIG. 4 is a time chart for explaining operation relating to a slice level in the present invention.

FIG. 5 is a time chart for explaining operation relating to a slice level in the present invention.

FIG. 6 is a time chart for explaining improvement of an edge shift by correcting a slice level in the present invention.

FIG. 7 is a time chart for explaining the non-linearity of a change in slice level and edge timing in the present invention.

FIG. 8 is a time chart for explaining a normal operation according to the present invention.

FIG. 9 is a time chart for explaining an error operation when the correction according to the present invention is not performed.

FIG. 10 is a block diagram showing a second embodiment of the present invention.

FIG. 11 is a block diagram showing a modification of the embodiment of FIG.

FIG. 12 is a block diagram showing a third embodiment of the present invention.

FIG. 13 is an operation flow of a controller used in the embodiment of FIG. 11;

FIG. 14 is a time chart for explaining a pit / edge recording system which is a premise of the present invention.

FIG. 15 is a diagram illustrating an example of an eye pattern when a (1, 7) RLL modulation code is recorded on a pit edge.

FIG. 16 is a circuit diagram showing a conventional data slice level circuit for automatically correcting a slice level.

[Description of Signs] 1, 2 input terminals 3 amplifier 5 center value detection circuit 6 sample and hold circuit 7 comparator 8, 9 input of comparator 10 comparator 11 edge detection circuit 12 PLL circuit for clock recovery 13 phase comparator 14 charge pump 15 VCO 16 rising edge timing averaging circuit 17 falling edge timing averaging circuit 22 difference signal generation circuit 23 slice level control voltage generation circuit 24 limiter circuit 25 compensation circuit 26 A / D converter 27 controller 28 D / A converter 29 selector

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-152512 (JP, A) JP-A-2-81368 (JP, A) JP-A-4-61028 (JP, A) Ken Yanagisawa, PLL (Phase Locked Loop) Application Circuit ", 6th edition, Sogo Denshi Publisher, February 1987, p. 37-76 (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B ^7/ 00-7/005 G11B 20/10 G11B 20/14

Claims (3)

(57) [Claims] An optical disk reproduction signal is defined as a slice level.
A comparator for obtaining a binarized output by comparison, and setting a mark length of the binarized output obtained from the comparator.
Edge that detected rising edge and falling edge
An edge detection circuit for extracting a signal; and a reproduction clock for reproducing a reproduction clock from the edge signal.
And the rising edge and the falling edge of the edge signal.
Pump down signal and pump down signal
A PLL circuit for extracting the output signal, the binarized output, the pump-up signal, and the pump
Signal and the average value of the rising edge timing
Rise timing flat to take out the proportional first voltage
Averaging circuit, the binarized output, the pump-up signal, and the pump
To the average value of the falling edge timing
Fall timing flat to extract proportional second voltage
And disproportionation circuit, a difference that is proportional to a difference between said first voltage and said second voltage
A difference signal generating circuit for extracting a divided voltage, and limiting the difference voltage to a range of change between an upper limit and a lower limit.
Control voltage obtained by compensating the frequency characteristic of the differential voltage
And the comparator sets the slice level.
Level control voltage generation circuit for feedback
Optical disk reproduction signal pulse automatic correction device provided with and. 2. The method according to claim 1, wherein the reproduction signal of the optical disk has a slice level.
A comparator for obtaining a binarized output by comparison, and setting a mark length of the binarized output obtained from the comparator.
Edge that detected rising edge and falling edge
An edge detection circuit for extracting a signal; and a reproduction clock for reproducing a reproduction clock from the edge signal.
And the rising edge and the falling edge of the edge signal.
Pump-up signal and the port Npudau which detects the phase difference between di
A PLL circuit for extracting the output signal, the binarized output, the pump-up signal, and the pump
Signal and the average value of the rising edge timing
Rise timing flat to take out the proportional first voltage
Averaging circuit, the binarized output, the pump-up signal, and the pump
To the average value of the falling edge timing
Fall timing flat to extract proportional second voltage
Averaging circuit, the first voltage and the second voltage or the first voltage
The difference voltage proportional to the difference between
Selector, the first voltage and the second voltage or the first voltage
Means for AD-converting the difference voltage from the second voltage, means for determining whether or not the amount of change from the normal value of the timing of the rising and falling edges is within an allowable range; and when fluctuation amount is within the permissible range, means for generating a slice level control voltage by the AD converted voltage of the in accordance with the detected amount of displacement limiter when fluctuation amount by the determination is out of the allowable range means for generating a slice level control voltage of said reproduced signal pulse by predetermined voltage value by performing an operation, the input side of said slice level control voltage by the DA conversion
An optical disk reproduction signal pulse automatic correction device comprising: means for feeding back a slice level . 3. The frequency band of the feedback loop.
The frequency range is not more than 1/2 of the frequency band of the PLL circuit.
3. The optical disk reproduction device according to claim 1, wherein
Raw signal pulse automatic correction device.