JP3030951B2 - Semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout of a semiconductor integrated device for an oscillator.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit for an oscillator, an analog area typified by an oscillating section and a digital area typified by a frequency dividing section are mixed, and the respective areas are either (1) not separated at all or (2) separated. However, the power supply system used the same wiring system. FIG. 5 shows an example of a layout of a conventional oscillator IC. Reference numeral 501 denotes an oscillation unit, 502 denotes an output buffer unit, 503 denotes a digital unit, 504 denotes VDD, and 505 denotes a VSS pad. Reference numeral 506 denotes a power supply line (VDD line) wired from the VDD pad, and 507 denotes a power supply line (VSS line) wired from the VSS pad.
Here, the oscillation section 501, the output buffer 502, and the digital section have the same VDD and VSS lines. An output buffer is arranged next to the oscillating unit.

[0003]

However, in such a layout, since the power supply line of the oscillating section and the output buffer is common, the oscillating section is dropped due to the instantaneous large current (short current) flowing through the output buffer. Drop the power supply. For this reason, the oscillation unit causes feedback oscillation, abnormal oscillation, and the like, which are not essential oscillations. Abnormal oscillations and the like due to such a layout cannot be easily countermeasured, so that a significant delay may occur in the delivery date of development, or the required specifications may not be finally satisfied. It is an object of the present invention to eliminate such disadvantages and to provide an oscillator with stable performance.

[0004]

According to the present invention, there is provided a semiconductor integrated device for a crystal oscillator having an oscillation section, a logic section, and an output buffer section, wherein the oscillation section and the output buffer section are composed of the logic section. A well which is separately disposed and has a conductivity opposite to that of the substrate of the oscillating unit is arranged on the logic unit and the output buffer unit side.

[0005]

[0006]

[0007]

FIG. 1 shows an embodiment of the present invention. This is an example of the layout of the oscillator IC. 99 and 100 are power supply pads (VDD), and 101 and 102 are the other power supply pads (VSS). Reference numerals 103 to 110 denote input / output pads, each of which has an electrostatic protection diode.
Here, reference numeral 103 denotes a pad for connecting a crystal oscillator, a gate pad, and reference numeral 104 denotes a drain pad. Reference numeral 111 denotes an oscillator, 112 denotes a frequency divider, and 113 denotes an output buffer. Reference numeral 114 denotes a VDD line wired from 99 power supply pads, and 115 denotes a VDD line wired from 100 power supply pads. Although the VDD line 114 and the VDD line 115 have the same potential, they are completely separated from each other in a pattern and form separate wiring lines. 116 and 117 are the same, and 116 is the VS wired from the power supply pad of 101.
The S line 117 is a VSS line wired from the power supply pad 102, and the 116 and 117 are completely different wirings. Reference numeral 118 denotes a well of the oscillation section, and the well of the oscillation section is arranged on the output buffer side. FIG. 2 shows an example of bonding to a package when the power supply pads are separated in this manner. Here, 99 and 100 correspond to the power supply pad of FIG. 201 denotes an IC chip, 205 denotes a lead frame, 202, 203 and 204 denote lead terminals, and especially 202 denotes a VDD power supply. 206 and 207 are bonding wires. Voltage fluctuations caused by a short-circuit current or the like in an output buffer or the like are caused by the bonding wire 207.
Through 206 to affect the oscillation section. Here, since the impedance from the lead terminal of 202 to the power supply outside the IC is considerably smaller than the impedance including the inductance of the bonding wire 206, the voltage fluctuation from the output buffer is absorbed by the external power supply and greatly affects the oscillation section. Absent. As described above, even in the power supply line having the same potential, the oscillation section and the digital section (frequency divider + output buffer section) use completely different wiring lines, so that the oscillation due to the voltage fluctuation caused by the short-circuit current in the output buffer section and the like. It is possible to prevent adverse effects on the parts.

Another embodiment of the present invention is shown in FIG. 301
Oscillating units 302 to 305 are digital units, and 306 is an output buffer. Numerals 307 to 312 denote P wells, which are N substrate ICs. In the case of a P substrate IC, an N well is used. Although the power supply line and pad arrangement are not particularly shown, it is assumed that the layout is based on the same concept as in FIG. This embodiment may be affected by power fluctuations through the substrate even if the power is completely isolated. For this reason, an output buffer, which is a cause of a large power supply fluctuation, is located as far as possible from the oscillation section inside the IC, and another digital section which does not cause much voltage fluctuation is interposed between the oscillation section and the output buffer section.
Also in the oscillating unit, wells having a potential opposite to that of the substrate are arranged on the output buffer side and the digital unit side to increase impedance against voltage fluctuation. FIG. 4 shows a cross-sectional view of a portion where the oscillating section and the digital section approach each other, which will be further described. 40
Reference numeral 1 denotes a substrate, which is an N substrate here. Reference numeral 402 denotes a P-well of the digital unit, and 403 denotes a P-well of the oscillation unit. 404
405 is a sub-contact on the N-substrate side of the oscillation section, 406
407 is a substrate sub-contact in the digital section. 408
409 is a well sub-contact of the oscillating unit, and 410 and 41
Reference numeral 1 denotes a well sub-contact of the digital section. 412
Numerals 419 are the respective diffusions constituting the transistor. Inverters 420 and 421 each comprise PN transistors of the digital section. 422 and 423 constitute an oscillation inverter. Reference numerals 424 to 427 represent the substrate resistance equivalently, and indicate visually that the impedance from the viewpoint of 404 becomes higher as going from the sub-contact 407 to the sub-contact 404. Here, when a short-circuit current flows from the inverter in the digital section, B flows from A to 420 through the transistor.
, And VDD and VSS are short-circuited through the transistor 421. Focusing on the VDD side, the short-circuit current flows through the substrate via the VDD line and the sub-contacts of 407 and 406. This causes the potential of the substrate to fluctuate in a decreasing direction. The effect of this change is
Attenuates as it passes through 426 and 427. Or 40
If there are many sub-contacts similar to the sub-contacts 6 and 407 around the sub-contacts 406 and 407, there is a possibility that the sub-contacts having low impedance are absorbed by the sub-contacts having low impedance and the influence on the direction of the oscillating section having high impedance is hardly obtained. Also, the digital section itself is a low-impedance voltage fluctuation absorption path for the output buffer. From such a concept, it is natural that the vicinity of the sub-contacts 405 and 404 is less susceptible to the voltage fluctuation than between the resistors 425 and 426.

[0009]

By using the above-described layout, a very sensitive portion such as an oscillating portion is not particularly affected by a portion such as an output buffer which causes a large current to flow and fluctuates the power supply. In an unstable state such as when oscillation starts, feedback oscillation or abnormal oscillation is likely to occur under the influence of power supply fluctuation. However, since the layout of the present invention shuts out the effect of the fluctuation of the power supply voltage on the oscillation section,
Even at the time of oscillation start, stable oscillation can be started. Therefore, it is possible to provide an oscillator having very strong and stable performance against feedback oscillation and abnormal oscillation.
Further, by using such a layout in the IC, it is possible to make it harder for the characteristics of the crystal to be affected by feedback from the IC, and therefore, there is a wide range of variations in the characteristics of the crystal itself. Therefore, the yield as the total oscillator can be improved and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a layout diagram of an embodiment of the present invention.

FIG. 2 is a bonding diagram of an example of the present invention.

FIG. 3 is a layout diagram of a second embodiment of the present invention.

FIG. 4 is a structural sectional view.

FIG. 5 is a conventional layout diagram.

[Explanation of symbols]

99 · 100 Power supply pad (VDD) 101 · 102 Power supply pad (VSS) 103 · 104 · 105 · 106 · 107 · 108 · 1
09/110 Input / output pad 111 Oscillator 112 Digital section 113 Output buffer 114/115 Power supply wiring (VDD) 116/117 Power supply wiring (VSS) 118 P-well

Claims (1)

(57) [Claims] 1. A crystal integrated semiconductor device for a crystal oscillator comprising an oscillating unit, a logic unit, and an output buffer unit, wherein the oscillating unit and the output buffer unit are separated from each other by the logic unit. A semiconductor integrated device, wherein a well having conductivity opposite to that of the substrate of the unit is arranged on the side of the logic unit and the output buffer unit.