JP3029445B2 - Startup reception device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a start reception method for reporting a start reception state in response to a drive request from a CPU via a bus, a start that enables continuous startup for a plurality of CPUs and IOs and has a small amount of hardware The purpose is to provide a reception system, connected to multiple CPUs and common storage devices by a bus,
In a data channel device that performs a data transfer operation between an MM or a CM and an IO device in the CPU, in response to channel command information having a start request instruction for the data channel device from the CPU, a start reception status report is issued. The data channel device stores the condition code information according to an arbitrary address set in the channel command information.

[Industrial applications]

The present invention relates to a data channel device, and more particularly, to a boot acceptance system for reporting a boot acceptance state in response to a drive request from a CPU via a bus.

[Conventional technology]

In computer systems, MM (main storage)
And a data channel device (DCH) for controlling data transfer between a CM (common storage device) and an IO device. For example, the data channel device is generally activated by a DCH instruction such as an SIO instruction, which is a conventional method.

According to this method, in response to a start instruction to the DCH, a start reception status report is made by directly storing a CDC (condition code) from the DCH in an internal register of the CPU, and the instruction is reported and completed. Therefore, even if SIO instructions are continuously executed, processing can be performed without contradiction.

On the other hand, in recent years, many microprocessors do not have a DCH instruction, and a normal data transfer instruction (store instruction: S
A DCH activation method based on an IO map using a T instruction) is employed. Even in such a system, the same activation acceptance state by CDC is indispensable, and by referring to the control register information on the DCH side or the CDC storage area provided on the system control register on the CPU side, its normality is checked. In many cases, a startup process is performed in accordance with the procedure of checking

FIG. 5 is a flowchart (1) of a conventional DCH activation process. When the CPU activates the DCH, first, an activation order is written to the control register (ODR) by the ST instruction for the DCH (S1). Control register O in DCH of this start order
When the writing of the DR is performed, the DCH sets the determination result of the activation acceptance state in the control register (CDR). During this time, the CPU reads the CDR in the DCH by a load instruction or the like and scans the state (S2). That is, the CPU determines the contents of the CDC a plurality of times after placing the activation order, and can obtain the determination of the reception state by the CDC after the DCH stores the determination result of the activation reception state.

On the other hand, the DCH reads the CCW on the MM after setting the above-described determination result of the activation acceptance state. DC after reading this CCW
H controls, for example, a data transfer operation between the IOC and the MM. After completing the transfer operation (S4), the result is stored in the control register TSR.
To be stored. Then, an end interruption report is sent to the activation source CPU (S5).

During the operation of the DCH described above, when the CDC becomes valid, the CPU has completed the activation process on the CPU side, and then waits for an end interrupt report from the DCH, receives an interrupt by the interrupt report (S5), Read the TSR and check the result.
By the series of operations described above, DCH for instructions such as ST instruction
Further, all processing of the CPU is terminated.

The above operation is a method in which the CPU and the DCH directly access the registers in the CPU and the DCH. On the other hand, the DCH writes CDC directly to the CPU register and writes the register in that CPU to the CPU.
, The transfer operation described above can be performed similarly.

FIG. 6 is a flowchart (2) of a conventional DCH activation process. When the CPU writes a start command to DCH # 0, DCH
# 0 sets the determination result of the start acceptance state in the control register CDR. During this time, the CPU sequentially reads the registers REG in the CPU and determines whether or not CDC has been received. When DCH # 0 sets the determination result of the activation acceptance state to the control register CDR (returns CDC), the CPU confirms the CDC reception by reading the register REG in the CPU, and then reads the CCW to transfer DCH # 0. Perform the operation.

On the other hand, when the CPU activates DCH # i,
, And sequentially reads the register REG in the CPU to receive the CDC. At this time, of course, the CD from DCH # i
When C return is added to the register and stored, CDC is received. In the above-described operation, activation of DCH # 0 and DCH # i cannot be performed at the same time. After the CDC is returned from DCH # 0, an activation command is transmitted to DCH # i.

[Problems to be solved by the invention]

To summarize the conventional method described above, if a control register for storing CDC is provided in the DCH,
Considering the optimal conditions for starting DCH from multiple CPUs, it is necessary to provide the number of CDC storage registers for each CPU. In other words, a condition that depends on the system is considered for the number of CPUs, and the amount of hardware required for the control register increases.

When the CDC storage control register is provided in the CPU,
You have to consider activation for multiple DCHs. That is, assuming that the number of CDC storage control registers is one, first, after the CPU activates one DCH, the CPU must wait for the activation of the next DCH until the CDC returns between the DCHs. No. To solve this problem, the number of CDC storage registers must be increased for DCH.
In this case as well, the result depends on the system such as the number of DCHs, and results are taken into consideration, and the amount of hardware required for the control register also increases.

On the other hand, in response to a request from the software, the CDC content also reports two judgments, such as the multiplex reception status of the DCH activation order, the IO activation status, and the abnormality detection during the execution of the channel program in the DCH, in addition to simply reporting the acceptability of the activation reception It is hoped that the accompanying content will be reported by CDC. This is for the purpose of early detection of an abnormality in software and facilitation of narrowing down the location where the abnormality occurs.

Under such circumstances, in the conventional method, if the number of control registers for storing CDC is limited, the CD
Since the control register for C storage is used, there is a problem that only a reception state can be reported as a report by the CDC. Also, assuming continuous startup from multiple CPUs, the CDC cannot be displayed for the CPU, so each CD
C The order of reporting cannot be compensated. Further, as described above, the number of register surfaces must be increased in accordance with the number of activation source CPUs / non-activation IOs, and there is a problem that the amount of hardware increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an activation accepting method that enables continuous activation of a plurality of CPUs and IOs and that requires a small amount of hardware.

[Means and Actions for Solving the Problems]

The present invention relates to a data channel device that is connected to a plurality of CPUs and a common storage device by a bus, and that performs data transfer between an MM or CM in the CPU and an IO device.

Channel command information (CCW) having a start request instruction from the CPU has an address where condition code information (CDC) in the data channel device DCH is to be stored. This CCW is transferred from the CPU to the data channel device DC.
H, and when the data channel device DCH reports a start acceptance state in response to the start request instruction of the channel command information, the condition code information CDC is stored at the designated address in the channel command information. That is, although the channel command is issued from the CPU, even if the channel command is separately sent to a plurality of data channel devices, the condition code information CDC from the data channel device DCH is added to the specified different addresses. .

The CPU can determine the contents (condition code information) of the specified address after accessing the plurality of data channel devices DCH, thereby speeding up the processing, reducing the number of software determination processes, and further reducing the amount of hardware. Can also be reduced.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flowchart (1) of a DCH activation process according to an embodiment of the present invention. When the CPU starts up by, for example, an ST instruction, a start command is written to a target DCH (S1).
0). That is, a command is written to the control register (ODR) in the DCH by the ST instruction. By this writing, DCH becomes MM
Read the CCW above. Then, the determination result such as the activation acceptance state is written to the MM as CDC (S11). After the CPU is activated by the ST instruction, the CPU reads from the MM whether or not the designated information in the MM is stored as CDC and determines. That is, the CDC on the MM is read by the load instruction to scan the state. This scan is executed before the writing of the CDC from the DCH is performed, and it is assumed that the CDC is received for the first time by being written, and the reception state is determined. If the read CDC is valid, the activation process from the CPU is completed, and the system waits for a termination interrupt from the DCH. DCH is CDC
Is written into the MM (S12), and then the transfer operation (S13) is started. After the end of the transfer operation, the result is stored in the control register TS.
Store in R. In addition, an end interrupt is reported to the starting CPU (S1
4) is output. When the CPU receives this end interrupt report, it accepts the interrupt and reads the TSR in the DCH to confirm the result.

FIG. 2 is a configuration diagram of a control command for activation, and FIG. 3 is a configuration diagram of a CCW. In the start-up control command described above, the sending device ID (DCH number), the internal address (ODR address), and the order type (ex, SIO) as the address ADR for the DCH are DA.
Has a command address (CMA). The DCH reads the CCW from the command address in the start-up control command and executes the command processing. In the command stored in the command address, CCW0 is a command code, IOA (activated IO), the number of transfer bytes, CCW1 is DA (data address), and CCW2 is CDA (CDC storage address).
The CDA (CDC) stored in CCW2 in this CCW configuration diagram
DCH stores the CDC at the designated address.

Conventionally, since the CDC storage address is not specified, the CPU has to perform, for example, a process of sequentially reading registers in the DCH.However, according to the present invention, since the CDA specifies the CDC storage address by the CDA, the CPU Is from the address indicated by the indicated CDA (CDC storage address)
CDC content can be determined.

FIG. 4 is a flowchart (2) of the DCH activation process according to the embodiment of the present invention. In the embodiment of FIG.
Although one DCH is activated from U, in the embodiment of the present invention shown in FIG. 4, two DCHs (DCH # 0, DCH # i) are activated. When starting two DCHs, the CPU is, for example, DC
H # 0 is first activated (S21), the CDC of DCH # 0 is immediately read (S22), and DCH # i is subsequently activated (S23). Then, similarly, the CDC of DCH # 0 / i is read. That is, time T
Running the DCH # i at time T ₂ to start the DCH # 0 in _1. Conventionally, two cannot be accessed at the same time, but the CDC storage addresses of the respective DCH # 0 and DCH #i are separately indicated in the CCW2 and are written into each. it can.

After activating DCH # i, the CDC of DCH # 0 / i is read (S24). This is read because the DCH # 0 and DCH # i are simultaneously activated, and during this time, the DCH # 0 and DCH # 1 each execute a reception process corresponding to the requested command. Then, for example, when DCH # 0 returns the CDC to the memory (S25),
In the CDC reading process S26 of DCH # 0 / i,
It confirms that DCH # 0 has returned the CDC and receives it. Thus, for example, it is determined that CDH # 0 has been accepted. At this time, DCH # i is still executing the processing of the request for the start command. Subsequently, the CPU sequentially reads the CDC of DCH # i (S27, S28).

DCH # i finishes processing, returns CDC, and stores CDC in memory MEM.
Is stored, the process of sequentially reading the CDC of DCH #i is to read the CDC of DCH #i after the CDC is stored, whereby the CDC of DCH #i can be received.

As described above, conventionally, activation to the DCHs that must be sequentially performed can be performed continuously, and after the activation, a determination as to whether an activation request has been received for each DCH is returned. Can be obtained by the ordered CDC, and only the request can be sent without starting the DCH, etc.), and then the request can be accepted. Can be shorter.

〔The invention's effect〕

As described above, the present invention has the following effects.

The CDC storage area can be set individually for each boot process, and there is no need to worry about rewriting the CDC.

Assuming continuous activation from multiple CPUs, the CDC can be displayed for each CPU, so that the order of CDC reporting can be compensated.

The CDC storage area can be set at any address, which makes it easy to increase the flexibility of the system.

For CDC contents, in addition to mere reporting of acceptability at the time of activation acceptance, it can include multiple acceptance status of DCH activation order, IO activation status, abnormality detection during execution of channel program in DCH, etc. We can provide useful information.

[Brief description of the drawings]

FIG. 1 is a flowchart (1) of a DCH activation process according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a control command for activation, FIG. 3 is a diagram of a CCW configuration, and FIG. Flowchart (2), FIG. 5 is a conventional DCH activation processing flowchart (1), and FIG. 6 is a conventional DCH activation processing flowchart (2). DCH: Data channel device, CDC: Condition code information, CCW: Channel command information.

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Noritaka Takatoku 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yoshiaki Wakimura 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Stock Corporation Inside the company (72) Inventor Tadayoshi Komachiya 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Hisao Taguchi 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Totsuka Plant (72) Inventor Daigo Kobayashi 216 Totsuka-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Inside the Totsuka Plant of Hitachi, Ltd. (56) References JP-A-58-56130 (JP, A) (58) Fields surveyed (Int .Cl. ⁷ , DB name) G06F 13/12

Claims (2)

(57) [Claims] 1. A data channel device connected to a plurality of CPUs and storage devices via a bus and performing a data transfer operation between the storage device and an IO device, wherein the CPU issues a start request instruction to the data channel device. In the channel command information having, set an arbitrary address to store the condition code information indicating the activation reception state in the data channel device, the data channel device sets the condition according to the set address. A data channel activation receiving device for storing code information; 2. A data channel activation receiving method which is connected to a plurality of CPUs and storage devices via a bus and performs a data transfer operation between the storage device and an IO device, wherein the activation request from the CPU to the data channel device is provided. Setting, in channel command information having an instruction, an arbitrary address at which condition code information indicating a start acceptance state in the data channel device is to be stored; and, according to the set arbitrary address, the condition code Storing the information.