JP3026341B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a high speed and low power consumption multi-bit static RAM.

[Prior Art] A first conventional example of a semiconductor memory device will be described with reference to FIG. In general, data in a memory cell 18 of the memory array 10 is supplied to an X-direction word line by an X-decoder (and word driver) 14 comprising an X-decoder and a word driver.
16 is selected, and a bit line pair (data, data bar) 24 in the Y direction is connected to a Y decoder or a Y selection switch 22.
And the data of the memory cell 18 is
And output from the sense amplifier 6.

When the capacity is increased with this conventional configuration, (1) the word line 16
And that the DC current flows from the load MOS transistor 26 through the memory cell when the word line is activated, (2) the word line delay increases and the speed decreases, (3) Further, in order to solve this problem, if the word line 16 is shortened, the number of memory cells in the Y direction, that is, the bit line direction increases, so that the bit line capacity increases and the access time becomes slow. .

A second conventional example as a method for solving the above problem will be described with reference to FIG. In the X decoder 14, the main word line 7
Select Next, the group word line 8 for selecting the memory cell 18 is selected via the divided word logic 11. Further, data is transmitted to the common data line 30 via the bit line pair 24. In this configuration, the number of memory cells selected can be reduced by subdividing the word line. As a result, the capacity of the bit line can also be reduced,
Higher speed can be achieved.

On the other hand, the length of the word line can be further reduced by the double word line system. This double word line system is a method in which the actual length of each word line is further effectively divided into two word lines. The method of forming the divided word lines shown in FIG. 3 is disclosed in, for example, US Pat. No. 4,554,646.

[Problem to be Solved by the Invention] The conventional technique shown in FIG. 3 is an effective technique for lowering the power, but the parasitic capacitance and resistance of the common data line, which are particularly important for high speed, are reduced. No consideration has been given to an increase in sense amplifiers and the like due to the division of the word lines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-bit semiconductor memory device that overcomes the above problems and achieves high speed and low power simultaneously.

Means for Solving the Problems In order to achieve the above object, in a semiconductor memory device according to the present invention, a first region having a plurality of memory cells arranged in a matrix and a plurality of memory cells arranged in a matrix are arranged. A memory block including a second area having
A plurality of bit lines for designating a plurality of memory cell columns;
Word lines and bit lines including a plurality of first word lines that specify only the rows of memory cells in the second area and a plurality of second word lines that specify only the rows of memory cells in the second area A y decoder for selecting at least one of the word lines, an x decoder for selecting at least one of the plurality of word lines,
The plurality of first word lines are connected to the x-decoder, the plurality of second word lines are connected to the x-decoder via a connection line different from the first word line, and the connection line has one end. An x-decoder is arranged to cross the first region, and is connected to a second word line at a connection point.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a RAM. In the figure, reference numeral 10 denotes an aggregate of memory cells 18 for storing information, for example, a large memory array of about 10 ¹⁰ . 16 is a word line, 24a to 24b are pairs of bit lines (data, data bar), 26 is a load MOS transistor, and 38 is an output data bus. Reference numeral 22 denotes a Y decoder including a Y-direction switch MOS transistor and the like, and reference numeral 36 denotes a multiplexer. The memory array 10 is divided into eight mats 12a to 12h by four X decoders (word drivers) 14a to 14d. In each case, the X decoder 14 has a Y
Control multiple word lines running in a direction. Each word line provides an activation signal to the memory cell 18 in the X direction. One Y decoder 22a to 22e selects a plurality of bit line pairs 24. Then, the bit line pair 24 is connected to the segment 30 of the common data line.

A plurality of load control circuits 27a to 27p
Bit line pair of one effective mat 28a or 28b selected during one write mode period of MOS transistors 26a to 26p
Connect selectively to 24.

The clock generation circuit 20 controls the X decoder (also a word driver) 14 and the Y decoder 22, and controls the sense amplifiers 32 and 34, the multiplexer 36 and the like through the amplifier drive circuit 40. The load control circuit 27 generates a load switching signal φLA-φLP based on the address signal Ai and the load control signal LC.

To increase the speed of a semiconductor memory device, it is important to reduce the wiring capacity, resistance, and the like of bit lines and common data lines. For example, in the case of a multi-bit configuration in which the number of memory cells is 1 M bits (128 K words × 8 bits), the Y direction, that is, the bit line direction is shortened to 512 bits to reduce the load (parasitic) capacity of the bit line. Further, in the X direction, that is, in the word line direction, the memory cell is arranged in 512 bits × 2048 bits with four X decoders (also serving as word drivers) 14 and eight mats, and the memory cell in the bit line direction to the word line direction is 1: And 4.

Further, each word line is reduced to half the mat in a double word line fashion.

In this way, when considering power and speed, two mats 12
It is divided into two effective mats 28, and the number of bits of each effective mat connected to the 28a and 28b sides is 1024 bits. The first location 16a of the word line 16 accesses one half of the bit's mat. Then, the second word line position 16b accesses the other half. As a result, the number of memory cells connected to an integrated word line is reduced, and power consumption is reduced. Accordingly, the common data line 30
Is an effective mat 28 divided into 8 mats, each leading to 8 mats
a and 28b lead to one segment of the eight common data lines. As a result, by dividing the common data line into eight segments, the capacitance, resistance, and the like of the diffusion layer and the wiring layer of the Y-direction switch MOS transistor of the Y decoder 22 can be reduced, and the speed can be increased.

This common data line is composed of two wires per bit. Therefore, in the case of a multi-bit configuration of 8 bits, 16 lines are arranged, and 8 bits are read or written when reading or writing.
The bit is activated.

On the other hand, 26 load MOS transistors are provided to keep the bit line pair 24 at a predetermined potential and enable a static operation of the memory cell. This load MOS transistor is composed of a plurality of MOS transistors.In particular, when shifting from a write operation to a read operation, a variable impedance load is used to precharge and equalize the potential difference of the bit line at high speed. Is used. This variable impedance load is performed in units of a selected word line. Further, since only the effective mats are selected at the time of writing, the power consumption is low.

Further, it is appropriate to provide a sense amplifier for each common data line in accordance with the division of the common data line 30 for speeding up.
For example, in the case of an 8-bit configuration, the number of sense amplifiers is 1 per memory mat in one common data line segment.
Eight circuits are provided as blocks (input / output terminals I / O1 to 8),
A total of 64 memory mats are arranged with 8 memory mats. As a result, the number of sense amplifiers that are simultaneously activated at the time of reading is reduced to eight circuits to reduce power consumption, and data is transferred to an 8-bit output data bus 38 by the selection of the multi-multiplexer 36. Each of the sense amplifiers is connected via a driving sense amplifier 34 for driving an output data bus 38 which is a second stage sense amplifier.

The multiplexer 36 is connected between a pair of the second-stage sense amplifiers 34 and a pair of output data buses 38. Furthermore,
In response to the read data being activated, the plurality of amplifier drive circuits 40 control the activation operation of the detection and drive sense amplifiers connected to the common data line segment.

FIG. 4 shows a more detailed configuration diagram of the static RAM of FIG. Here, 12 is the memory mat shown in FIG.
Is a 4MOS + 2R type flip-flop type memory cell using a high resistance as a load. This memory cell has two outputs, a high level and a low level. When the flip-flop operates, the high level and the low level outputs are inverted.

The bit line pair 24 is connected to two different terminals of the flip-flop. Each of the bits thus selected includes a high level signal and a low level signal. The state of the high-level signal and the low-level signal of that bit indicates whether digital "1" and "0" have been stored in the memory cell. Reference numeral 26 denotes a load MOS transistor, which includes n-channel MOS transistors 60a, 60b, 62a, and 62b. This 26 is used to stabilize the data of the memory cell at the time of reading,
At the same time, by controlling one of the load MOS transistors 60a and 62a with a clock, power consumption during the write operation period can be reduced, and
High-speed recovery and equilibration of the bit line voltage at the time of shifting to the read operation are performed. The signal φL for controlling the load MOS transistors 60a and 62a is controlled by a write / read signal (▲). In particular, the signal φL corresponding to the subdivision of the word line.
It is preferable for the high-speed operation of the memory that the load MOS transistor be turned off and the other memory cells be turned on at the time of writing only in the bit line of the memory cell of the selected mat 28, that is, the subdivision of the memory cell. This is because the subdivision reduces the wiring capacitance and resistance, increases the speed of the operation of the signal φL, and enables high-speed bit line voltage recovery and balancing.

An X decoder (also a word driver) 14 activates a word line 16 by an address signal Ai and a word line activation signal φWD. Reference numerals 24a and 24b denote bit lines, which indicate wiring for data and data bars, respectively. When the word line 16 is activated (high-level signal), the data in the memory cell is passed through the Y-direction switch MOS transistor 66 of the Y decoder 22. Then, it is transmitted to the divided common data line 30.

Reference numeral 64 denotes a precharge circuit which always sets the potential of the bit line to a constant level during reading to increase the speed of reading inverted data of data "1" and "0".
It is started by

On the other hand, for data, the word line 16 is activated at a high level, so that the output of the memory cell connected to one of all the flip-flop circuits connected to the word line is connected to the bit line. Further, the data of the bit line pair 24 is transferred to the divided common data line 30 by the switch MOS transistor pair 66 of the Y decoder 2. In the case of an 8-bit memory, the memory cell is composed of eight flip-flops, and the high-level signal of the word line is connected to the eight flip-flops together with the bit line pair.

Further, eight of the switch MOS transistor pairs 66 are connected to a bit line pair of eight flip-flops together with the respective wiring pairs of the common data line 30. In this way, all eight flip-flops are read out simultaneously.

Reference numeral 36 denotes a multiplexer for connecting the output of the sense amplifier to an output data bus 38 having a multi-bit configuration. The read signal transmitted to the output data bus 38 is
The signal is transmitted to the output circuit 80 and output from the multi-bit output terminal. As described above, by dividing the common data line into memory mat units, the wiring capacity, resistance, and the like can be reduced and the speed can be increased.

At the time of reading, the high and low level signals of the bit line pair 24a and 24b are applied to the sense amplifiers 32 and 34 by the common data line 30.
Is transmitted to The first stage amplifier, which is the sense amplifier, is formed by a pair of current mirror type amplifiers, and is activated by a sense amplifier activation signal φMRS from the amplifier drive circuit 40. The second stage drive amplifier is:
It is activated by φMRS.

The multiplexer 36 connects the output of the sense amplifier to the output data bus 38, so that the multiplexer control signal φMRO
Activated by Data bus 38 to which the data is output
Has a wiring pair corresponding to each bit. Further, each wiring pair is connected to an output circuit 80 for coupling a high-level signal and a low-level signal from a flip-flop having digital “1” and “0”.

FIG. 5 shows a configuration diagram of the memory mat portion. In the figure, 28 is the memory mat of FIG. 1, 14 is an X decoder (also a word driver), 16 is a word line for selecting a memory cell, 28C
Indicates a near end memory mat, and 28d indicates a far end memory mat. Further, reference numeral 50 denotes a third wiring layer for selecting the far end memory mat, which is connected to the word line 16b for selecting the far end memory mat by a contact 52. Another third wiring layer 50 from the word line is wired from the X decoder 14 to the contact 52, and the second word line 16b is connected by the contact 52. As described above, the X decoder (also a word driver) can select a memory cell of the effective mat 28d at the far end by sending a word signal to the word line 16b through the third wiring layer 50. Also, the word line 1 of the effective mat 28d at the far end
6b is shortened by the third wiring layer 56 and the contact 54 to minimize the word line delay. On the other hand, the third wiring layer 56 can be grounded separately from the third wiring layer 50. In this case, the influence of noise when the wiring is floating can be eliminated.
Further, the memory cells in 28d may have a configuration in which the third wiring layer 56 is removed.

The number of memory cells selected by a word line by the above-mentioned double word line method is reduced by half, for example, 256 bits becomes 128 bits, and low power can be achieved.

Note that the third wiring layer can be used as a ground line of a memory cell, and in this case, it is useful for reducing the area of the memory cell. As a result, the area of the memory chip can be reduced, the wiring capacitance, the resistance, and the like can be reduced, and the speed and power consumption can be further reduced.

FIG. 6 shows each timing at the time of reading in FIG. Thus, the read operation of the present invention will be described.

In the figure, when the input address signal (Ai) changes while the chip select signal (▲ ▼) of the semiconductor memory device is at a low level, an address change detection signal corresponding to the address is generated, and based on this, Basic clock φtota
l is made. Next, based on this φtotal, a precharge signal φC for the bit line, a data latch signal φDL, an activation signal φWD for the X decoder (also a word driver), an activation signal φMRS for the sense amplifier, and an activation signal φMRO for the multiplexer
Are each made. On the other hand, when there is a skew in the address signal or when the address changes, φtotal is generated again, and the precharge signal φC is generated. However, other clocks (φDL, φWD, φMRS, φMRO) and the like are continued as they are, and the timing is designed so that the internal operation is not affected. The response of these signals is the φtotal signal, the clock generation circuit 20 is activated by the internal chip select signal (▲ ▼) low level,
The precharge signal φC applied to the decoder 22 is generated by inversion, and φDL and φWD are generated with a delay from the edge of φtotal. The activation signal φMRS of the sense amplifier and the activation signal φMRO of the multiplexer are generated by delaying the first edge of the address Ai signal change.

The read operation of the memory corresponding to the above timing pulse is as follows.

When the address (Ai) changes, the precharge signal φC
Is precharged by the precharge circuit 64 to which all the bit lines are precharged, the X decoder 14 is activated by φWD, and a small signal of a high level and a low level is read from a predetermined memory cell and transmitted to the sense amplifier 32. You. Further, the sense amplifier activation signal φMRS is activated, and this small signal is amplified twice by a two-stage current mirror type sense amplifier for detection and driving, transmitted at high speed, and output via the multiplexer 36. You. This series of clocks is important for shortening the access time of the SRAM. For example, not only that each clock has an appropriate delay time and width, but also the rising edge of φtotal determines the minimum width of the precharge signal φC for which precharge can be performed reliably. Become. Also, after a certain time from the change of the address, the data latch signal φDL goes low to latch data, and then goes low in the order of φMRS, φMRO, φWD to deactivate the internal circuit. Therefore,
In a cycle in which the read time is long, power consumption is reduced because the internal circuit does not operate except for a fixed time.

As described above, when a plurality of sense amplifiers are selected by an address signal, activated, and their outputs are selected and taken out by a multiplexer, φMRS and φMRO at the beginning and end of the read operation are set to have the relationship shown in FIG. By doing so, data can be transferred reliably.

FIG. 7 shows each timing at the time of writing in FIG. Thus, the write operation of the present invention will be described.

Write / read signal in write cycle (▲ ▼)
Changes from the high level to the low level, the data input activation signal DIG goes high, the word line activation signal φWD of the memory X decoder (also word driver) goes high, and a predetermined word line goes high. Level, and data is transferred to the common data line. Furthermore, Y direction switch MOS
The data is transferred to the bit line via the transistor, and data is written to a predetermined memory cell.

In the write cycle, the detection and drive amplifiers of the sense amplifier, the multiplexer, and peripheral circuits thereof are turned off. Then, the write data is directly taken into the data latch circuit in the output buffer circuit. Therefore, in the same address, when the signal changes from the low level to the high level and shifts to the read state, the data of the latch circuit is read. At the same time, a series of signals DIC and φWD are set to low level. As a result, it is possible to prevent a phenomenon in which the sense amplifier once returns to the active state, which occurs in the conventional circuit, and the unstable operation of only the output can be prevented, and the output signal can always be fixed at a high level and a low level. Further, when shifting from the writing state to the reading state, the load control signal LC in FIG. Therefore, the load MOS transistor of the bit line is turned on by a signal obtained by taking a logic of a predetermined address signal and LC. As a result, the bit line voltage having a large voltage amplitude is quickly balanced with the precharge, and the recovery speed after writing is improved. Furthermore, high-speed operation requires that the LC signal transition at a high speed, and a method of subdividing and controlling signal lines for each selected word line can be said to be an optimal configuration.

FIG. 8 shows an arrangement having the same configuration as the memory mats 28a and 28b shown in FIG. 1, and explains an 8-bit configuration memory. 70 indicates an address signal in the Y direction.

14a to 14d are X decoder (also word driver), 74 is Y
A signal for selecting a direction switch MOS transistor;
Memory cells of I / O1 to 4 and memory cells of I / O5 to 8 are selected by input / output (I / O) terminals. 72 is the logic of the Y decoder circuit, and selects 74.

With this configuration, the memory cell array of I / O1-8 connected to one word line is divided into two (I / O1-4, I / O5-8)
Data output delay between I / O 2-3ns
Can be provided. As a result, the peak current flowing through the output transistor when activated can be divided, and the effect of noise on the internal circuit when activated can be reduced.

FIG. 9 shows a clock generation circuit 20 for various control signals such as φWD, φDL, φC, etc. of FIG. 5, and is constituted by a logic circuit.

In the figure, φtotal is a basic clock generated based on an address change detection signal, DIC is a data input activation signal generated by a write / read signal (▲ ▼), ▲
▼ is a chip internal activation signal generated from the chip select signal (▲ ▼) and activating φWD and φDL.

FIG. 10 shows the amplifier drive circuit 40 shown in FIG. 1, which generates a signal for controlling a sense amplifier such as φMRS, φMRO, etc. and a multiplexer, and is constituted by a logic circuit. In the figure, Ai is an address signal for selecting a sense amplifier. φMWI is an activation signal for the data write circuit of the memory, and the Ai address signal and the write / read signal (▲
The data input activation signal DIC according to ▼) is used. Further, it is configured to generate a sense amplifier activating signal φMRS, a multiplexer activating signal φMRO, and its inverted signal ▼.

The amplifier drive circuit 40 selects and activates each of the first-stage detection sense amplifier and the second-stage drive sense amplifier. Further, since the sense amplifier is activated only in the portion of the read memory cell, the power can be minimized.

The above-described circuits shown in FIGS. 9 and 10 are circuits for effectively driving the divided common data lines, sense amplifiers, and the like according to the subdivided memory mats shown in FIG.

In the above-described embodiment, the description has been made by taking the 8-bit configuration as an example.
Similar high speed and low power can be expected for bits, 32 bits, etc. In addition, the gist of the present invention shows a method of configuring a semiconductor memory device, and does not limit elements, control circuits, and the like that configure the memory.

The influence of controlling or connecting the divided common data lines and sense amplifiers outside the memory mat, such as an increase in the occupied area of the memory chip, can be considered. It is negligible compared to the benefits gained by speeding up and reducing power consumption.

[Effect of the Invention] As described above, according to the present invention, the static
There is an effect that high speed and low power of the RAM can be achieved.

Furthermore, the current increases due to the increase in the bit line capacity and the common data line capacity in the prior art, the access time is delayed,
Further, there is an effect that a reduction in the life due to an increase in the chip temperature due to an increase in the current can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a static RAM according to an embodiment of the present invention,
FIG. 2 is a diagram showing a first conventional example, FIG. 3 is a diagram showing a second conventional example, FIG. 4 is a more detailed configuration diagram of the static RAM of FIG. 1, and FIG. FIG. 6 is a diagram showing a double word line configuration applied to the embodiment, FIG. 6 is a diagram showing each timing at the time of reading in the embodiment of the present invention, and FIG. 7 is a diagram showing each timing at the time of writing in the embodiment of the present invention. FIG. 8, FIG. 8 is a diagram showing the configuration of the memory mat portion of the present invention, FIG. 9 is a diagram showing the configuration of the clock generation circuit of FIG. 1, and FIG.
FIG. 2 is a diagram showing a configuration of an amplifier drive circuit of FIG. 18 memory cell, 10 word line, 24 bit line pair, 12 memory mat, 14 decoder (word driver), 26 load MOS transistor, 27 load control circuit, 22 ... Y decoder, 30 common data line,
32: first stage detection amplifier, 34: second stage drive amplifier, 36: multiplexer, 38: output data bus, 20: clock generation circuit, 40: amplifier drive circuit 28: Effective memory mat, 10: Memory array.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shigeru Honjo 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Koichiro Ishibashi 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi Inside the Central Research Laboratory of the Works (72) Inventor Toshiaki Masuhara 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of the Hitachi, Ltd. (56) References JP-A-59-210588 (JP, A) JP-A-56-118369 ( JP, A) JP-A-54-148442 (JP, A) JP-A-61-96589 (JP, A) JP-A-59-155954 (JP, A)

Claims (7)

(57) [Claims] A memory block including a first area having a plurality of memory cells arranged in a matrix and a second area having a plurality of memory cells arranged in a matrix; and a plurality of columns designating columns of the plurality of memory cells. A plurality of first word lines designating only the rows of the memory cells in the first region and a plurality of second word lines designating only the rows of the memory cells in the second region A word line, a y decoder for selecting at least one of the plurality of bit lines, and an x decoder for selecting at least one of the plurality of word lines, wherein the plurality of first word lines are the x decoder. And the plurality of second word lines are connected to the x-decoder to the first word line.
The connection wiring is connected at one end to the x-decoder, is disposed so as to cross the first region, and is connected at a connection point to the second wiring at a connection point. A semiconductor memory device which is connected to a word line. 2. The semiconductor memory device according to claim 1, wherein said first region is disposed between said second region and said x decoder. 3. The connection line and the second word line are formed in different wiring layers, and are connected by a first contact at the connection point.
Or the semiconductor memory device according to 2. 4. The semiconductor memory device according to claim 3, wherein said first contact is disposed between said one end and said other end of said connection wiring. 5. The semiconductor memory device according to claim 4, wherein a second contact is further provided at said other end, and said connection wire is connected to said second word line. 6. The connection line traverses the first region and the second region, and the connection point is between the first region and the second region. The semiconductor memory device according to claim 1, wherein: 7. The semiconductor device according to claim 1, wherein no logic circuit exists between said connection wiring and said x decoder or said second word line, and the connection wiring is directly connected. The semiconductor memory device according to claim 1.