JP3024156B2 - Variable length data memory interface circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable-length data memory interface circuit which can be accessed as a memory having an arbitrary data width as a fixed-length data memory.

"Prior art" As is well known, RAM (random access memory)
And other readable / writable memories can read / write only data of a predetermined width at a time. Therefore, for example, a 1-bit memory requires the number of memories corresponding to the data width. That is, if the data width is 8 bits, 8 memories are required.

[Problems to be Solved by the Invention] As described above, a memory such as a RAM can only read / write data of a predetermined width at a time. The number of memories required for the data width was required. In addition, even if the width of data required at a time is small, data can be read / written only in a predetermined data width, so that a heavy load on software such as performing a shift operation is used, and a consistent algorithm is used. I couldn't do that.

The present invention has been made in view of the above circumstances, and has a variable-length data memory interface capable of reading / writing data from / to a memory without imposing a large burden on software even for data other than data having a predetermined width. It is intended to provide a circuit.

[Means for Solving the Problems] The present invention relates to a variable-length data memory interface circuit capable of accessing a fixed-length data memory as a memory having an arbitrary data width, and includes a virtual address specified by software and an application. Effective address generating means for multiplying the data width by a set value, adding the result of the multiplication and a count value sequentially output from a count means set to a base number corresponding to the data width, and sequentially generating an effective address; Outputting the data read from the fixed-length data memory with a predetermined data width based on the effective addresses sequentially generated by the effective address generating means, and supplying the supplied data to the fixed-length data memory It is instructed that data input / output means and sign extension by the application be performed. Bit width of the most significant bit of the data read from the fixed-length data memory, provided that the width of the data read from the fixed-length data memory is smaller than the predetermined data width. Sign extension means for setting the same bit value to a portion other than the data read from the fixed-length data memory in the data output with the predetermined data width.

[Operation] According to the above configuration, the multiplication result of the virtual address specified by the software and the data width set by the application and the count value corresponding to the number of bits of the data width (1 to 7 if the data width is 8 bits) An effective address is generated on the basis of the above-mentioned count value, and data having a predetermined data width is read or written from the fixed-length data memory using the effective address. Further, when the code extension is specified by the application and the width of the data read from the fixed-length data memory is smaller than the predetermined data width, the read-out from the fixed-length data memory is performed. The same bit value as the most significant bit of the data is set in a portion other than the data read from the fixed-length data memory in the data output with the predetermined data width. By doing so, the fixed-length data memory can be apparently accessed as a memory having an arbitrary data width.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a variable length data memory interface circuit according to one embodiment of the present invention. In this figure, reference numeral 1 denotes a readable / writable memory such as a RAM. The memory 1 has a memory capacity of, for example, 64 k × 1 bit. 2 is a virtual address register. The virtual address register 2 is a register used by software like a general-purpose address register of a normal CPU, and is set as 1, 2, 3,....
Reference numeral 3 denotes a data width register for arbitrarily setting the data width read from the memory 1. For example, when reading 8-bit data from the memory 1, the content of the data width register 3 is set to "8". The data width register 3 is set manually by an application. A multiplier 4 multiplies the content of the virtual address register 2 by the content of the data width setting register 3 and outputs the result. Reference numeral 5 denotes a counter, which performs a ternary or octal counting operation based on the contents of the data setting register 3. In other words, when the content of the data width register 3 is "8", it becomes an octal counter. An adder 6 adds the output of the multiplier 4 and the output of the counter 5 and supplies the result to the memory 1 as an effective address.

Here, each of FIGS. 2 and 3 is a diagram showing an example of generation of an effective address.

First, FIG. 2 is a diagram showing generation of an effective address having a data width of "8" bits. For example, when the content of the virtual address register is "0", the value "0" is multiplied by the content "8" of the data width register 3 by the multiplier 4 to output the value "0". Since the counter 5 is an octal counter, the effective address is "0", "1", "2",... Together with the counts "0", "1", "2". ... "7" are sequentially generated. Then, data is read serially from the memory 1 bit by bit in correspondence with each of the effective addresses "0", "1"... "7". Here, suppose that the contents of addresses 0 to 7 of the memory 1 are "101011
Assuming that the content is "10", the content "10101110" is sequentially read out by the effective addresses "0", "1"... "7", while if the content of the virtual address register 2 is "1", The output of the multiplier 4 becomes “8”, and the effective address is sequentially generated as “8”, “9”,..., “15” with the count of the counter 5. Thereafter, the effective address “8” is processed in the same manner as described above. ",
"9" ... 1 data from memory 1 corresponding to "15"
Bits are read out serially.

Next, FIG. 3 is a diagram showing generation of an effective address having a data width of "3". When the contents of the virtual address register are “0”, the value “0” and the contents of the data width register 3 are “3”.
Is multiplied by the multiplier 4 to output a value “0”.
And since the counter 5 is a ternary counter,
With the counts “0”, “1”, and “2”, the effective addresses are sequentially generated as “0”, “1”, and “2”. Then, data is read serially from the memory 1 bit by bit corresponding to each of the effective addresses "0", "1", and "2". Here, assuming that the contents of addresses 0 to 2 of the memory 1 are "101", the contents "101" are sequentially read out by the effective addresses "0", "1", and "2". go.
On the other hand, when the content of the virtual address register 2 is “1”,
The output of the multiplier 4 becomes “3”, and the effective address is sequentially generated as “3”, “4”, “5” with the count of the counter 5. Hereinafter, the effective address “3”,
Data is read serially one bit at a time from the memory 1 corresponding to “4” and “5”.

In FIG. 1, data read from a memory 1 is temporarily stored in a serial-in / parallel-out shift register 8 via a multiplexer 7. in this case,
When the data read from the memory 1 is treated as a positive number, the data read from the memory 1 is written into the shift register 8 as it is. However, when the width of the data read from the memory 1 is smaller than the data width of the shift register 8, portions other than the data of the shift register 8 are filled with "0" (see FIG. 4). On the other hand, when the data read from the memory 1 is treated as a negative number, that is, when sign extension (two's complement format) is used, the portion other than the data is the same bit as the most significant bit of the read data. Buried. In this case, both the case of filling with "0" and the case of filling with "1" are performed by the multiplexer 7. Whether or not to perform sign extension is determined by the sign extension register 9.
Is determined by the content of In this case, the setting of the contents of the sign extension register 9 is manually performed by the application. Here, FIG. 5 shows a state where the same bit as the most significant bit of the read data is filled,
The filling process is shown in FIG. Note that these figures
This shows a case where the data width is 3 bits and "-3" data is read. First, as shown in FIG.
One bit is read, and then the number of times the data width is subtracted from the register width (in this case, as shown in FIG.
(5 times) shift is performed. Next, FIG.
As shown in (d), the remaining two bits of the data are read from the memory 1.

In FIG. 1, the data temporarily stored in the shift register 8 is output to the CPU 10 in parallel. Reference numeral 11 denotes a switch for reading data from the memory 1 or setting data writing to the memory 1. In this case, when opened, reading of data from the memory 1 is set, and when closed, writing of data to the memory 1 is set.

In the variable-length data memory interface circuit thus configured, a data read operation is performed in the following process.

The shift register 8 is cleared.

Contents of virtual address register 2 and data width register 3
And the output of the counter 5 is added to the value.
It is supplied to the memory 1 as an effective address.

1-bit data is read from the memory 1, and in this case,
If sign extension is required, the shift is performed by the number of times corresponding to the value obtained by subtracting the data width set by the data width register 3 from the register width of the shift register 8.

Data is read from the memory 1 while shifting 1-bit data by the data width.

The contents of shift register 8 are read out in parallel.

In the above embodiment, the case of reading data is described. However, the case of writing data is performed by the reverse operation.

[Effects of the Invention] As described above, according to the variable length data memory interface circuit of the present invention, the multiplication result of the virtual address specified by the software and the data width set by the application and the number of bits of the data width An effective address is generated based on the corresponding count value, and data having a predetermined data width is read or written from the fixed-length data memory by the effective address. Apparently, it can be accessed as a memory having an arbitrary data width.

Also, there is no significant software change due to a change in the data width used by the application.

In addition, the memory can be accessed even with the 1-bit memory 1 in the same manner as when a plurality of memories are connected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a variable length data memory interface circuit according to an embodiment of the present invention.
6 to 6 are views for explaining the same embodiment. 1 ... memory, 2 ... virtual address register, 3 ... data width register, 4 ... multiplier, 5 ... counter, 6 ... adder, 7 ... multiplexer, 8 ... shift register, 9 ... Sign extension setting register, 10 ... CPU, 11 ... Switch.

Claims (1)

(57) [Claims] 1. A variable-length data memory interface circuit which enables access to a fixed-length data memory as a memory having an arbitrary data width, and (b) a virtual address specified by software and set by an application. Effective address generation means for multiplying the multiplication result by a data width, adding the multiplication result to a count value sequentially output from a count means set to a base number corresponding to the data width, and sequentially generating an effective address; c) outputting data read from the fixed length data memory with a predetermined data width based on the effective addresses sequentially generated by the effective address generation means, and supplying the supplied data to the fixed length data memory; Data input / output means to perform, and (d) designation of sign extension by the application And the same as the bit value of the most significant bit of the data read from the fixed length data memory, provided that the width of the data read from the fixed length data memory is smaller than the predetermined data width. Sign extension means for setting a bit value to a portion other than the data read from the fixed-length data memory in the data output with the predetermined data width, and a variable-length data memory interface. circuit.