JP3023172B2 - TR module with error correction - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to electronic management and control of radar equipment, and more particularly to a transmission and reception module having an operation mode directed to some desired features of a phased array radar equipment. You.

Among the available operating modes are antenna command mode, receive mode, transmit mode, receive calibration mode, BIT / FI
There is a T mode and a transmission calibration mode. Error correction is performed in both open and closed loops to compensate for deviations from desired performance.

Prior art In the use of radar antennas of a type of system designed to accurately determine the location of airborne remote targets that require an active stage to avoid detection, the intended operation of the radar antenna It is very important to do exactly. Control of the antenna and processing of the signals transmitted and received by the antenna is performed in part by electronic, electrical, or electromechanical devices that have very tight operating tolerances. Improving the performance of the antenna controller and its associated radar performance is still a goal.

One component of a new radar control system that controls by rapid scanning of the environment through an active aperture array type radar is commonly referred to as a transmit / receive module (T / R module). The use of advanced equipment using T / R modules overcomes the exact technical problems that limit the performance of traditional mechanical scanning radar equipment. Mechanical scanning due to antenna rotation is skipped by the electronic phase shift of the signal transmitted (and received) by the stationary antenna array. By providing a separate T / R module associated with each element of the antenna array, very rapid directional changes are made to the beam without the need for physical rotation of the antenna structure. This ultra-rapid beam pointing is enabled by precise electronic control of the phase of the signal at each antenna element.

The overall operation of an electronically scanned antenna transmits a signal and divides the signal into a plurality of signal paths, each associated with an element of an antenna array, through which the transmitted signal is desired. Is to direct the signal to each element of the antenna array with the signal phase at each element modified as necessary to form a beam directed at In the receive mode, the phased array antenna system is also directional, providing directional control by adjusting the phase of the signal received at each element of the array, and signals from the desired direction are additive;
Signals from other directions do not have the proper phase relationship and tend to cancel each other when added. This is done by providing a phase shifting device in the signal receiving path from each element and combining the "in-phase" signals by a power combiner to obtain a signal received from a predetermined direction.

T / R in addition to improved control by beam direction aiming
The module can be used at the front end of the receiver, which connects to a low noise amplifier (preamplifier), eliminating transmission losses from the antenna to the common radar preamplifier without the T / R module This can improve radar sensitivity. Another improvement is made in system efficiency, where the application of power gain at each element avoids the losses associated with the previously used integrated feed power splitter.

The phase shifting function can be performed by any technique well known in the art similar to phased array radar systems. Examples of various phase shifting techniques are described in U.S. Pat. No. 4,044,360 and Merrill I. Skolni.
Mr. k's “Radar Handbook” (McGraw-Hill 1970
Year)). The use of phase shifters in radar applications to obtain phased array radar is well known. An example of a phased array radar is described in U.S. Pat. No. 3,990,077, issued 1975, entitled "Electric Scanning Antenna for Directional Error Measurement."

The need to provide the same signal to each antenna element has given rise to a challenge phase shift matching problem despite being phase shifted relative to each other. One type of device conventionally used is known as a space feed phased array radar. In this manner, signals can be emitted from the horn onto the back of the panel of the array.
An array of apertures in the panel receives a portion of the radiated signal,
It is adapted to a feed-through type element that performs a pre-programmed phase shift and emits a signal again. Programming the phase shift of each feedthrough radiator element is a control mechanism for beam pointing. This method represents a significant improvement over previously used integrated feed devices due to the hardware complexity required to accurately supply the signal to each radiating element. The above US patent
No. 4,044,360 describes the advantages of space feed over an integrated feed device.

The use of a phase shifter to provide control by beam pointing is disclosed in U.S. Pat. No. 3,864,689, issued 1973, entitled "Hybrid Scanning Antenna", in which a multiple waveguide antenna section comprises a single long section. Used to simulate. In 1978, a system that simplifies conventional complex integrated feed-phased array antenna systems was filed as U.S. Pat.No. 4,257,050, entitled "Large Element Antenna Array With Grouped Overlapping Apertures," For example, 40 beamwidths of scan can be achieved by using only eight phase shifters and eight miniature position switches. number
A semiconductor-based phase shifter suitable for operation at GHz / S frequencies is disclosed in US Pat. No. 4,450,372, 1982, entitled "Electronically Controlled Variable Phase Shifter with Long Gate Field-Effect Transistors and Use of Such Device" Circuit ". Another method of phase shifting is 1982
U.S. Pat. No. 4,480,254, entitled "Electron Beam Steering Method and Apparatus", describes the use of a dielectric prism having a phase shift depending on the electric field strength to which the dielectric prism is exposed.

U.S. Pat. No. 4,359,742 to 1980, "Double Switched Multimode Array Antenna" discloses a radar antenna system operable in both transmit and receive modes. U.S. Pat. No. 4,376,281, "Multimode Array Antenna", dated 1980, discloses another radar antenna system designed for both transmit and receive operation.

U.S. Pat. No. 4,450,372 discloses a transmit / receive radar system that uses a separate phase shift device for each antenna element. The T / R switch is shown with intervening transmit and receive channel circuits.
In the T / R module for each antenna element, a phase shift element is provided in both transmission and reception channels for antenna pointing, that is, beam pointing. A separate control circuit is used to provide control signals for direction control.

FIG. 1 shows a typical prior art antenna device in which a terminal 101 receives a transmission drive signal and receives a signal by an antenna. Phase shifter 103 receives the phase control signals on phase control lines 104a-104d and provides the appropriately phased signals in response to receiving incoming or outgoing signals. Phase control adjusts the direction of the beam of the phased array antenna. T / R switch 105 is a phase shifter 103
The transmission or reception operation is selected by connecting either the transmission path 106 or the reception path 108 between the antenna and the antenna element 10. Power amplifier 107 amplifies the signal transmitted when in transmit mode, i.e., when the transmit path is in circuit, while preamplifier 109 is received when the system is operating in receive mode and the receive path is in circuit. Amplify the signal.

The device of FIG. 1 is limited in overall performance by tight tolerances that must meet performance improvements. For example, if 60 dB sidelobe suppression is desired, 0.5 dB R
MS amplitude and 5 ° RMS phase tracking is required. If 75 dB sidelobe suppression is needed, the system requirements are tightened. This is satisfied if such tight tolerances can be met. However, even the tolerance for 60 dB sidelobe performance enforces existing technical capabilities. Furthermore, conventional T / R modules are subject to temperature fluctuations, power supply changes, duty cycles, and pulse width changes and frequency changes in normal operation. These effects result in large phase and amplitude variations in each module, resulting in poor tracking and sidelobe performance.

A phase correction circuit for a phase shift device is disclosed in U.S. Pat.
No. 553, “Microwave digital phase shift apparatus and manufacturing method”. The microwave digital diode phase shifter provides improved phase error and improved carrier side by side spurious sideband suppression by utilizing a digital correction scheme. It also reduces amplitude modulation errors by using GaAs amplifiers that operate at saturation.

DISCLOSURE OF THE INVENTION In the present invention, the C-band transmit / receive module uses a gallium arsenide monolithic chip manufactured by the multifunction self-aligned gate method (MSAG) developed by ITT gallium arsenide technology center, for example, active aperture radar. Provided. Each module is (1) 5
A 6-bit programmable phase shift device using a number of digital and analog bits; (2)
Programmable attenuator, (3) low noise preamplifier, (4) driver, (5) power output amplifier plus T / R
Includes five GaAs chip packages consisting of switches.
Power regulators and controls, both on a thick film substrate, are provided for completely independent control.

Close phase and amplitude tracking is achieved using built-in correction and adjustment circuits for temperature, power supply changes, operating bandwidth, and phase conditions.

In a second embodiment, the elements are placed differently on the four chips and the pre-driver, driver and power amplifier are switched off the circuit if no power amplifier or driver is needed, Are connected such that the bias of the three amplifiers can be switched to reduce power requirements and heat dissipation. This is particularly advantageous because a large number of T / R modules are required for a phased array radar. B-class amplification can be used for increased efficiency.

To overcome the limitations encountered in conventional methods, corrections for both open and closed loop are used for both phase and amplitude. Open loop correction compensates for phase shift and amplitude errors for all phase states of the phase shifter, and corrects for changes in operating bandwidth and operating temperature range. Module gain and phase are all 0.5dB
Pre-calibrated to provide receive and transmit regains within 5% and phase within 5 ° of reference. The quality of the open loop correction circuit is configured to be as good as possible by using the state of the art GaAs technology. The use of GaAs elements in the feedback circuit results in very uniform device performance and can be obtained by tight quality control in the selection of matched GaAs devices.

Closed loop correction can be input to the module during service to compensate for long term variations to achieve and maintain low sidelobe performance over time under changing environmental conditions.

Additional Prior Art Prior art for switching features is disclosed in Andricos U.S. Pat. No. 4,598,252, which shows an amplifier connected in parallel and the bias does not change.

Additional prior art literature indicating phase correction is U.S. Statutory Invention Registration H173Claborn et al., Which discloses phase correction in the transmitter for temperature fluctuations in both apertures and power dividers, while receiver correction or None of the amplitude corrections are disclosed. 3 PROMs 48 and 74 in Fig. 3 are adders
The phase correction information combined at 78 is included.

U.S. Pat. No. 4,652,883 to Andricos further discloses an analog phase shifter for compensating for inaccuracies of the preset shifter plus a 5-bit phase shifter for the preset shift.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a conventional transmission and / or reception method.

FIG. 2 shows a block diagram of a T / R module having an amplitude and phase correction method.

FIG. 3 shows the performance curve of the hybrid coupled MSAG amplifier.

FIG. 4 shows the transmission mode output power of the devices summarized in Table I.

FIG. 5 shows the T / R module reception mode passband gain and noise characteristics.

 FIG. 6 is a block diagram showing another embodiment of the RF circuit.

FIG. 7 is a block diagram of another embodiment of the T / R module.

FIG. 8 is a block diagram of the amplitude and phase correction of FIG.

FIG. 9 shows the transmission mode signal level and gain distribution for the high power mode.

 FIG. 10 shows the same as the reception mode.

FIG. 11 shows the calculation of the T / R module noise figure and the reception loss.

FIG. 12 is a graph of efficiency and power output versus power input for class B operation of the amplifier.

FIG. 13 is a graph of efficiency and power output versus power input for different biases of class B.

FIG. 14 is a graph of power output versus frequency for different drain voltage and B class drives.

FIG. 15 is a graph of class B power output and efficiency versus power input.

 FIG. 16 is a schematic diagram of the 10 dB step attenuator 712 of FIG.

FIG. 17 is a partial block diagram and a partial schematic diagram of the power amplifier 711 of FIG.

 FIG. 18 is a schematic diagram of the SP3T switch 707 of FIG.

FIG. 19 is a schematic diagram of the switch of FIG. 18 in a high power mode.

FIG. 20 is a block diagram and a flowchart of the digital control circuit in the lower left part of FIG.

FIG. 21 is a block diagram of the T / R module amplitude and phase correction method.

FIG. 22 is a block diagram of the closed loop calibration of the module controller.

BEST MODE FOR CARRYING OUT THE INVENTION A block diagram of a T / R module having an amplitude and phase correction scheme is shown in FIG. The phase correction is generated within 1 ° by the analog phase bit 201 of the phase shifter 202 and the gain is corrected in an analog programmable attenuator 203 in 0.2 dB steps.

The inputs to the correctors 202 and 203 consist of a 13-bit phase code and a 4-bit amplitude correction. The former consists of an 8-bit phase shift setting 204, a 2-bit frequency setting 205, and a 2-bit temperature setting 206 for both transmit and receive modes. The 8192 × 8 EEPROM 207 stores a total of 256 phase states for four frequencies and four temperatures and for both receive and transmit modes. The output line of the EEPROM 207 is divided into a 4-bit phase correction 208 (1.25 degree resolution) and a 4-bit amplitude correction 209 (0.25 dB resolution). EEPROM 207 contains all open loop correction periods entered during module calibration. Inter-module tracking is improved because the temperature correction adjusts the phase and amplitude to correspond to the average temperature sensitivity gradient. Frequency input 205 adjusts for amplitude and phase ripple in the bank. Input 20
Temperature sensors for 6 are located on each module controller board.

The 4-bit amplitude correction 210 adds the condition to the compensated gain adjustment 211 in an adder 212 to adapt the closed loop gain adjustment for more precise control. Closed loop adjustment of the phase is achieved by the 8-bit phase command word 204.

The module can be constructed using eleven GaAs MMICICs mounted in five packages as shown. Ferrite circulator 213 protects the output of power amplifier 214 from high power standing wave ratio (VSWR) during transmit mode and, in conjunction with switch 215, transmits from antenna 216 to low noise amplifier (LNA) 217 during receive mode Send.
The buffer amplifier 218 is provided between the attenuator 203 and the switch 215.

The main assemblies of the T / R module are: (1) The programmable phase shifter 202 has five digitally controlled phase bits and 11.25- ゜, 22.5
-゜, and analog control bits that provide a phase error of less than ± 2 ゜ for 45-45 bits. 90− ゜ and
For 180- ゜ bits, the phase error is less than ± 6 ゜ for a 1 GHz bandwidth.

(2) Programmable attenuator 203 uses double-gate FETs to achieve 2dB gain control with constant VSWR and bandwidth. The phase change is less than 3 ° for a 5 dB gain change.

(3) Drive amplifier 219 provides 25 dB of gain over its bandwidth at an output of more than 2 watts. It consists of a three-stage amplifier and three 2.5m FETs in an output configuration combined to output high power.

(4) The output power amplifier 214 is a hybrid having a gain of 7 dB and a gain change of less than 1 dB over its bandwidth. The circulator 213 at the output prevents thermal burnout of the FET at high load VSWR.

T / R switch 215 uses a two-section shunt mode FET switch in the receive arm to have more than 33 dB of isolation at high power levels. The insertion loss is kept below 1 dB over the bandwidth.

(5) In the receiving loop, the low noise amplifier 217 has a good V
A balanced circuit using an on-chip range coupler at the input and output for SWR and low noise. A 25 dB gain is achieved with a 1 dB compression point of +14.5 dBm.

These chips were constructed using the recessed gate method rather than the improved MSAG method described above. Even better performance is achieved with the MSAG device.

The performance curves for the hybrid coupling complex of four 3.5 watt driver ICs using the MSAG method are shown in FIGS. 3A and 3B
Is shown in This amplifier provides a 14 watt output with a 35% power added efficiency over the 5.2-5.9 GHz frequency band as shown in FIG. 3A. Gain is 5.5d
B. These remarkable results indicate the improvement achieved using the MSAG device. Diagram of gain flattening over frequency
Excellent as shown in 3B. This amplifier is 32mm
Including the periphery of the output FET gate. The method used was consistently reported to be 750 mW / mm under appropriate design conditions, so a final power amplifier close to 20 watts is possible without problems. Since this is more power than necessary, the amplifier can be derated and increase reliability.

The measurements from the three T / R modules are summarized in Table I. A graph of transmit mode output power versus frequency for the three modules is shown in FIG. Output power is 5.55
Over 12 watts in GHz. The gain flatness is good.

Table I “IRAD T / R Module Measurement Aggregation” Measurement Data Receive Mode Bandwidth (1dB)> 600MHz Noise Figure 5dB Gain 25dB Gain Flatness over 50MHz Segment ± 0.3dB Input VSWR <1.5: 1 Amplitude Linear ± 0.2dB 1dB Compression Point + 12dBm Third order intercept + 23dBm Output VSWR <1.5: 1 Phase linearity over 50MHz segment <5 ゜ Transmission mode Gain 25dB Power (at module output) 12W Output VSWR ≤1.3: 1 Power efficiency 20% Input VSWR <1.5: 1 Pulse width 0.1-200usec Duty cycle 30% maximum Pulse amplitude droop 0.1dB (100usec) Phase within pulse 5 ゜ Input VSWR <1.5: 1 Phase shifter 6 bits Phase accuracy <3 ゜ RMS 5 ゜ peak Amplitude change 0.5dB peak ( 0.25dB RMS) Programmable Attenuator Range 15dB Power Supply + 12V, -12V Power Drain 17Watt (25% Duty) Weight 8oz Dimensions 4-7 / 8 x 1-3 / 8 x 1 inch Operation Temperature −54 to + 85 ° C. FIG. 5 shows the T / R module reception mode passband gain and reception noise figure. The gain is flat over the frequency band of interest.

The module was tested over a temperature range of -55 to + 85 ° C to determine phase and amplitude changes with or without correction circuitry. Without compensation, the T / R module receive mode over the full temperature range of -55 to + 85 ° C
Shows less than 10 ° phase and less than 1.5 dB gain tracking. The correction circuit adjusts the phase and amplitude with temperature to set values that approximate the average module slope. This corrects gain within 0.5 dB peak and phase within 5 ° peak over operating temperature. This results in an RMS phase of 3 ° and an amplitude tracking error of 0.25 dB.

Similarly, when there is no correction, the transmission mode gain is +1.5 to 2
The phase tracking is within 15 ° for operating temperatures between -55 and 85 ° C. With correction, tracking error is 0.5dB
Peak amplitude and 5 ° phase. Aggregation of T / R module sensitivity and tracking data is shown in Table II.

The sensitivity coefficients of all GaAs circuits of the T / R module to changes in voltage from the power supply are compared with and without the internal regulator. The sensitivities are summarized in Table III. An internal regulator provides low frequency (less than 120 Hz) rejection of more than 60 dB of input change. For the internal power regulator, all DC sensitivities are reduced to negligible values. A voltage change of ± 10% of the total bias voltage to the module does not cause a measurable gain or phase change in transmit or receive mode.

As shown in FIG. 6, the RF circuitry of another embodiment of the module includes a number of new features.

The integrated front dipole radiating element 601 and the integrated rear dipole radiating element 602 are replaced with RF connectors to adapt their operation as active elements of a space-fed lens array.

A DPDT T / R switch 603 is provided on the back of the module to re-adapt the space lens operation.

The RF circuit for each emission channel is divided into five MMIC chips as shown in FIG. This high level of integration is consistent with an optimal compromise between chip yield and interconnect cost.

All MMICs in a module are manufactured by a single method. The driver 604 and final power amplifier 605 have been found to provide a flat 14 watt power output with 35% efficiency over the 5-6 GHz band.

The intelligent module controller 606 is configured in the form of an ASIC (Application Special Integrated Circuit) gate array. The module controller 606 allows wireless control of the array and T / R module, as well as T / R module status monitoring, error calibration, and alignment.

Table IV summarizes the performance characteristics of each RF channel of the module assembly.

Table IV “T / R Module RF Performance Characteristics” RF Transmit Channels (each) Operating Frequency Band 5.25-5.85GHz Min Gain Nominal 32.8dB RF Power Output (Emitted) 12W Min Peak Duty Cycle 20% Max Pulse Width 1 Up to 200 microseconds Maximum load VSWR Infinite (open or short circuit) Power amplifier Chain frequency 35% (DC to RF) RF receiving channel (each) Operating frequency band 5.25 to 5.85GHz Minimum gain Nominal 25dB Noise figure (system) 2.8dB maximum 1 dB compression point +10 dBm (output) 3rd order intercept +20 dBm input VSWR <1.3: 1 Common RF characteristics Phase shifter 6 bits (5 digital + 1 analog) Programmable attenuator range 10 dB minimum Figure 7 shows the present invention using four chips T / of another embodiment
Shows the R module. Important to achieve the required phase and amplitude accuracy and tracking of the T / R module is the use of a high uniformity MSAG method and simple open loop error correction of the module.

An open loop pre-calibrated form is used to meet tight phase and amplitude accuracy and tracking requirements with respect to phase state, attenuation range, frequency, and temperature. It is not expensive and gives the minimum requirements for antenna configuration.

The detailed block diagram of the module shows how the command signals are processed by the controller to obtain 3 ゜ RMS phase and 0.5 dB RMS amplitude accuracy of the module. Three EE
PROMs 701, 702, 703 are used to store the gain and phase corrected values for each programmed instruction.

The use of GaAs chips with high temperature and frequency uniformity and small phase and amplitude gradients is important to meet tracking requirements between devices after the initial phase and amplitude errors have been calibrated by the PROM. Accurate voltage input to the module minimizes errors due to voltage fluctuations. GaAs
On-chip measurements show good long-term stability of the post-combustion step parameters, making the open loop calibration method feasible.

A block diagram of the T / R module amplitude and phase correction is shown in FIG. The phase correction is generated to ± 10 ° by the analog phase bits of the phase shifter 801 while the gain is corrected in an analog programmable attenuator 802 in steps of ± 0.25 dB.

The input to the EEPROM 803 consists of a 6-bit phase shift setting 804, a 3-bit frequency setting 805, and a 3-bit temperature setting 806 for both receive and transmit modes.
It consists of a 13-bit phase code. EEPROM output line is 4
It is divided into a bit phase correction 807 (resolution of 1.25 degrees) and a 6-bit amplitude correction 808 (resolution of 0.25 dB). EEPROM8
03 includes all open loop correction periods entered during module calibration. Inter-module tracking is improved because the temperature correction adjusts the phase and amplitude to correspond to the average temperature sensitivity gradient. The frequency input adjusts for in-band amplitude and phase ripple at 100 MHz intervals. Temperature sensors are located in each module controller board.

The phase bit input command signal 804 is modified by the necessary phase correction when the transmission gain is changed by the digital adder 809. Phase correction for receive gain control is not required due to the phase accuracy and stability of the programmable attenuator 802.

The module controller performs the following operations on the module.

a) Receive the 6-bit phase command signal 804 and set the module phase correctly. Phase correction is applied to temperature, frequency, and phase conditions to maintain tracking over required module accuracy. In addition, phase correction is applied when the transmission gain is changed to compensate for the switching amplifier and changing drive levels.

b) Receiving the 5-bit receiver gain control command 810 and receiving 20 dB
Set the gain over the range. The correction is applied to compensate for the nonlinearity of the analog attenuator 802.

c) Receive the 6-bit transmission gain control command 811 and set the module transmission gain over a 30 dB range. The decoder switches on all power amplifiers and sets the module in the corrected power output mode. The controller corrects for the non-linearity of the output amplifier over the dynamic range.

d) Convert the output of the controller with built-in temperature sensor to digital form and use the output to correct for module phase and gain gradients to improve tracking. The MOSFET switch that switches the power amplifier on and selects the drain supply is part of the controller. The interface circuit and the level shift device that provide the gate bias for the device FET switch are also part of the controller.

The microwave section of FIG. 7 consists of four circuits, three of which are fully integrated MMIC designs. Power amplifier 711 has an external splitter and combiner 4
A hybrid circuit including two monolithic circuits.
All T / R modules 705 and power modes 706 are integrated in the MMIC chip configuration except for the output power mode 3P3T switch 707. GaAs PIN diodes are used for this function to minimize switching losses in high power modes. The separate EEPROM is used for correcting the phase command 701, the reception gain command 702, and the transmission gain command 703. Decoder 708 switches power amplifiers 709, 710, 711 to the appropriate configuration for the transmit attenuation command.

Programmable attenuator is a 0 / 10dB digital switch
712 and an analog attenuator 713 of 0 to 13 dB. This is used to set the required module attenuation and to fine tune the gain change of the programmable phase shifter 714 over all conditions, ie, temperature and frequency. Buffer amplifier 733 is a digital attenuator 712
And the switch 706.

The phase control EEPROM 701 is connected to the A / D circuit 7 from the built-in thermistor 716.
A 3-bit temperature 715 is input via 17. A 3-bit frequency control 718 is also input to make corrections over the 600 mHz operating band. The controller also includes a level translator that sets the voltage input to the MMIC circuit at a level appropriate for operation.

+ 5V arrival voltage supplied to conductor 719, 10V arrival voltage supplied to conductor 720 and conductor 72
The incoming voltage of -10V supplied by 1
3,724, respectively, held during the pulse by a large storage capacitor 725 bypassing the positive supply. FET switch 726 is a multiple MOSFET device that switches the drain voltage between + 10V, + 5V, or 0 volts. Separate drain control switches off unused amplifiers and allows class B idle current to be reduced to zero. Class B amplification is used to increase efficiency and reduce temperature.

The instruction switches switch 729 between EEPROMs 702 and 703, and T
Guided by interface 728 to switch / R switches 705,706 and LNA switch 730. Digital-to-analog converters 731 and 732 convert the output from EEPROM 701 to analog input 734 of phase shifter 714, respectively, and adder 727 having the output of switch 729 as another input.
To the analog input 735 of the attenuator 713. Digital output 736 of adder 727 flows to digital attenuator 712.

The receiving channel elements are arranged to optimize the overall noise figure and dynamic range with respect to operating temperature. The gain and level diagram shown in FIG.
Indicates the signal level encountered at the receiving path at 75 ° C. The overall reception gain is 25dB at 75 ° C and increases to 30dB at room temperature. These gain changes are due to the FET stages of the amplifier chain, corresponding to a nominal gain-to-temperature gradient of 0.016 dB / ° C per stage. The modules are expected to track gain very closely with respect to temperature, and open-loop corrections are applied to bring each module gain versus temperature gradient to a nominal value. Two input signal levels, the expected maximum operating level of -28 dBm and the maximum linear level of -21 dBm, are shown in FIG. The noise figure requirements of the module are consistent with using an input preamplifier with a 2 dB noise figure at 25 ° C.
The calculation results shown in FIG. 11 give a 3.2 dB module noise figure at 25 ° C. and a 3.8 dB noise figure at 75 ° C., taking into account 1.25 dB input loss.

The 1 dB compression point of all active microwave elements is shown in FIG. 10 with the signal level encountered at the maximum operating signal level. Since all the signals shown in the table are larger than 5 dB under compression, excellent amplitude and phase linearity are achieved.

The instantaneous dynamic range of the receiver is shown in FIG. 11 using a noise figure of 4 dB and a bandwidth of 100 MHz. A 69dB dynamic range is obtained at 25 ° C with a maximum output signal level of 9dBm. At 75 ° C, a dynamic range of 69 dBm is obtained with a maximum output signal level of 7 dBm.

The use of wideband monolithic elements in the transceiver results in excellent phase linearity and low amplitude ripple over the operating bandwidth. Measurements with existing GaAs monolithic C-band amplifiers have demonstrated less than 0.2 dB of amplitude ripple and less than 2 ° of phase linearity over 200 MHz.

The transmit output power is kept above 10 watts (+40 dBm) and the overall maximum gain is kept above 30 dB for all operating environments.

The transmission level distribution diagram of FIG. 9 shows the signal level and gain along the transmission path for operating temperatures of 25 ° C. and 75 ° C. The change in nominal gain with temperature is based on measured or estimated gain versus temperature sensitivity and changes in the drive level of the power stage. When the temperature is 25 ° C., the buffer amplifier 904
Is compressed to 1 dB, resulting in a power output amplifier 906. 10.94 watts of output power is achieved with an overall gain of 30.4 dB. When the temperature is + 75 ° C., all amplifiers 904,906 are compressed to less than 1 dB by obtaining 10 watts with an overall gain of 30 dB.

Both harmonic and non-harmonic spurious frequencies are maintained at low levels at the transmitter output. DC bias supply 1/4 according to measurement of single-ended B-class power amplifier
40 dB of harmonics due to wavelength line and matching network
Gives the suppression. Additional suppression of the output isolator further reduces this noise figure.

Power amplifiers are designed to be stable and do not exhibit spurious modes when pulsing. The operating voltage is kept below the avalanche point, and the power supply is filtered sufficiently to prevent regeneration.

Discrete non-harmonic spurious signals are power FETs
65dB measured in pulsed and continuous wave B class mode
Was found to be less than.

The measured performance of a GaAs FET operating in B-class mode shows excellent characteristics with high efficiency, constant gain, and good phase characteristics over a 7 dB dynamic range.

To determine the potential for GaAs FETB class operation, measurements were made in the C band with both pulsed and continuous wave inputs of multiple devices and circuits.

The device tested was a GTC AlGaAs 2.5 mm power FET and the power amplifier MMIC circuit consisted of three standard power FETs (GTC 227
-1) and internally matched power FETs manufactured by Fujitsu Limited (FLM 5359-14).

All these amplifiers were tested in B-class mode in single-ended form.

Important characteristics to be applied as variable power devices in T / R modules have been measured. These are power output versus power input linearity, power added efficiency, transmit phase change versus input power,
And operation at reduced drain voltage. Measurements on pulse operation were made to determine the on or off characteristics of a B class amplifier. The phase swing during the pulse (intra-pulse phase change) and the inter-pulse phase change (inter-pulse phase change) were measured. Similarly, droop of intra-pulse amplitude and inter-pulse amplitude change were noted. For good MTI performance, it is important that these phase amplitudes and phase changes are low and do not exhibit irregular characteristics. Gain and phase sensitivity to drain voltage during pulsed mode were also measured. Pulse and continuous wave mode spectral analysis was performed to determine spurious levels.

GTC's 2.5mm AlGaAs power FET has good properties for B-class operation. This characteristic includes a low pinch-off voltage of 2V, a high drain breakdown voltage of 30V, and high gain.

The GTC 2.5mm FET was biased at -2V and was slightly below the pinch-off voltage, so a 0.1mA quiescent drain current was set.

Figure 12 shows the curve of power added efficiency and power output versus power input.
Is shown in A well-constant gain of 7.5 dB is obtained up to the 1 dB compression point and occurs at an output of 1.7 watts (+32.4 dBm). At this time, the power added efficiency peaked at 50.7%. For operation from the 1 dB compression point to +25.4 dBm (0.346 watts), the efficiency remains higher than 25%.

Gate current monitored over input drive range is 1dB
20mA is reached at the compression point. For a 10 finger device, this is close to the maximum allowable finger gate current of 2 mA for reliable operation.

The range of the 10dB transmission phase change is less than ± 1.5 ゜ to the 1dB compression point.

A similar type of measurement was made based on the Fujitsu Limited FLM 5359-14 C-band power FET, and the results are shown in FIG. The internally matched power FET is a hybrid device with a pinch-off voltage of 2V and a breakdown voltage of 30V.

Efficiency, power output and phase shifter versus input power levels were recorded for drain voltages of + 10V, + 9V, + 7V, + 5V, and + 3V.

The gain is constant for each operating voltage over a wide dynamic range. Gain from 7.5dB at + 10V to +
Drops to 6.0dB at 5V. Power output at 1dB compression is +
At 10 V it is 16.3 watts (+42.14 dBm) and at +5 V it is 3.88 watts (+35.88 dBm).

A graph of transmit phase change Δφ versus power output is shown from the low level input to the + 10V, + 7V, and + 5V 1 dB compression points. A phase shift of less than ± 1.5 ° occurs for all these operating voltages.

Peak power efficiency is maintained above 35% for all these voltages in the range of 5V to 10V.

Graphs of power output with respect to frequency characteristics at different drain voltages are shown in FIG. In the range 5.3 to 5.9 GHz, the bandpass curve is maintained as when the power supply is changed from + 3V to + 10V.

Very low knee voltage makes this FET + 3V
Shows acceptable performance when operating with a drain power supply.

Testing of the MMIC power amplifier using the MSAG device was performed.
The pinch-off voltage for the FET is -4.61V, the bending voltage is about 2.6V, and the drain breakdown voltage is 18V.

The performance of this amplifier in B class mode is shown by the curves in FIG. 4 dB linear gain of 1.4 watts (+31.46 dBm)
Up to the 1dB compression point. The power added efficiency peaks at 23% and drops smoothly to 10% when the power drops to 7dB. Low gain, high pinch-off voltage, and bending voltage can result in low efficiency. The drain efficiency of this device is about 39%. By inserting an AlGaAs FET in this circuit, the efficiency is increased by over 50%, the gain is increased to 7.5 dB, and the power output is increased to 3 watts.

The curve of the phase shift versus power input graph gives good results of less than 2 ° over the dynamic range.

The measured curve for the pulsing of the power input gives good results of less than 2 ° over the dynamic range.

Measurements of the power amplifier pulse operation were made to determine the on-off characteristics in class B operation and to measure transient phase and amplitude effects.

Class B power amplifiers exhibit excellent linearity, efficiency, and pulse characteristics over a wide range of power output levels. 65dB over 10dB spurious level dynamic range
Lower.

This T / R module uses a total of four GaAs chips, the three chips being fully multifunctional and fully integrated. Table V shows the chips and their associated properties.

The chip set uses the MSAG method for superior performance and improved reliability. These chips are single-substrate multi-function circuits including through holes, internal bias resistors, and connections.

Chip # 1 comprises a low power DPDT switch 705, a programmable phase shifter 714, a digital one bit programmable attenuator 712, and an analog attenuator 713.

DPDT switch 705 is effectively two SPSs connected in cascade
T (similar to chip # 2) is a series shunt switch. The 1-bit programmable 0.1 dB step attenuator uses two SPST 600 μM FET switches with fixed resistance pads.

The phase shifter 714 provides an accurate 6 bit (5 digital +
1) MMIC design. The MMIC chip configuration and its measured performance showed significant phase accuracy with respect to frequency, temperature and phase bit settings, and low insertion loss and low insertion loss variation. It has the best properties of any other reported MMIC phase shifter.

The programmable phase shifter 714 is an important component of the transceiver that maintains phase accuracy and amplitude stability, and tracking between the devices. This phase shifter 71
4 meets T / R module system requirements when combined with open loop error compensation and correction circuit. Correction is with analog phase correction bit 734 and programmable attenuator 713
Applied to The phase shift device consists of five digital bits and one analog bit. A sixth bit resolution of 5.6 ° is achieved using analog bit control. It is also used to correct for errors in the phase shifter as well as other external errors. ±
The 10 ° phase adjustment range allows complete compensation of the phase error for all bits due to frequency and temperature in the worst case.

The phase shifter 714 is composed of six cascaded stages. 11.25 ゜, 22.5 ゜, and 45 ゜ bits consist of loaded line sections, while 90 一方 and
The 180 ° bit uses a Lange coupler for a reflection type phase shifter. The latter has a line width and gap of 12μ
Use a Lange coupler designed to be m and 4.96 mm in total length. The 2400 μm FET switch terminates the transmission line matching network that produces the incoming signal reflected by the required 90 ° phase shift. For each bit
FET dimensions are optimized for best VSWR and insertion loss and three different FET perimeters of the circuit, ie 1200μ
m, 1800 μm, and 2400 μm.

These large FETs also degrade high power handling capability.

Analog Bits Use FETs in Variable Impedance Mode to Adjust Phase Shift over ± 10 °
It consists of the range of ゜. The load line section consists of a transmission line approximately 1/4 wavelength long, approximately 50 ohms, loaded with high impedance stubs terminated at both ends by FET switches. The measured performance of the phase shifter is summarized in Table VI.

Table VI Programmable Measured Phase Shifter Performance Operating Frequency 5.0-6.0GHz Digital Bits 180 ゜, 90 ゜ 45 ゜, 22.5 ゜ 11.25 ゜ Analog Bits ± 10 ゜ Phase Accuracy 5 ゜ for Bits, Frequency, and Temperature
RMS insertion loss 7 dB max Loss change over bit, frequency, and temperature ± 0.5d
B Switching time 0.2μs Analog bit adjustment range ± 10 ゜ Insertion loss change Phase ± 0.2dB Peak control voltage -3 ~ 0V Phase stability ± 1 ゜ In-out VSWR ≤1.4: 1 1dB compression point + 20dBm Tertiary intercept point + 30dBm Analog The programmable attenuator 713 adjusts the gain of the T / R module over a 10dB range and is used to compensate for gain change (3dB) with phase setting, frequency, and temperature, resulting in 6dB of increased system accuracy Reduce the sensitivity to less than 1 ° per gain. This is achieved by using both gates of a double gate device for control. Its performance is shown in Table VII.

Table VII Programmable attenuation characteristics Operating frequency 5.0 to 6.0 GHz Gain control Analog gain adjustment range 13 dB Insertion loss 3 dB maximum Noise figure (maximum gain) 5 dB Phase change over 10 dB attenuation ± 1 ゜ Amplitude stability over temperature and frequency ± 0.2 dB 1 dB Compression point + 5dBm Third order intercept point + 15dBm Gain control switching time ± 0.2μsec Input VSWR <1.4: 1 Input VSWR <1.4: 1 Power + 10V at 10mA -4V 1mA 0 / 10dB Digital attenuator 712 is fixed 10dB
Used to provide step gain changes to the module. This design uses a DPDT switch 1601 developed with a fixed resistor pad 1602 as shown in FIG. Through line 1603 is phase matched to a phase change of greater than 1 ° over a 10 dB switch range in length. To minimize the size, a 600 μm FET is used for the switch because the absolute loss is not critical to this circuit.

 Performance details are shown in Table VIII.

Table VIII Performance of 1/10 step attenuator Operating frequency 5.0 to 6.0GHz Attenuation 0 or 10dB Attenuation accuracy ± 5dB Differential phase shift ± 1 ゜ Fixed loss 2dB maximum Switching time <0.2μs Input VSWR <1.4: 1 Output VSWR < 1.4: 1 1 dB compression +10 dB maximum voltage input +20 dB command -3 to 0 V high impedance-DPDT T / R switch 705 must handle more than +10 dBm and must have high isolation to prevent crosstalk. Two SPST switches using 2.5mm FETs in series shunt configuration are used to construct a compact circuit.

 The switch performance is shown in Table II.

Table IΧ Performance of DPDT T / R switch Operating frequency 5.0 to 6.0GHz Maximum power input (CW) 100mW (+ 20dBm) Insertion loss 1dB Isolation ≧ 40dB Switching time ≦ 0.2μsec Input VSWR <1.4: 1 Output VSWR <1.4: 1 chip # 2 is integrated on a single chip with dimensions of 4100μm x 4400μm, three-stage LNA737, two-stage buffer amplifier
733, and SPDT switch 706. Preamplifier 737
Includes three 0.8 μm × 300 μm GaAs FETs, while buffer amplifier 733 includes 0.8 μm × 300 μm and 0.8 μm × 60 μm.
It has a 0 μm FET. SPDT switch 706 includes four 2.5 mm FETs in series shunt configuration.

Receiver LNA 737 and buffer amplifier 733 are low noise amplifiers that use new MSAG ultra-low noise FETs to achieve 2 dB noise figure, high gain and dynamic range.

The amplifier is designed to meet the required overall system dynamic range of 60 dB and a noise figure of 2.8 dB. 25 for low noise, low input VSWR, and receiver input
Low noise preamplifier 737 with dB gain stage and 17 dB
Two amplifiers are used, a buffer amplifier 733 having a high dynamic range and a high dynamic range used for both receive and transmit modes. The input amplifier maintains the linear characteristics of the system over a wide dynamic range by having a 1 dB compression point of +6 dBm. Low noise preamplifier
The 737 uses a three-stage single-ended configuration, and the buffer amplifier 733 uses a two-stage cascaded amplifier to meet these requirements.

The performance of these amplifiers and switches is shown in
I and Table II. An external PIN diode limiter is used to prevent damage from a + 20dBm continuous wave input.

Table II LNA Performance Operating Frequency 5.0 to 6.0GHz Nominal Gain (75 ℃) 25dB Gain Flattening over 100MHz Bandwidth ± 0.2dB Input VSWR ≤1.4: 1 Output VSWR ≤1.4: 1 Noise Figure at 75 ℃ 2dB Max 1dB Compression point ≦ + 5 dBm 3 order intercept point ≦ + 15 dBm 5V input CW level for amplitude linearity ± 0.1 dB bias 25mA across a bandwidth over the bandwidth of the phase linearity ± 2 ° 100MHz of 100MHz, no damage + 15 dBm table ΧI buffer amplifier performance operating frequency 5.0 ~ 6.0GHz Nominal gain (75 ° C) 17dB Gain flattening over 100MHz bandwidth ± 0.2dB Input VSWR ≤1.5: 1 Output VSWR ≤1.5: 1 Noise figure at 75 ° C ± 3.0dB Max 1dB compression point + 15dBm Third order intercept Point + 25dBm Phase linearity over 100MHz bandwidth ± 2 振幅 Amplitude linearity over 100MHz bandwidth ± 0.1dB Bias 5V for 30mA -4V for 1mA Table II Performance of SPDT-T / R switch Operating frequency 5.0 to 6.0GHz Switch type SPDT Maximum power input (CW) 100mW (+ 20dBm) Insertion loss ≤1dB Isolation ± 30dB Switching time ≤0.2μsec Input VSWR ≤1.4: 1 Output VSWR ≤1.4: 1 Instruction on 0V Instruction off -3V Chip # 3 has high power T / R switch 705, pre-drive amplifier
709, drive amplifier chain 710, and two SPST switches 73
Includes 8,739. SPST switches 738, 739 are similar to switches on chips # 1 and # 2, but have higher power levels. Output switch 739 uses a 4mm FET to use 2 watts of power.

Pre-drive amplifier 709 and drive amplifier 710 each have 24
It is a B class circuit that supplies 0 mW and 1.7 w.

Pre-drive amplifier 709 comprises a 600 mm FET biased for B-class operation. The FET has a low pinch-off voltage of -1.5V and a B class gain of greater than 10dB. The performance of the amplifier is shown in Table III.

Table III Performance of pre-drive amplifier Operating frequency 5.0 to 6.0GHz Operating mode B class Power output (1dB compression) 250mW Gain 10dB minimum Power added efficiency 67% Operating drain voltage + 10V Input VSWR ≤1.4: 1 Output VSWR ≤1.4: 1 Drive Amplifier 710 consists of a 2.5 mm FET that produces 1.7 W of power. This amplifier is used for the output stage in the intermediate power mode of the T / R module. Its performance is shown in Table IV
Is shown in

Table IV Performance of IV drive amplifier Operating frequency 5.0 to 6.0GHz Operating mode B class Power output (1dB compression, + 10V drain) 1.7w gain 9dB power added efficiency 67% Operating drain voltage + 5V to + 10V Input VSWR ≤1.4: 1 Output VSWR ≤1.4 1: Chip # 4 is a hybrid circuit that includes a discrete MMIC chip 1701 of four 3.2 watt amplifiers coupled on a high dielectric microwave substrate as shown in FIG. This constitutes a power amplifier 711.

Each MMIC chip amplifier 1701 is a push-pull circuit type B
Includes two 2.5mm FETs 1702 operating in class. Each MMIC
The chip can generate 3.2 watts of power at the 1 dB compression point when operating with a +10 V drain voltage. The four-way coupling at 1703 produces about 12 watts of total power.

 The performance of the power amplifier 711 is shown in Table IIV.

Table II Operating frequency 5.0 to 6.0GHz Operating mode B class Power output (1dB compression) + 10V drain 12w gain 9dB power added efficiency 67% Operating drain voltage + 5V to + 10V Input VSWR <1.4: 1 Output VSWR <1.4: 1 12 in total Watt amplifiers have very high density packages. Input and output substrates and single chip GaAs
FETs have excellent heat sinks in sealed environments
Mounted on a 0.5 x 0.5 inch metal container.

The input section is a four-way power splitter 1704, four pairs
Four baluns feeding a 2.5mm GaAS FET (balanced
Unbalanced transformer), and four simple impedance transformers 1705. The output section is a replica of the input to collect the total output power. The balun design is a standard coplanar circuit with changes to small dimensions.

Each coarse transmit output power level of the module is quickly selected and maintained with low power loss by providing a high efficiency RF power switch.

Poor control of the module transmit output power level is provided by a single pole, three throw RF switch 707. The insertion loss associated with each switch position is minimized. This is because this reduces the overall module output power. The first switch position handles RF power levels from 1 to 10 watts, and overall efficiency is one of the most critical requirements.

Switch design compromises focus on low loss at the level 1 position and compromises on the second and third levels.
The electrical properties for the selected candidate are shown in Table VI. Table II VI RF Switch Characteristics Transmission Mode Insertion Loss Insulation High Power <0.1dB> 50dB Intermediate Power <0.3dB> 28dB Low Power <0.3dB> 28dB High frequency switches have low insertion loss and high insulation when carefully selecting control elements. Can be achieved. Currently new technologies on GaAs are available for PIN diodes with high cut-off frequency and low insertion loss.
The RF equivalent circuit of the three-way switch is shown in FIGS. P ₁ , P ₃ , and P ₄ are the input connections for the three differential power supplies. D ₁ , D _2A , and D _3A are handled by zero current, D _2B and D _3B are each driven at 10 mA, and the RF power at P ₁ is transmitted to P ₂ and isolated from P ₃ and P ₄ .
L ₁ is inserted to reduce the input VSWR. Level 2 and 3 transmission lines are selected by alternating current conduction to each diode. Off-diodes are biased at -10V for high isolation.

FIG. 20 shows a digital control circuit for the variable power T / R module. The input data includes a frequency (3 bits), a phase (6 bits), a transmission amplitude (5 bits), and a reception amplitude (6 bits). These data words are latched in input data latches L1-L4 on the rising edge of input data strobe IDSTB. At this time, the thermistor 2001 that senses the analog-digital converted temperature data (3 bits) is also latched. The input data strobe has other timing and control (TRS, TSTB, RST
B) and activate the electrically erasable programmable read only memory (EEPROM) and initiate standby mode control.

EEPROM P1 (701) performs the necessary phase correction during the transmit and receive modes. Phase correction during transmission mode is amplitude dependent, while phase correction during reception mode is zero. This EE
The contents of PROM P1 are appended to the received phase. Transmit and receive phase and amplitude command data is obtained from EEPROM R5. This EEPROM is addressed by a 3-bit frequency, a 3-bit temperature, and a 6-bit phase. EE
PROMs P2 and P4 provide amplitude correction data for the transmission and reception modes of operation, respectively. These data are stored in EEPROM
Adder A added to the amplitude data provided by P5
2 (727) is 6-bit amplitude data and 1-bit 10dB
Step gain control is performed. EEPROM P3 (703) includes pre-driver gain, driver gain, output path selection (+ 5V), and FE
Perform T voltage selection (+ 10V).

The transmit and receive T / R module instructions are stored in output latches L5 and L6, respectively. The final output consists of:

a) 5-bit digital phase b) 4-bit analog phase (after digital-analog conversion) c) 6-bit analog amplitude (after digital-analog conversion) d) 1-bit 10dB staircase control e) 6-bit analog amplitude (After digital-analog conversion) f) 1-bit pre-driver gain control g) 1-bit drive gain control h) 3-bit output path selection i) 2-bit FET + 5V and + 10V selection Provide phase and amplitude accuracy Using GaAs processing with excellent uniformity to track by the T / R module, and simple open loop error correction in the module assisted by an external online closed loop error correction system that automatically aligns the array is important.

The T / R module allows for both phase and amplitude open and closed loop corrections. Open loop correction compensates for phase shift and amplitude errors for all phase states of the phase shifter, and also compensates for changes over the operating bandwidth and operating temperature range. The module gain and phase are all pre-calibrated to provide receive and transmit gain within ± 0.5 dB and phase within ± 5 ° of reference.

The use of GaAs chips with a highly uniform phase and amplitude gradient with respect to temperature and frequency is an important factor when the initial phase and amplitude gradient errors match the tracking targets between devices after being calibrated by the PROM. An accurate voltage regulator in the module minimizes errors due to input voltage fluctuations.

This accurate open loop phase and gain tracking method makes the T / R module structure independent. That is, the module operates in an antenna configuration that does not provide space.
However, unique space-fed antennas are well suited for closed-loop monitoring and calibration to eliminate residual phase and amplitude errors.

Closed loop correction can be input to the module during service to compensate for long term drift to achieve and maintain low sidelobe performance for extended periods of time under changing environmental conditions.

FIG. 21 is a block diagram of the amplitude and phase correction method of the T / R module. Phase correction is performed by the phase shifter 21
Generated within ± 10 ゜ by analog phase bits using 01 while gain is analog programmable attenuator
It is corrected in steps of ± 0.2 dB by 2103.

The input to the compensator is a 13-bit phase code 2105 and 4
It comprises a bit amplitude correction term 2107. The former consists of an 8-bit phase shift setting, a 2-bit frequency setting, and a 2-bit temperature setting for both transmission and reception modes. The 8192 × 8 EEPROM 2109 contains a total of 256 phase states for four frequencies, four temperatures, and both receive and transmit modes. The output line of the EEPROM 2109 is divided into a 4-bit phase correction 2111 (1.25 ° resolution) and a 4-bit amplitude correction 2113 (0.25 dB resolution). EEPROM 2109 contains all open loop correction terms entered during module calibration. Tracking between modules is improved because the temperature correction adjusts the phase and amplitude to correspond to the average temperature sensitivity gradient. The frequency input adjusts for in-band amplitude and phase ripple. Temperature sensors are located on each module controller board.

Referring to FIG. 22, in receive calibration closed loop mode, the calibration switch 2201 at the indicated position causes the array
One “special” element in 2203 is addressed for calibration (at a given time), while all other “non-specific” elements are above, ie, all non-specific element voltages are off at the gate. The switch is set to a transmit mode position or some special high isolation position. The signals generated by the calibration horn 2205 and entering the four dipoles pass through the same module as the receiving module for a particular element, while the signal is rejected at all other elements.

Transmit calibration closed loop mode is an off-line mode used to align antenna beams in transmit mode. Here, one unique element of array 2203 is set to transmit mode, amplifier 2287 is gated on, and
On the other hand, all other elements are maintained in the command mode. This method continues until each element is aligned. Alignment during transmission is less necessary because the effect of gain and sidelobe tolerances is less on the transmit beam than on the receive beam. This mode is mainly used as an inspection during initial installation.

Following the beam control command before transmission, calibration is performed on the previously specified unique elements. This element is maintained in receive mode to receive a signal initiated from pilot pulse calibration horn 2205. All remaining elements are switched to the highest isolated position (transmit mode or special off setting). Calibration involves measuring the downlink signal passing through the module. Here, the phase and amplitude response characteristics of a particular element, ie, an element in a particular phase and gain state, are compared to pre-stored calibration values (ideal amplitude and phase values or data based on antenna test distance measurements). You. The radar controller reduces the calibration data after all modules have completed the cycle. The actual update correction of each element occurs during the next alignment cycle on a closed loop basis.

Having thus described the principles of the invention, those skilled in the art will appreciate modifications that adapt to a particular situation without departing from the principles of the invention. It is intended that the appended claims cover such modifications as well as those described above and be limited only by the true scope of the invention.

Continuation of the front page (56) References JP-A-60-147668 (JP, A) JP-A-62-177467 (JP, A) JP-A-3-31785 (JP, A) JP-A-4-116486 (JP) , A) Japanese Utility Model 63-132376 (JP, U) Japanese Utility Model 64-64413 (JP, U) Japanese Utility Model 1-152279 (JP, U) Japanese Utility Model 2-79481 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G01S ⁷ /00-7/42 G01S 13/00-13/95 H01Q 3/26

Claims (17)

(57) [Claims] 1. In a phased array radar system in which microwave power is amplified separately for each antenna aperture, rather than split from a common source, a transmit and receive module included in each aperture channel comprises: Sets of terminals of the T / R switching means, a phase shifter, a programmable attenuator, a buffer amplifier, a second set of terminals of the T / R switching means, and a power output amplifier. And a means for connecting the circulator to the antenna aperture in series between the transmitter input terminal and the circulator at the transmission position of the second set of T / R switching means; and connecting the circulator to ground at the transmission position. Terminals of a third set of T / R switching means connected between the terminals; and terminals of the third set of T / R switching means; A low noise amplifier, a second position of a terminal of the first set of T / R switching means, the phase shifter, the programmable attenuator, the buffer amplifier, and the second set of T / R switching means. A second position of a terminal of the T / R switching means is connected in series between the antenna aperture and a receiver output terminal at a receiving position of the switching means; and a phase, frequency, temperature, and amplitude correction input. The phase shift of both the closed-loop digital phase correction factor and the closed-loop analog phase correction factor to correct both transmit and receive signals for short-term changes in phase state, attenuation range, frequency, and temperature using A transmitter-receiver module for providing a closed loop correction factor to the programmable attenuator. Le. 2. The transmission of claim 1 wherein the EEPROM uses an open loop correction means in the controller and the EEPROM stores all open loop correction terms entered during module calibration for long term corrections. A receiving module. 3. The terminal of said first set of T / R switching means is a double pole double throw switch which connects said transmitter input terminal to an input of said phase shifting device in a transmitting position and a receiving position. 3. The transmission according to claim 1, wherein an output of the low noise amplifier is connected to an input of the phase shifter, and an output of the buffer amplifier is connected to a transmitter input terminal functioning as a receiver output terminal at a reception position. A receiving module. 4. The programmable attenuator comprises an analog attenuator for receiving analog correction information from the control device and a digital attenuator for receiving digital correction information from the control device connected in series therewith. The transmission-reception module according to claim 3, wherein the transmission-reception module is configured. 5. The power output amplifier comprises a pre-drive amplifier, a drive amplifier, and a power amplifier, which are connected to terminals connected when transmitting the second set of T / R switching means. Four sets of switching means connected in series to the circulator through the terminals of the circulator, the fourth switching means being a single-pole, three-throw switch, a fixed terminal connected to the circulator and the pre-drive amplifier, An amplifier, and three movable terminals respectively connected to each output of the power amplifier, directly connected to the output of the power amplifier, and connections to the drive amplifier and the pre-drive amplifier are provided with additional unipolar twins. EEPROM of the control device, which is performed through a throw switch and switches the additional single pole double throw switch and the fourth switching means.
And switching the power amplifier or the power amplifier and the drive amplifier out of series if not necessary to reduce the power consumption and temperature caused by the multiple T / R modules used. The transmitting-receiving module as described. 6. The pre-amplifier, a drive amplifier,
And the power amplifier bias connection, while 2
A controller switch connected to one or more different power levels, and further comprising varying the bias of said bias connection to reduce bias when power consumption and temperature can be reduced again. 6. The transmission-reception module according to claim 5, further comprising means provided in said control device for switching said control device switch. 7. The transmission-reception module according to claim 5, wherein said pre-drive amplifier, drive amplifier, and power amplifier are further operated in class B to increase efficiency and reduce temperature. 8. The transmit-receive module according to claim 7, wherein said pre-drive amplifier, drive amplifier, and power amplifier are configured by a multi-function self-aligned gating method to further increase efficiency and reduce temperature. . 9. The multi-function self-aligned gate method for further increasing efficiency and decreasing temperature, wherein said T / R switching means, said phase shifter, said analog attenuator, said digital attenuator and said buffer amplifier are further increased. The transmission-reception module according to claim 7, wherein the transmission-reception module comprises: 10. The transmit-receive module according to claim 1, wherein said power output amplifier is further operated in class B to increase efficiency and decrease temperature. 11. The transmit-receive module according to claim 10, wherein said power output amplifier is configured by a multi-function self-aligned gate method to further increase efficiency and decrease temperature. 12. The T / R switching means, the phase shifter, the programmable attenuator, and the buffer amplifier are configured by a multi-function self-aligned gate method to further increase efficiency and reduce temperature. 11. The transmission-reception module according to claim 10, wherein: 13. An amplifier comprising a plurality of amplifiers connected in series, each having a bias connection, and selectively switching one or more of the plurality of amplifiers out of the series connection when not necessary. An amplifier comprising means and switching means connected between a power supply and said bias connection for reducing bias to reduce power consumption and temperature. 14. The amplifier of claim 13, wherein said pre-drive amplifier, drive amplifier, and power amplifier are operated in Class B to further increase efficiency and reduce temperature. 15. A drive amplifier, a drive amplifier, and a power amplifier connected in series, wherein the power amplifier alone or the drive amplifier and the power amplifier are excluded from the series connection when unnecessary. Means for switching, a bias connection of the pre-driver, driver and power amplifier, and a switching connected between a power supply and the bias connection to reduce bias to reduce power consumption and temperature. And an amplifier. 16. The amplifier of claim 15, wherein said pre-drive amplifier, drive amplifier, and power amplifier are further operated in Class B to increase efficiency and reduce temperature. 17. The amplifier of claim 14, wherein said pre-drive amplifier, drive amplifier, and power amplifier are configured by a multi-function self-aligned gate method to further increase efficiency and reduce temperature.