JP3017644B2 - Display synchronization signal generator in image decoding apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display synchronizing signal generator in an image decoding apparatus for properly displaying decoded image data.

[0002]

2. Description of the Related Art When transmitting or storing digitally expressed image data, encoding is performed to reduce the amount of data. As a coding method, there is a method of reducing redundancy by utilizing temporal or spatial correlation of image information.

As a method utilizing the temporal correlation, there are methods of encoding a difference between two consecutive screens (frames) and detecting motion of an image to perform motion compensation.
As a method utilizing spatial correlation, an image is divided into blocks of a predetermined size (for example, 8 pixels each in the vertical and horizontal directions), data in the blocks are subjected to orthogonal transform, and transform coefficients are scan-converted. Some (for example, rearrange from low-frequency components to high-frequency components) and perform variable-length codes. An image coding method (hereinafter, abbreviated as MPEG2), which is being standardized by the Moving Picture Experts Group (MPEG), uses the above two methods in combination.
MPEG2 tentative recommendation is Generic Cordingof Moving Pic
ISO / IEC13818-2 entitled tures and Associated Audio
It is described in.

FIG. 4 shows an example of the configuration of an image decoding apparatus for decoding data encoded by such a method. In FIG. 4, reference numeral 10 denotes a memory storage unit, which comprises a buffer memory control unit 11 and a buffer memory 12. Decoding means 20 comprises a variable length decoder 21, a scan converter 22, an inverse quantizer 23, an inverse DCT unit 24, a motion compensated image reproducing unit 25, and a prediction frame memory 26. 40 indicates prediction data, 41 indicates decoded data, and 42 indicates display data. Further, reference numeral 100 denotes an input bit stream representing an encoded image, and 200 denotes decoded image data.

Next, the operation will be described.

The input bit stream 100 is stored in the buffer memory 12 under the control of the buffer memory controller 11. The data read from the buffer memory 12 is subjected to variable length decoding by the variable length decoder 21.

Although not all data are variable-length coded, fixed-length codes are also decoded by the variable-length decoder 21. Next, after the scan converter 22 rearranges the order of the data, the data is inversely quantized by the inverse quantizer 23. Next, the inverse DCT unit 24 performs an inverse discrete cosine transform. When the inter-frame difference is received, the motion-compensated image reproducing unit 25 reads the prediction data 40 from the prediction frame memory 26, adds the data to the reception data from the inverse DCT unit 24 , and then stores the decoded data 41 in the prediction frame memory 26. Write. When data encoded in the frame is received, the received data is written to the prediction frame memory 26 as it is. As described above, the decoded image data 2
00 is reproduced.

In the forward (one-sided) prediction, a frame temporally later (here, a P frame) is predicted from a previous frame (here, an I frame). Therefore, to reproduce the P frame, the prediction data 40 of the I frame that has been decoded in advance is used.
Must be read. Prediction data 40 and inverse DCT unit 2
The P frame is reproduced by the prediction error which is the output of 4,
The decoded data 41 is written to the prediction frame memory 26. Further, the written data is read out as the display data 42 and output as the decoded image data 200 from the motion compensation image reproducing unit 25.

The above-described conventional image decoding apparatus receives an input bit stream 100 representing an encoded image and decodes the input bit stream 100 to decode the image.
From the time when the value indicating the decoding start time is read, the time at which the decoded image is displayed is determined from the time when the value indicating the decoding start time is read, and the display synchronization signal and the decoded image data 200 are displayed from the time. Output to the device and display the decoded image.

[0010]

Generally, it takes about several frames to pull in a synchronization signal in a display device. For this reason, the conventional method of outputting a synchronization signal in accordance with the output of a display image does not perform good image display during a period in which synchronization is drawn.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a decoded image display in a device which inputs an input bit stream representing an encoded image and decodes the image, and provides a good display image at the start of display. .

[0012]

A display synchronizing signal generator in an image decoding apparatus according to the present invention reads a value indicating a decoding start time present in a header portion in an input bit stream, and reads a subsequent image bit. A decoding start time calculation unit that calculates a time at which decoding is started from a time at which writing of the stream to the buffer is started; a display start time calculation unit that calculates a display start time from the decoding start time ; Write buffer
At the start of decoding, which is the time from the start time to the decoding start time
The interval is d / S [seconds], and the display start time is from the decryption start time.
The display start time difference, which is the time until
Let the clock be F [H _Z ] and satisfy the following equation:
From the start time of buffer writing of image bit stream
Synchronization signal output start time r, which is the time until the generation of the synchronization signal
/ S [seconds] is calculated, and the synchronization signal represented by r in the following equation is calculated.
And a synchronization signal generation time calculation unit that outputs a signal output start instruction value to the synchronization signal generation unit . d / S + t = m / F + r / S (where S = constant 0 ≦ r / S <1 / F m = 0,
1,2, ...)

[0013]

Before the decoded image is output to the display device, the display device outputs the synchronization signal with a margin longer than the time for drawing the synchronization signal. Therefore, when displaying the decoded image, a good display screen can be obtained even at the beginning of the display.

[0014]

DETAILED DESCRIPTION FIG. 1 shows an example configuration of a synchronizing signal generating apparatus according to the present invention, it is shown to block diagram of one embodiment. 1 is a header analysis unit for detecting a decoding start time instruction value and generating an image bit stream write start signal, 2 is a decoding start time calculation unit, 3 is a display start time calculation unit, 4 is a synchronization signal generation time calculation unit, 5 Is a synchronization signal generator, 6 is a display unit, 7 is an image bit stream buffer, 8 is a display data buffer, 9
Denotes a display device, and 20 denotes a decoding unit, which corresponds to the decoding unit shown in FIG. Also, 100 is an input bit stream, 10
1, 102 is an image bit stream, 200, 201,
202 is decoded image data, 300 is an image bit stream write start signal, 301 is a decoding start signal, 302 is a display start signal, 303 is a synchronization signal, 400 is a decoding start instruction value, 401 is a decoding start time, and 402 is a display start time difference. t, 403 is a synchronization signal output start instruction value, 500 decoding start instruction clock, 501 indicates a frame clock.

Next, the operation will be described with reference to FIG. 2 showing the time calculated by each processing unit.

The header analyzer 1 detects a decoding start instruction value (d) 400 counted in the decoding start instruction clock (S [Hz]) 500, which is present in the header of the input bit stream 100, Output to the decoding start time calculation unit 2.

Further, after the header analysis, the image bit stream 101 in the input bit stream 100 is sent to the image bit stream buffer 7 as an image bit stream write start signal 300 indicating that writing to the image bit stream buffer 7 has started.
To the decoding start time calculation unit 2 and the synchronization signal generation unit 5.

Further, a decoding start time (d / S [sec]) 40
1 is output to the synchronization signal occurrence time calculation unit 4.

The decoding means 20 reads the image bit stream 102 from the image bit stream buffer 7 in response to the decoding start signal 301, and starts decoding.

Further, the decoded image data 200 is written into the display data buffer 8.

The display start time calculation unit 3 calculates a display start time difference (this is set to t [seconds]) from the decoding start time to the display start time, which is known in advance, based on the decoding start signal 301.
After 02, a display start signal 302 is output to the display unit 6.

Further, the display start time difference (t [sec]) 4
02 to the synchronization signal occurrence time calculation unit 4.

The synchronization signal generation time calculation unit 4 calculates a decoding start time (d / S [sec]) 401 and a display start time difference (t
[Second]) 402 and a frame clock (F [Hz]) 501, a synchronization signal output start instruction value (r) 403 indicated by r in the following [Equation 1] is calculated. Is output to the synchronization signal generator 5.

[0024]

D / S + t = m / F + r / S where m = 0, 1, 2,... 0 ≦ r / S <1 / F In the synchronization signal generator 5, the counter is controlled by the image bit stream write start signal 300. It starts, counts up with a decoding start instruction clock (S [Hz]) 500 , and outputs a synchronization signal 303 to the display device 9 at a time coincident with the synchronization signal output start instruction value (r) 403.

The display section 6 outputs the decoded image data 202 from the display data buffer 8 to the display device 9 in accordance with the display start signal 302.

The input bit stream 100 is assumed to be a bit stream related to video. However, if a bit stream of the system, which is obtained by adding another bit stream related to audio and the like, is assumed as an input bit stream, the header In the part, a decoding time instruction value (DTS) corresponding to the decoding start instruction value (d) 400, the decoding start time (d / S) 40
1 plus the display start time difference (t) 402 is used as the decoding start instruction clock (S [Hz]) 500
Display time indication value (PTS
To exist). A similar effect can be obtained by using the decoding time indication value (DTS) and the display time indication value (PTS).

As a specific embodiment, FIG. 3 shows a decoding start instruction value (d) = 35000 decoding start instruction clock (S [Hz]) = 90000 [H]
z] The time calculated by each processing unit when the display start time difference (t [sec]) = 1/30 [sec] and the frame clock (F [Hz]) = 30 [Hz] is shown. In this embodiment, the timing of the decoding start time coincides with the timing of the synchronization signal . According to the above equation (Equation 1), m = 1
2, r = 2000, and the input bit stream 100
1/45 seconds after the writing of the middle image bit stream 101 into the image bit stream buffer 7 starts outputting a synchronization signal 303 to the display device 9,
After outputting the synchronization signal 303, the decoding starts 11/30 seconds later, and the display starts 1/30 seconds after the decoding starts.

[0028]

As described in detail above, the present invention reads the value indicating the decoding start time existing in the header portion of the input bit stream, and starts writing the subsequent image bit stream to the buffer. A decoding start time calculation unit for calculating a time at which decoding is started from a display start time calculation unit for calculating a display start time from the decoding start time; and a buffer for the image bit stream.
Recovery time that is the time from the write start time to the decryption start time
The signal start time is set to d / S [seconds] and displayed from the decoding start time
The display start time difference, which is the time until the start time, is represented by t [seconds].
And the frame clock is set to F [H _Z ], and the following equation is satisfied.
Start writing the image bitstream buffer
Synchronization signal output opening, which is the time from the time to the generation of the synchronization signal
The start time r / S [seconds] is calculated, and is represented by r in the following equation.
And a synchronization signal generation time calculation unit that outputs a synchronization signal output start instruction value to the synchronization signal generation unit, so that a decoded image is displayed after the generation of the synchronization signal, so that good display can be performed at the start of display. Images can be obtained. d / S + t = m / F + r / S (where S = constant 0 ≦ r / S <1 / F m = 0,
1,2, ...)

[0029]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a display synchronization signal generator according to the present invention and a relationship between image data decoding means and a display device.

FIG. 2 is a diagram illustrating times calculated by respective processing units in the embodiment of FIG. 1;

FIG. 3 is a diagram showing a time determined by each processing unit in the specific numerical example of FIG. 2;

FIG. 4 is a block diagram illustrating a configuration example of an image decoding device to which the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Header analysis part 2 Decoding start time calculation part 3 Display start time calculation part 4 Synchronization signal generation time calculation part 5 Synchronization signal generation part 6 Display part 7 Image bit stream buffer 8 Display data buffer 9 Display device 100 Input bit stream 101 Image bit stream 102 video bit stream 200 the decoded image data 201 decoded image data 202 decoded image data 300 video bit stream writing start signal 301 backward GoHiraki start signal 302 display start signal 303 synchronizing signal 400 decoding start instruction value 401 decoding start time 402 display start time Difference 403 Synchronization signal output start instruction value 500 Decoding start instruction clock 501 Frame clock

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 7/24 G09G 5/00 555A (72) Inventor Yutaka Okada 4-36-19 Yoyogi, Shibuya-ku, Tokyo Graphics Co., Ltd.・ Communication Laboratories (72) Inventor Yoshikazu Kawamura 4-36-19 Yoyogi, Shibuya-ku, Tokyo Co., Ltd.Graphics Communication Laboratories Co., Ltd. (72) Inventor Shigeru Komatsu Shibuya, Tokyo 4-36-19, Yoyogi-ku, Tokyo Graphics Communications Laboratories Inc. (72) Inventor Norihiko Nagai 4-36-19, Yoyogi, Shibuya-ku, Tokyo Graphics Communications Co., Ltd.・ Laboratories (72) Inventor Tomoyuki Shindo 4 Yoyogi, Shibuya-ku, Tokyo No. 36-19 Inside Graphics Communication Laboratories, Inc. (56) References JP-A-61-156937 (JP, A) JP-A-1-89783 (JP, A) JP-A-6-196 133234 (JP, A) JP-A-7-7730 (JP, A) JP-A-7-327032 (JP, A) JP-A 8-65292 (JP, A) JP-A 8-65664 (JP, A) JP-A-8-102894 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/04-5/12 H04N 7/24-7/68 H04N 5/38-5 / 46 G09G 5/18 G09G 5/00

Claims (1)

(57) [Claims] 1. An input bit stream representing an encoded image is inputted, and a display synchronization signal generating device in an image decoding device for decoding an image decodes a decoding start time present in a header portion of the input bit stream. A decoding start time calculating unit that calculates a time at which decoding is started from a time at which reading of a value indicating the following and writing of a subsequent image bit stream to the buffer, and a display that calculates a display start time from the decoding start time The start time calculator and the decoding start time, which is the time from the buffer writing start time of the image bit stream to the decoding start time, is d / S [seconds], and the display start, which is the time from the decoding start time to the display start time. An image bit stream that satisfies the following equation, with a time difference of t [seconds] and a frame clock of F [Hz]. Synchronization signal output start time r / which is the time from the buffer write start time to the generation of the synchronization signal.
A synchronization signal generation time calculation unit that calculates S [seconds] and outputs a synchronization signal output start instruction value indicated by r in the following equation to the synchronization signal generation unit. Display synchronization signal generator. d / S + t = m / F + r / S (where S = constant 0 ≦ r / S <1 / F m = 0,
1,2, ...)