JP3014619B2 - Asynchronous transfer mode communication system, cell disassembly apparatus therefor, and asynchronous transfer mode communication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous transfer mode communication system, a cell decomposer, and an asynchronous transfer mode communication system, for example, an asynchronous transfer mode such as B-ISDN (Broadband Integrated Services Digital Network) or LAN connection communication. The present invention relates to an asynchronous transfer mode communication system and a cell decomposer suitable for use in a network, and an asynchronous transfer mode communication system.

[0002]

2. Description of the Related Art In recent years, with the digitization and integration of communication networks, B-ISDNs capable of transmitting various media information including voice, data, and images have been put into practical use. this
As one means for realizing B-ISDN, for example, an ATM (Asynchronous Transfer Mode) communication method is known. ATM communication method is
In this system, various types of media information are divided into fixed-length cells called ATM cells, and exchange and transmission are performed in units of these cells. By employing this communication method, the network can be unified and a network independent of various media can be constructed.

For example, in a B-ISDN network, an ATM cell is obtained by dividing information from a terminal into 48-byte information fields, and adding a 5-byte header to each of the information fields at a node including an exchange. The cells are sequentially switched and transferred as a fixed-length cell by hardware. The header is
A virtual path identifier (VPI) that identifies a virtual path (VP) set between terminals according to the information capacity, and a virtual channel (VC) that is set for each terminal of information as multiple lines in the virtual path
Channel identifier (VCI), which identifies the type of information field, payload type (PT), which indicates the type of information field, cell loss priority indication (CLP), which indicates cell priority, and header error and cell synchronization Header error control code (HE
C).

In this case, the virtual path identifier VPI is assigned 8 bits (256 patterns) from the terminal and 12 bits in the network, and can correspond to a maximum of 4096 virtual paths. Sixteen bits are allocated to the virtual channel identifier VCI so that it can support up to 65536 different lines.
As a result, each node separates the header from the arriving ATM cell and analyzes its normality over all bits. If it is normal, the ATM switch is passed through the ATM cell, and the ATM switch performs hardware routing processing to switch to a desired virtual path and virtual channel. The switched cell is added with a header according to the routing processing at the next node or the virtual path and the terminal node of the virtual channel, and is sent out to each line. ATM cells are sequentially transferred to a desired destination.

[0005]

However, in the above-mentioned conventional technique, the routing bits are formed by using all the bits of the virtual path identifier VPI and the virtual channel identifier VCI assigned at each node. Therefore, there is a problem that the determination becomes complicated and it takes time for the routing processing unit such as the ATM switch to identify the virtual path VP and the virtual channel VC. Specifically, for example, in B-ISDN, a transmission path connecting each node has a capacity of 2.4 to 10 Gbps. When a virtual path VP of 24 to 100 Mbps is assigned to this, about 10 virtual paths are set in each node. When these are connected to a plurality of nodes, for example, 10 nodes, about 100 virtual paths are set. Therefore, in practice, a 7-bit virtual path
The use of identifiers on the order of bits is sufficient. Similarly, the virtual channel identifier can be sufficiently identified with about 10 bits out of 16 bits. Further, when a specific service is set in advance, cell transfer can be performed by using only a few bits of a virtual path identifier and a virtual channel identifier. In this way, in practice, the routing bits to be determined by the node need to be assigned with fewer bits than the routing bits to be set, and the redundancy of processing such as identifying all the routing bits at the receiving node is sufficient. there were. Similarly, in corporate communications
In the case of using ATM communication, the number of routing bits used is smaller than that of communication in a public network, and it is necessary to devise a method of removing redundancy at the time of identification on the receiving side.

The present invention solves the above problems and simplifies identification of routing bits used in a receiving node.
It is an object of the present invention to provide an asynchronous transfer mode communication system, a cell disassembly apparatus, and an asynchronous transfer mode communication method capable of performing the determination at a high speed.

[0007]

In order to solve the above-mentioned problems, an asynchronous transfer mode communication system according to the present invention assembles information into cells having a fixed bit length, and divides the fixed-length cells between respective nodes into an information amount. In an asynchronous transfer mode communication system for transferring data via a virtual path and a virtual channel set according to a route, a fixed length is added to a header of a cell by adding a routing bit including a virtual path identifier and a virtual channel identifier having a fixed bit length. Cell assembling means for assembling a cell, header separating means for separating a header from a fixed-length cell received from another node and analyzing its routing bit, and routing means for performing a cell routing process based on the routing bit. The header separating means includes a virtual path identifier among the separated headers. And first storage means for sequentially storing routing bits including the virtual channel identifier and a virtual channel identifier, and second storage means for storing preset check bits for confirming the normality of the routing bits stored in the first storage means. Storage means, and comparison means for sequentially comparing the routing bits from the first storage means and the check bits from the second storage means, wherein the comparison means is one of the routing bits from the first storage means. A plurality of bits of a virtual path identifier and a virtual channel identifier that are not used in the own node are compared with the check bits, and a match or mismatch is detected.If the result of the comparing means does not match, the fixed-length cell is discarded. If they match, the routing means routes based on the used bits of the virtual path identifier and virtual channel identifier. And performing management.

In this case, the bits used for the virtual path identifier and the virtual channel identifier at each node are successively arranged in the upper or lower bits of the routing bit at the transmitting node and transmitted, and the comparing means is the first means. When comparing the routing bits from the storage means with the check bits from the second storage means, the lower or upper bits of the routing bits and the check bits excluding the use bits of the virtual path identifier and the virtual channel identifier at the node It is advantageous to check the normality of the routing bits by comparing

Further, the bits used for the virtual path identifier and the virtual channel identifier at each node are arranged and transmitted at predetermined bit positions of the routing bits at the transmitting node, and the comparing means reads from the first storage means. When comparing the routing bits of the first storage means with the check bits from the second storage means, the bits of the virtual path identifier and the virtual channel identifier which are not used in the node among the routing bits from the first storage means are determined from predetermined positions. The check bit may be extracted and compared with the extracted unused virtual path identifier and virtual channel identifier.

Further, the bits used for the virtual path identifier and the virtual channel identifier at each node are transmitted to the transmitting node by distributing them to arbitrary bit positions and arbitrary bit widths of the routing bits, and the receiving system is transmitted to the transmitting node. , Of the routing bits from the first storage means,
Advantageously, the comparing means includes masking means for masking the bit positions and bit widths of the virtual path identifier and the virtual channel identifier used at the node, wherein the comparing means compares the routing bits masked by the masking means with the check bits. .

On the other hand, the cell disassembly apparatus according to the present invention separates a header from a fixed-length cell received from another node and analyzes a routing bit thereof. First storage means for sequentially storing routing bits including a channel identifier, and second storage means for storing preset check bits for confirming the normality of the routing bits stored in the first storage means When,
A comparison unit for sequentially comparing routing bits from the first storage unit with check bits from the second storage unit;

In this case, when comparing the routing bit from the first storage means with the check bit from the second storage means, the comparing means compares the routing bit with the lower or upper bit of the routing bit at the transmitting node. It is preferable to check the normality of the routing bits by comparing unused bits and check bits of the virtual path identifier and the virtual channel identifier arranged consecutively.

The cell disassembly device may further include, among the routing bits from the first storage unit, unused bits of a virtual path identifier and a virtual channel identifier which are arranged at predetermined bit positions of the routing bits at the transmitting node. May be sent to the comparing means, and the comparing means may compare unused bits of the extracted virtual path identifier and virtual channel identifier with check bits from the second storage means.

Further, the cell disassembly device masks the virtual path identifier and the use bit of the virtual channel identifier which are distributed and transmitted to an arbitrary bit position and an arbitrary bit width of the routing bit at the transmitting node. And the comparing means advantageously compares the routing bits masked by the masking means with the check bits from the second storage means.

On the other hand, in the asynchronous transfer mode communication system according to the present invention, the information is assembled into cells having a fixed bit length, and these fixed length cells are set between the respective nodes according to the amount of information and the route. In the asynchronous transfer mode communication method in which data is transferred via a virtual channel, the number of bits of a virtual path identifier and a virtual channel identifier actually used at the time of routing with respect to a set virtual path and a virtual channel at each node. The first step of setting the number of unused bits in advance and transmitting the unused bits with a predetermined bit value, and at each node receiving the fixed-length cell,
A second step of setting the same number of check bits as the unused virtual path identifier and the virtual channel identifier, and separating and storing routing bits including the virtual path identifier and the virtual channel identifier from the received fixed-length cell header A virtual path identifier and a virtual channel identifier that are not used by the node among the routing bits stored in the third step,
4th comparison with the check bit set in the step
And discarding the fixed-length cell received when the result does not match, and routing the fixed-length cell based on the virtual path identifier and the virtual channel identifier used by the node when the result matches. And a step.

In this case, in the first step, the virtual path identifier and the virtual channel identifier to be used are successively arranged in the upper or lower bits of the routing bit and transmitted, and the fourth step is in the node. It is preferable to check the normality of the routing bits by comparing the lower or upper bits of the routing bits except the used bits of the virtual path identifier and the virtual channel identifier with the check bits.

In the first step, the virtual path identifier and the virtual channel identifier to be used are arranged at arbitrary bit positions of the routing bits and transmitted, and the receiving node is separated in the third step. The step of extracting the virtual path identifier and the virtual channel identifier that are not used in the node among the routing bits may be compared with the extracted bit and the check bit in the fourth step.

In the first step, the virtual path identifier and the virtual channel identifier to be used are distributed to arbitrary bit positions and arbitrary bit widths of the routing bits and transmitted. Masking the allocated bits of the virtual path identifier and the virtual channel identifier used in the node, wherein the fourth step compares the masked routing bit with the check bit. Is also good.

[0019]

According to the asynchronous transfer mode communication system and the asynchronous transfer mode communication method of the present invention, each node actually uses a virtual path and a virtual channel set in accordance with information at the time of routing. By setting in advance the number of bits of the virtual path identifier and the virtual channel identifier and the number of unused bits,
Unused bits are given a predetermined bit value and transmitted sequentially. The receiving node sets the same number of check bits as the virtual path identifier and the virtual channel identifier that are not used in the second storage means, and sets the virtual path identifier and the virtual channel identifier in the header of the received fixed-length cell. And sequentially separate the routing bits including
, And sequentially read out by the comparing means, and compare with the check bits set in the second storing means to detect the coincidence or non-coincidence. By this means, if the result does not match, the fixed-length cell received assuming that the routing bit is invalid is discarded, and if the respective bits match, the virtual path identifier and virtual channel identifier of fewer bits used by the node are replaced. Extract
Based on this, each fixed-length cell is routed at high speed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an asynchronous transfer mode communication system, a cell decomposing device and an asynchronous transfer mode communication system according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a cell disassembly device to which an asynchronous transfer mode communication method according to the present invention is applied.
FIG. 2 shows an embodiment of an asynchronous transfer mode communication system to which the cell disassembly device shown in FIG. 1 is applied. In these drawings, only parts directly related to the present embodiment are shown, and parts not directly related to the present embodiment, such as a subscriber unit and a control unit, are not shown. .

The asynchronous transfer mode communication system according to the present embodiment is effectively applied between nodes 10 and 20 of an asynchronous transfer mode network such as B-ISDN (Broadband Integrated Services Digital Network). This is a communication system that effectively checks the header of fixed-length ATM cells transferred over the network at 20 and speeds up the ATM cell routing process.

Each of the nodes 10 and 20 is connected to a virtual path VP of a predetermined capacity set on a physical transmission line as shown in FIG. Routing devices NA to NN that transfer ATM cells to respective routes via virtual channels VC. Such routing devices NA to NN include an ATM switch such as a subscriber line switch or a trunk line switch, or a virtual path handler VPH and a virtual channel handler VCH or a plurality of virtual channel handlers interposed between the ATM switch and an optical fiber transmission line. The present invention can be applied to a cell transfer device such as a cross-connect switch CNS provided at a point where the transmission lines intersect with each other, which is appropriately arranged according to the configuration of the network.

The data is transferred between such nodes 10 and 20.
The ATM cell has a 5-byte ATM header as shown in Fig. 4.
This is information formed into a fixed length of 53 bytes including 500 and a payload section 600 of 48 bytes. The header section 500 includes a routing bit 502 including a virtual path identifier VPI and a virtual channel identifier VCI, and a payload type (PT) 504.
, Cell loss priority indication (CLP) 506, and header error control code
(HEC) 508. The payload section 600 is user information obtained by adding 1-byte user header to information obtained by dividing information from a terminal into 47 bytes.

In the header section 500, the routing bit 50
The virtual path identifier VPI of No. 2 is a 12-bit code for identifying a virtual path VP set between terminals according to the capacity of information. The virtual channel identifier VCI is a 16-bit code for identifying a virtual channel VC set for each information base as a multiplexed channel in the virtual path VP. In the present embodiment, the number of significant bits that are substantially used and the number of invalid bits that are not used in each of the nodes 10 and 20 are set in advance, and the valid bits are continuously arranged in the upper bits of the routing bits 502. To send. The invalid bit is compared with a check bit preset for each node 10, 20, as described below, to verify the validity of the routing bit 502.

The payload type 504 is a 3-bit code representing the type of the information field 600 such as user information or control information. The cell loss type priority indication 506 is a 1-bit code indicating the priority of each cell. When a value "1" is set in this cell, the cell has a low priority, and when "0" is set, it indicates a priority cell. The header error control code (HEC) 508 is a 1-byte code used for error detection and cell synchronization of the 4-byte header.

Returning to FIG. 2, the details of the nodes 10 and 20 of this embodiment will be described.
, An ATM switch 200, and an ATM cell assembling unit 300. The ATM cell decomposing unit 100 is a header separation processing unit that separates the header unit 500 from ATM cells having a fixed bit length received from other nodes and analyzes the routing bits 502 including the virtual path identifier VPI and the virtual channel identifier VCI. In particular, in this embodiment, the normality of the routing bit 502 is confirmed by comparing the virtual path identifier VPI and the virtual channel identifier VCI which are not used in the respective nodes 10 and 20 with check bits having the same number of bits, and checking the normality of the ATM switch.
This is a header analyzer that transfers only normal ATM cells to 200. Specifically, the transmission path connecting the respective nodes 10 and 20 has, for example, a capacity of 2.4 to 10 Gbps in B-ISDN, and assigns a virtual path VP of 24 to 100 Mbps to this. About 10 virtual paths VP are assigned to each node 1
Set at 0,20. These have multiple nodes, for example
About 100 virtual paths when connected to 10 nodes
VP is set. Therefore, in practice, in each of the nodes 10, 20, an identifier of, for example, about 7 bits is substantially used for the 12-bit virtual path identifier VPI.
Similarly, the virtual channel identifier VCI is 9 to 16 out of 16 bits.
About 10 bits are substantially used. Thus, in the present embodiment, for example, the routing bit 50 is utilized by using an unused identifier of 8 to 12 bits of both identifiers VPI / VCI.
Check the health of 2.

More specifically, as shown in FIG. 1, a cell decomposing unit 100 includes a decomposing circuit 102 and a VPI / VCI buffer 104.
, A check bit buffer 106, and a comparison circuit 108. The decomposition circuit 102 converts the received ATM cell into routing bits 502 including a virtual path identifier VPI and a virtual channel identifier VCI, a payload type (PT) 504, a cell loss priority indication (CLP) 506, and a header error control code (H
EC) 508 and a header separation circuit that separates and outputs the data to the payload section 600. The header separation circuit includes, for example, a one-input multiple-output multiplexer that sequentially and selectively outputs according to the number of bits. Advantageously, since the cells are input in units of bytes, only the 1-byte header error control code 508 is separated from the header section 500, and the payload type 504 and the cell loss priority indication 506 are included in the routing bits 502. The output and the 48 byte payload section 600 may be output separately.

The VPI / VCI buffer 104 is a buffer for temporarily storing the routing bits 502 from the separation circuit 102, and has a capacity of 28 bits or more including 12 bits of the virtual path identifier VPI and 16 bits of the virtual channel identifier VCI. . Advantageously, it may have the capacity to store 32 bits of information, including payload type 504 and cell loss priority indication 506. In this case, although not shown, the ATM cell is sent to the main decomposition unit 100 in a state where the processing is performed through a circuit for establishing error correction and cell synchronization of the header unit 500 based on the header error control code 508. Is supplied.

The check bit buffer 106 has a VPI / VCI
This is a storage circuit in which check bits for confirming the normality of the routing bits 502 stored in the buffer 104 are stored in advance, and the number of bits of the virtual path identifier VPI and the virtual channel identifier VCI which are not used in the preset node. And has a capacity of 8 to 12 bits, for example. The storage of the check bits in the buffer 106 is inevitably determined by the capacity of the transmission path accommodated in the node, the number of virtual paths VP that can be set, and the number of virtual channels VC that can be set in this node. The number of bits is set in advance between the node and the node.
The transmitting node adds this to the actual number of bits used for transmission. At the receiving node, the data is stored in the buffer 106 in advance via the external interface.

The comparison circuit 108 includes a routing bit 502 from the VPI / VCI buffer 104 and a check bit buffer.
In this embodiment, the upper bits or lower bits in which the bits of the virtual path identifier VPI and the virtual channel identifier VCI which are not used in the routing node 502 are set are set. A few bits and a check bit are compared. If the comparison results match, only the valid bits used in the routing process as cell valid are separated by the separation circuit 10.
ATM switch 20 in addition to the payload separated in 2
Output to 0. If not, each cell is discarded.

Returning to FIG. 2, the ATM switch 200
A routing processing unit that receives a normal ATM cell checked by the M cell disassembly unit 100 and routes the ATM cell by hardware processing based on the routing bit 502, and includes a buffer type switch or a batcher-banyan switch. Alternatively, a self-routing type switch such as a barrel switch is effectively applied. In particular, in the present embodiment, the cells from the ATM cell decomposer 100 have extra bits as headers because the routing bits of only valid bits used in this node are added. The routing process is executed while determining at a higher speed than in the case.

The ATM cell assembling section 300 includes the ATM switch 200.
An output circuit that assembles the cells that have been subjected to the routing processing into cells of a fixed length of 53 bytes and outputs the cells to a predetermined route.
This is a header adding circuit that generates a 5-byte header section 500 for routing at the next node and adds it to the payload section 600. In the present embodiment, the virtual path identifier VP and the virtual channel identifier VC actually used in the next node
The valid bits of I and the invalid bits that are not used are placed in predetermined bits of the routing bit 502, and AT
The payload section 504 and the cell loss priority code 506 from the M cell decomposer 100 are added, and the header error control code 508 is added to generate the header section 500. in this case,
Of course, the invalid bit has the same number of bits as the check bit set in the next node, and the routing bit 50
Place them consecutively above or below the second.

In the above configuration, the asynchronous transfer mode communication method according to the present embodiment will be described together with the operation of the communication system and the cell disassembly apparatus. For example, when transferring an ATM cell from the node 10 to the node 20, first, in the receiving node 20, the same number of bits as the virtual path identifier VPI and the virtual channel identifier VCI not used by the own node are stored in the check bit buffer 106 in advance. For example, 8 to 12 check bits are set via an external interface.

In this state, the transmission side node 10
Routed to node 20 by switch 200
ATM cells are sequentially assembled in an ATM cell assembling section 300 and transferred to a transmission path. In this case, the number of bits and the number of unused bits of the virtual path identifier VPI and the virtual channel identifier VCI actually used in routing at the next node 20 are set in advance, and the unused bits are set in the node 20. The same bit value as the check bit is added to generate a routing bit 502, and a header section 500 including this is added to the payload section 600 and transmitted. In the present embodiment, for example, the bits of the virtual path identifier VPI and the virtual channel identifier VCI used in the node 20 are successively arranged in the upper bits or the lower bits of the routing bits 502 and are transmitted sequentially.

Next, the node 20 that has received the ATM cell from the node 10 via the transmission line,
Disassemble the cell and check the normality of the cell. First, in the ATM cell, the disassembly circuit 102 sets the routing bit 502 including the virtual path identifier VPI and the virtual channel identifier VCI to AT
The data is separated from the M cells and sequentially stored in the VPI / VCI buffer 104. The accumulated routing bits 502 are sequentially read out to the comparison circuit 506 and are read out by the check bit buffer 10.
Compared with the check bit from 6. In this case, the check bits are sequentially compared with the bit values of the unused virtual path identifier VPI and the virtual channel identifier VCI arranged in the lower bit or the upper bit of the routing bit 502.

If the result of comparison by the comparison circuit 108 does not match, the received fixed-length cell is regarded as invalid and discarded. On the other hand, if they match, node 20
The valid bits of the virtual path identifier VPI and the virtual channel identifier VCI used in are added to the payload from the separation circuit 102 and output to the ATM switch 200. Next, the ATM switch 200 that has received a valid ATM cell performs high-speed fixed-length cell routing processing based on the valid bits of the virtual path identifier VPI and the virtual channel identifier VCI used in its own node. The ATM cell routed by the ATM switch 200 is assembled into the original fixed-length cell of 53 bytes by the ATM cell assembling unit 300 as in the case of the node 10, and is transferred to a predetermined route.

Similarly, a check bit having the same value as an unused bit is previously set in the check bit buffer 106 at the receiving node, and the ATM cell assembling section 300 at the transmitting node uses the check bit in the next node. The bit is transmitted at a predetermined bit position of the routing bit 502. As a result, the receiving node effectively checks the routing bit 502 and the check bit separated from the received ATM cell by the comparison circuit 108 and transfers them to the ATM switch 200 when they match. As a result, AT
The M-switch 200 effectively switches the ATM cell to a desired route by a high-speed routing process using only valid bits.

As described above, according to the present embodiment, the effective bits of the virtual path identifier VPI and the virtual channel identifier VCI used in advance in each of the nodes 10 and 20 out of the routing bits 502 of the header section 500 of the ATM cell. And unused bits are set in predetermined bit positions,
By comparing the virtual path identifier VPI and virtual channel identifier VCI not used by the receiving side with the prepared check bit, it is determined whether to perform logical channel conversion or discard the logical channel. As a result, the ATM switch 200 determines the virtual path identifier VPI determined for the routing process.
In addition, the number of bits used for the virtual channel identifier VCI can be reduced. Therefore, the processing can be performed at a higher speed as compared with the case where the routing processing is performed using the routing bit 502 including the invalid bit.

Next, FIG. 5 shows a second embodiment of the asynchronous transfer mode communication system, the asynchronous transfer mode communication system, and the cell decomposer according to the present invention. In this figure, the difference from the above embodiment is that the virtual path identifier VPI and the virtual channel identifier VCI to be used are arranged at arbitrary bit positions of the routing bit 502 at the transmitting node, and The point is that the unused virtual path identifier VPI and the unused virtual channel identifier VCI are separated and extracted from the received routing bits 502, and are compared with the check bits.

For example, FIG.
The ATM cell assembler 300 of 0,20 places the used bits of the virtual path identifier VPI and the virtual channel identifier VCI in the upper bits of the routing bit 502 and transmits the ATM cell to the VPI / VCI buffer 104 of the receiving node. An example in the case where it is stored is shown. In this case, the receiving node separates and reads out the lower bits of the buffer 104, that is, the bits of the virtual path identifier VPI and the virtual channel identifier VCI that are not used in the own node, from the used bits, and supplies them to the comparison circuit. The comparison circuit 108 compares the unused bits from the buffer 104 with the check bit buffer 10
6 and compare the check bits from the
And outputs an instruction to perform logical channel conversion. If they do not match, an instruction to discard the used bits of the buffer 104 and the separated payload section 600 is output. In this example, the bits used are routing bits 502
In the description given above, an example is given in which unused bits are assigned to lower bits in the upper bits of this example. However, in this embodiment, the bit positions of unused bits are set in advance at each node, and By setting the read position in the node in advance, the unused bits to be compared with the check bits are effectively read and compared.

As described above, according to the present embodiment, the unused bit arranged at an arbitrary bit position from the transmission side is separated from the used bit and is compared with the check bit. , The comparison process can be executed quickly and accurately.

FIG. 6 shows a third embodiment of the asynchronous transfer mode communication system, the asynchronous transfer mode communication system, and the cell decomposer according to the present invention. In this figure, the difference from the first embodiment and the second embodiment is that the virtual path identifier is
The bits used by the VPI and the virtual channel identifier VCI are transmitted in a state where the bits are divided into arbitrary bit positions and arbitrary bit widths of the routing bit 502, and the receiving node receiving the transmission bit 502 separates the routing bit 502 from the ATM cell. Of these, the bit position and bit width of the virtual path identifier VPI and virtual channel identifier VCI used in this node are masked, and the masked routing bit 502, that is, the unused bit and the check bit are compared. is there.

For example, FIG.
The ATM cell assembler 300 of 0,20 divides the used bits of the virtual path identifier VPI and the virtual channel identifier VCI into three places of the upper, middle and lower bits of the routing bit 502, and arranges the bits by several bits and transmits the divided bits. An example is shown in which an ATM cell is stored in a VPI / VCI buffer 104 at a receiving node. In this case, VPI / VC
Upper of the routing bits 502 from the I-buffer 104,
A mask circuit such as a random access memory (RAM) that stores the mask bits for masking the middle and lower bits
110 are provided. As a result, in order to compare the virtual path identifier VPI and the virtual channel identifier VCI which are not used in the own node, the receiving node uses a mask bit indicating which bit is to be checked in addition to the check bit in the mask circuit 110. The width of the check bit and the position of the check bit are set in advance.

In this state, the transmitting node allocates the unused bits and the bits of the virtual path identifier VPI and the virtual channel identifier VCI to be used to the routing bits 502 as described above. In this case, the allocation methods need not be consecutive as in the first and second embodiments, but may be any bit position and any bit width, and one virtual path identifier VPI and one virtual channel identifier are used.
It suffices that one assignment is performed for the VCI bit value. Routing bit 50 allocated in this way
2 is added to the payload section 600 and the AT
Send M cells.

Upon receiving this, the receiving node obtains the virtual path identifier VPI and the virtual channel identifier VCI from the ATM cell.
When separated from the ATM cell, the mask bits from the mask circuit 110, which store the allocation as described above, and the routing bits from the VPI / VCI buffer 104 are read, and the virtual path identifier VPI and the virtual channel identifier VCI are read. Mask the bits used. Next, the masked virtual path identifier VPI and virtual channel identifier VCI
Is compared with a check bit by a comparison circuit 108 to determine a match / mismatch. As a result, if they match, logical channel conversion of the virtual path identifier VPI and virtual channel identifier VCI to be used is performed, and if they do not match, the used virtual path identifier VPI and virtual channel identifier VCI are discarded together with the payload section 600. .

As described above, according to the third embodiment of the present invention, the bit positions and bit widths of the virtual path identifier VPI and the virtual channel identifier VCI of the header section 500 of the ATM cell are previously associated between transmission and reception. Accordingly, it is possible to more reliably determine the match / mismatch between the unused virtual path identifier VPI and the unused virtual path identifier VCI for an arbitrary bit position and an arbitrary bit width.
This can reduce the number of bits used for the virtual path identifier (VPI) and the virtual channel identifier (VCI).

The above embodiment is an example of the asynchronous transfer mode communication system, the cell separation device, and the asynchronous transfer mode communication system according to the present invention, and the present invention is not limited to these embodiments. Modifications and aspects that do not depart from the scope of the claims are included in the present invention.

[0048]

As described above in detail, according to the asynchronous transfer mode communication system, the asynchronous transfer mode communication system, and the cell disassembly apparatus of the present invention, the routing bits are separated from the header of the received fixed-length cell and used. By comparing the virtual path identifier and the virtual channel identifier with a check bit set in advance, the normality of the routing bit is confirmed, and if it is normal, the virtual path identifier and the virtual channel identifier with fewer bits to be used are used. Since the routing process is performed, there is an effect that the routing process in each node can be executed smoothly and in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an asynchronous transfer mode communication system and a cell disassembly device to which an asynchronous transfer mode communication method is applied according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an asynchronous transfer mode communication system to which the cell disassembly device according to the embodiment of FIG. 1 is applied;

FIG. 3 is a format diagram showing an ATM cell applied to the asynchronous transfer mode communication system according to the embodiment of FIG. 1;

FIG. 4 is a conceptual diagram showing a connection relationship of an asynchronous transfer mode communication network to which the asynchronous transfer mode communication system according to the embodiment of FIG. 1 is applied;

FIG. 5 is a block diagram showing a second embodiment of the asynchronous transfer mode communication system, the asynchronous transfer mode communication method, and the cell disassembly device according to the present invention.

FIG. 6 is a block diagram showing a third embodiment of the asynchronous transfer mode communication system, the asynchronous transfer mode communication method, and the cell disassembly device according to the present invention.

[Explanation of symbols]

 10,20, NA to NN node 100 ATM cell decomposition unit 102 Separation circuit 104 VPI / VCI buffer 106 Check bit buffer 108 Comparison circuit 110 Mask circuit 200 ATM switch 300 ATM cell assembly unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-8916 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (12)

(57) [Claims] 1. An asynchronous transfer mode for assembling information into cells of a fixed bit length and transferring these fixed length cells between respective nodes via virtual paths and virtual channels set according to the amount of information and the route. In a communication system, the system includes a cell assembling means for assembling a fixed length cell by adding a routing bit including a virtual path identifier and a virtual channel identifier having a fixed bit length to a header of the cell, and a fixed length cell received from another node. A header separating unit that separates a header and analyzes a routing bit thereof; and a routing unit that performs a cell routing process based on the routing bit, wherein the header separating unit includes a virtual path identifier among the separated headers. And sequentially storing routing bits including virtual channel identifiers Storage means; second storage means for storing preset check bits for confirming the normality of the routing bits stored in the first storage means; and routing bits from the first storage means. And comparing means for sequentially comparing the check bits from the second storage means with the virtual path identifier which is not used in its own node among the routing bits from the first storage means. A plurality of bits of a virtual channel identifier are compared with the check bits to detect a match or mismatch, and the system discards a fixed-length cell when the result of the comparing means does not match, and Routing processing is performed by the routing means based on bits used for a virtual path identifier and a virtual channel identifier. Asynchronous transfer mode communication system. 2. The asynchronous transfer mode communication system according to claim 1, wherein the use bits of the virtual path identifier and the virtual channel identifier at each node are continuous with the upper or lower bits of the routing bits at the transmitting node. The comparing means, when comparing the routing bits from the first storage means with the check bits from the second storage means, includes a virtual path identifier and a virtual channel at the node. An asynchronous transfer mode communication system comprising comparing a lower or upper bit of a routing bit excluding a use bit of an identifier with a check bit to confirm the normality of the routing bit. 3. The asynchronous transfer mode communication system according to claim 1, wherein bits used for a virtual path identifier and a virtual channel identifier at each node are arranged at predetermined bit positions of routing bits at a transmitting node. The comparing means compares the routing bit from the first storage means with the check bit from the second storage means, and compares the routing bit from the first storage means with a node among the routing bits from the first storage means. Extracting the bits of the unused virtual path identifier and virtual channel identifier from predetermined positions of the routing bits and comparing the extracted unused virtual path identifier and virtual channel identifier with the check bit. Transfer mode communication system. 4. The asynchronous transfer mode communication system according to claim 1, wherein the use bits of the virtual path identifier and the virtual channel identifier at each node are set at an arbitrary bit position and an arbitrary bit of the routing bit at the transmitting node. Transmitted in bit widths, the system comprises:
Of the routing bits from the first storage means,
Mask means for masking bit positions and bit widths of virtual path identifiers and virtual channel identifiers used in the node, wherein the comparing means compares the routing bits masked by the masking means with the check bits An asynchronous transfer mode communication system, comprising: 5. A header separating apparatus for separating a header from a fixed-length cell received from another node and analyzing its routing bit, wherein the apparatus includes a virtual path identifier and a virtual channel identifier among the separated headers. First storage means for sequentially storing routing bits, second storage means for storing preset check bits for confirming the normality of the routing bits stored in the first storage means, A cell disassembly device comprising: comparing means for sequentially comparing a routing bit from a first storage means and a check bit from the second storage means. 6. The cell disassembly device according to claim 5, wherein said comparing means transmits a comparison result when comparing a routing bit from said first storage means with a check bit from said second storage means. At the side node, check the validity of the routing bit by comparing unused bits of the virtual path identifier and virtual channel identifier arranged consecutively to the lower or upper bits of the routing bit with the check bit. Characterized cell disassembly device. 7. The cell disassembly device according to claim 5, wherein the device is arranged at a predetermined bit position of the routing bit at a transmission side node among the routing bits from the first storage means. Unused bits of the virtual path identifier and the virtual channel identifier are extracted and sent to the comparing means, and the comparing means checks the extracted unused bits of the virtual path identifier and the virtual channel identifier from the second storage means. A cell disassembly device that compares a bit with a cell. 8. The cell disassembly device according to claim 5, wherein the device is configured to transmit a virtual path identifier and a virtual path distributed at an arbitrary bit position and an arbitrary bit width of a routing bit by a transmitting node. Cell disassembly comprising masking means for masking use bits of a channel identifier, wherein said comparing means compares routing bits masked by said masking means with check bits from said second storage means. apparatus. 9. An asynchronous transfer mode in which information is assembled into cells of a fixed bit length and these fixed length cells are transferred between respective nodes via virtual paths and virtual channels set according to the amount of information and the route. In the communication method, the method uses the number of bits of a virtual path identifier and a virtual channel identifier actually used in routing for each set virtual path and virtual channel at each node and the number of unused bits. A first step of transmitting a preset bit value by assigning a predetermined bit value to an unused bit, and the same bit as an unused virtual path identifier and a virtual channel identifier at each node receiving the fixed-length cell. A second step of setting the number of check bits, and a virtual path identifier from the header of the received fixed-length cell. A third step of separating and storing routing bits including a virtual channel identifier and a virtual path identifier and a virtual channel identifier that are not used by the node among the routing bits stored in the third step; A fourth step of comparing the check bit set in the second step with the check bit; discarding the fixed-length cell received when the result does not match; and a virtual path identifier used by the node when the result matches. And a fifth step of routing fixed-length cells based on the virtual channel identifier. 10. The asynchronous transfer mode communication system according to claim 9, wherein said first step includes arranging a virtual path identifier and a virtual channel identifier to be used continuously in upper or lower bits of a routing bit. Send,
The fourth step is to compare the lower or upper bits of the routing bits except the bits used for the virtual path identifier and the virtual channel identifier at the node with the check bits to confirm the normality of the routing bits. Characteristic asynchronous transfer mode communication method. 11. The asynchronous transfer mode communication system according to claim 9, wherein the first step arranges and transmits a virtual path identifier and a virtual channel identifier to be used at an arbitrary bit position of a routing bit, The receiving node extracts a virtual path identifier and a virtual channel identifier not used by the node from the routing bits separated in the third step, and outputs the extracted bit and the check bit in the fourth step to the fourth step. The asynchronous transfer mode communication method characterized in that the comparison is performed in the steps of: 12. The asynchronous transfer mode communication system according to claim 9, wherein said first step divides a virtual path identifier and a virtual channel identifier to be used into arbitrary bit positions and arbitrary bit widths of routing bits. Transmitting, and the receiving node includes a step of masking, in the separated routing bits, bits in which a virtual path identifier and a virtual channel identifier used in the node are arranged, and the fourth step includes: An asynchronous transfer mode communication method, wherein a masked routing bit and a check bit are compared.